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source: rtems/cpukit/score/cpu/m68k/rtems/score/cpu.h @ da42259

4.104.115

Last change on this file since da42259 was da42259, checked in by Thomas Doerfler <Thomas.Doerfler@…>, on 08/24/09 at 10:29:10
Define M68K_FP_STATE_SIZE also if used in assembler files.
Property mode set to `100644`
File size: 20.7 KB

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1	/**
2	* @file rtems/score/cpu.h
3	*/
4
5	/*
6	* This include file contains information pertaining to the Motorola
7	* m68xxx processor family.
8	*
9	* COPYRIGHT (c) 1989-2006.
10	* On-Line Applications Research Corporation (OAR).
11	*
12	* The license and distribution terms for this file may be
13	* found in the file LICENSE in this distribution or at
14	* http://www.rtems.com/license/LICENSE.
15	*
16	* $Id$
17	*/
18
19	#ifndef _RTEMS_SCORE_CPU_H
20	#define _RTEMS_SCORE_CPU_H
21
22	#ifdef __cplusplus
23	extern "C" {
24	#endif
25
26	#include <rtems/score/m68k.h> /* pick up machine definitions */
27	#ifndef ASM
28	#include <rtems/score/types.h>
29	#else
30	/* FIXME */
31	#define TRUE 1
32	#define FALSE 0
33	#endif
34
35	/* conditional compilation parameters */
36
37	#define CPU_INLINE_ENABLE_DISPATCH TRUE
38	#define CPU_UNROLL_ENQUEUE_PRIORITY FALSE
39
40	/*
41	* Does the CPU follow the simple vectored interrupt model?
42	*
43	* If TRUE, then RTEMS allocates the vector table it internally manages.
44	* If FALSE, then the BSP is assumed to allocate and manage the vector
45	* table
46	*
47	* M68K Specific Information:
48	*
49	* XXX document implementation including references if appropriate
50	*/
51	#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
52
53	/*
54	* Use the m68k's hardware interrupt stack support and have the
55	* interrupt manager allocate the memory for it.
56	*/
57
58	#if ( M68K_HAS_SEPARATE_STACKS == 1)
59	#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 0
60	#define CPU_HAS_HARDWARE_INTERRUPT_STACK 1
61	#else
62	#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 1
63	#define CPU_HAS_HARDWARE_INTERRUPT_STACK 0
64	#endif
65	#define CPU_ALLOCATE_INTERRUPT_STACK 1
66
67	/*
68	* Does the RTEMS invoke the user's ISR with the vector number and
69	* a pointer to the saved interrupt frame (1) or just the vector
70	* number (0)?
71	*/
72
73	#define CPU_ISR_PASSES_FRAME_POINTER 0
74
75	/*
76	* Some family members have no FP, some have an FPU such as the
77	* MC68881/MC68882 for the MC68020, others have it built in (MC68030, 040).
78	*
79	* NOTE: If on a CPU without hardware FP, then one can use software
80	* emulation. The gcc software FP emulation code has data which
81	* must be contexted switched on a per task basis.
82	*/
83
84	#if ( M68K_HAS_FPU == 1 ) \|\| ( M68K_HAS_EMAC == 1 )
85	#define CPU_HARDWARE_FP TRUE
86	#define CPU_SOFTWARE_FP FALSE
87	#else
88	#define CPU_HARDWARE_FP FALSE
89	#if defined( __GNUC__ )
90	#define CPU_SOFTWARE_FP TRUE
91	#else
92	#define CPU_SOFTWARE_FP FALSE
93	#endif
94	#endif
95
96	/*
97	* All tasks are not by default floating point tasks on this CPU.
98	* The IDLE task does not have a floating point context on this CPU.
99	* It is safe to use the deferred floating point context switch
100	* algorithm on this CPU.
101	*/
102
103	#define CPU_ALL_TASKS_ARE_FP FALSE
104	#define CPU_IDLE_TASK_IS_FP FALSE
105	#define CPU_USE_DEFERRED_FP_SWITCH TRUE
106
107	#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE
108	#define CPU_STACK_GROWS_UP FALSE
109	#define CPU_STRUCTURE_ALIGNMENT
110
111	/*
112	* Define what is required to specify how the network to host conversion
113	* routines are handled.
114	*/
115
116	#define CPU_BIG_ENDIAN TRUE
117	#define CPU_LITTLE_ENDIAN FALSE
118
119	#if ( CPU_HARDWARE_FP == TRUE ) && !defined( __mcoldfire__ )
120	#if defined( __mc68060__ )
121	#define M68K_FP_STATE_SIZE 16
122	#else
123	#define M68K_FP_STATE_SIZE 216
124	#endif
125	#endif
126
127	#ifndef ASM
128
129	/* structures */
130
131	/*
132	* Basic integer context for the m68k family.
133	*/
134
135	typedef struct {
136	uint32_t sr; /* (sr) status register */
137	uint32_t d2; /* (d2) data register 2 */
138	uint32_t d3; /* (d3) data register 3 */
139	uint32_t d4; /* (d4) data register 4 */
140	uint32_t d5; /* (d5) data register 5 */
141	uint32_t d6; /* (d6) data register 6 */
142	uint32_t d7; /* (d7) data register 7 */
143	void a2; / (a2) address register 2 */
144	void a3; / (a3) address register 3 */
145	void a4; / (a4) address register 4 */
146	void a5; / (a5) address register 5 */
147	void a6; / (a6) address register 6 */
148	void a7_msp; / (a7) master stack pointer */
149	#if defined( __mcoldfire__ ) && ( M68K_HAS_FPU == 1 )
150	uint8_t fpu_dis;
151	#endif
152	} Context_Control;
153
154	#define _CPU_Context_Get_SP( _context ) \
155	(_context)->a7_msp
156
157	/*
158	* Floating point context areas and support routines
159	*/
160
161	#if ( CPU_SOFTWARE_FP == TRUE )
162	/*
163	* This is the same as gcc's view of the software FP condition code
164	* register _fpCCR. The implementation of the emulation code is
165	* in the gcc-VERSION/config/m68k directory. This structure is
166	* correct as of gcc 2.7.2.2.
167	*/
168	typedef struct {
169	uint16_t _exception_bits;
170	uint16_t _trap_enable_bits;
171	uint16_t _sticky_bits;
172	uint16_t _rounding_mode;
173	uint16_t _format;
174	uint16_t _last_operation;
175	union {
176	float sf;
177	double df;
178	} _operand1;
179	union {
180	float sf;
181	double df;
182	} _operand2;
183	} Context_Control_fp;
184
185	/*
186	* This software FP implementation is only for GCC.
187	*/
188	#define _CPU_Context_Fp_start( _base, _offset ) \
189	((void *) _Addresses_Add_offset( (_base), (_offset) ) )
190
191	#define _CPU_Context_Initialize_fp( _fp_area ) \
192	{ \
193	Context_Control_fp *_fp; \
194	_fp = (Context_Control_fp *)_fp_area; \
195	_fp->_exception_bits = 0; \
196	_fp->_trap_enable_bits = 0; \
197	_fp->_sticky_bits = 0; \
198	_fp->_rounding_mode = 0; /* ROUND_TO_NEAREST */ \
199	_fp->_format = 0; /* NIL */ \
200	_fp->_last_operation = 0; /* NOOP */ \
201	_fp->_operand1.df = 0; \
202	_fp->_operand2.df = 0; \
203	}
204	#endif
205
206	#if ( CPU_HARDWARE_FP == TRUE )
207	#if defined( __mcoldfire__ )
208	/* We need memset() to initialize the FP context */
209	#include <string.h>
210
211	#if ( M68K_HAS_FPU == 1 )
212	/*
213	* The Cache Control Register (CACR) has write-only access. It is also
214	* used to enable and disable the FPU. We need to maintain a copy of
215	* this register to allow per thread values.
216	*/
217	extern uint32_t _CPU_cacr_shadow;
218	#endif
219
220	/* We assume that each ColdFire core with a FPU has also an EMAC unit */
221	typedef struct {
222	uint32_t emac_macsr;
223	uint32_t emac_acc0;
224	uint32_t emac_acc1;
225	uint32_t emac_acc2;
226	uint32_t emac_acc3;
227	uint32_t emac_accext01;
228	uint32_t emac_accext23;
229	uint32_t emac_mask;
230	#if ( M68K_HAS_FPU == 1 )
231	uint16_t fp_state_format;
232	uint16_t fp_state_fpcr;
233	double fp_state_op;
234	uint32_t fp_state_fpsr;
235
236	/*
237	* We need to save the FP Instruction Address Register (FPIAR), because
238	* a context switch can occur within a FP exception before the handler
239	* was able to save this register.
240	*/
241	uint32_t fp_fpiar;
242
243	double fp_data [8];
244	#endif
245	} Context_Control_fp;
246
247	#define _CPU_Context_Fp_start( _base, _offset ) \
248	((void *) _Addresses_Add_offset( (_base), (_offset) ))
249
250	/*
251	* The reset value for all context relevant registers except the FP data
252	* registers is zero. The reset value of the FP data register is NAN. The
253	* restore of the reset FP state will reset the FP data registers, so the
254	* initial value of them can be arbitrary here.
255	*/
256	#define _CPU_Context_Initialize_fp( _fp_area ) \
257	memset( *(_fp_area), 0, sizeof( Context_Control_fp ) )
258	#else
259	/*
260	* FP context save area for the M68881/M68882 and 68060 numeric coprocessors.
261	*/
262
263	typedef struct {
264	/*
265	* M68K_FP_STATE_SIZE bytes for FSAVE/FRESTORE
266	* 96 bytes for FMOVEM FP0-7
267	* 12 bytes for FMOVEM CREGS
268	* 4 bytes for non-null flag
269	*/
270	uint8_t fp_save_area [M68K_FP_STATE_SIZE + 112];
271	} Context_Control_fp;
272
273	#define _CPU_Context_Fp_start( _base, _offset ) \
274	( \
275	(void *) _Addresses_Add_offset( \
276	(_base), \
277	(_offset) + CPU_CONTEXT_FP_SIZE - 4 \
278	) \
279	)
280
281	#define _CPU_Context_Initialize_fp( _fp_area ) \
282	{ \
283	uint32_t _fp_context = (uint32_t )*(_fp_area); \
284	*(--(_fp_context)) = 0; \
285	(_fp_area) = (void )(_fp_context); \
286	}
287	#endif
288	#endif
289
290	/*
291	* The following structures define the set of information saved
292	* on the current stack by RTEMS upon receipt of each exc/interrupt.
293	* These are not used by m68k handlers.
294	* The exception frame is for rdbg.
295	*/
296
297	typedef struct {
298	uint32_t vecnum; /* vector number */
299	} CPU_Interrupt_frame;
300
301	typedef struct {
302	uint32_t vecnum; /* vector number */
303	uint32_t sr; /* status register */
304	uint32_t pc; /* program counter */
305	uint32_t d0, d1, d2, d3, d4, d5, d6, d7;
306	uint32_t a0, a1, a2, a3, a4, a5, a6, a7;
307	} CPU_Exception_frame;
308
309	/* variables */
310
311	SCORE_EXTERN void *_CPU_Interrupt_stack_low;
312	SCORE_EXTERN void *_CPU_Interrupt_stack_high;
313
314	extern void* _VBR;
315
316	#if ( M68K_HAS_VBR == 0 )
317
318	/*
319	* Table of ISR handler entries that resides in RAM. The FORMAT/ID is
320	* pushed onto the stack. This is not is the same order as VBR processors.
321	* The ISR handler takes the format and uses it for dispatching the user
322	* handler.
323	*
324	* FIXME : should be moved to below CPU_INTERRUPT_NUMBER_OF_VECTORS
325	*
326	*/
327
328	typedef struct {
329	uint16_t move_a7; /* move #FORMAT_ID,%a7@- */
330	uint16_t format_id;
331	uint16_t jmp; /* jmp _ISR_Handlers */
332	uint32_t isr_handler;
333	} _CPU_ISR_handler_entry;
334
335	#define M68K_MOVE_A7 0x3F3C
336	#define M68K_JMP 0x4EF9
337
338	/* points to jsr-exception-table in targets wo/ VBR register */
339	SCORE_EXTERN _CPU_ISR_handler_entry _CPU_ISR_jump_table[256];
340
341	#endif /* M68K_HAS_VBR */
342
343	#endif /* ASM */
344
345	/* constants */
346
347	/*
348	* This defines the number of levels and the mask used to pick those
349	* bits out of a thread mode.
350	*/
351
352	#define CPU_MODES_INTERRUPT_LEVEL 0x00000007 /* interrupt level in mode */
353	#define CPU_MODES_INTERRUPT_MASK 0x00000007 /* interrupt level in mode */
354
355	/*
356	* context size area for floating point
357	*/
358
359	#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
360
361	/*
362	* extra stack required by the MPCI receive server thread
363	*/
364
365	#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
366
367	/*
368	* m68k family supports 256 distinct vectors.
369	*/
370
371	#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256
372	#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
373
374	/*
375	* This is defined if the port has a special way to report the ISR nesting
376	* level. Most ports maintain the variable _ISR_Nest_level.
377	*/
378
379	#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
380
381	/*
382	* Minimum size of a thread's stack.
383	*/
384
385	#define CPU_STACK_MINIMUM_SIZE M68K_CPU_STACK_MINIMUM_SIZE
386
387	/*
388	* Maximum priority of a thread. Note based from 0 which is the idle task.
389	*/
390	#define CPU_PRIORITY_MAXIMUM M68K_CPU_PRIORITY_MAXIMUM
391
392	/*
393	* m68k is pretty tolerant of alignment. Just put things on 4 byte boundaries.
394	*/
395
396	#define CPU_ALIGNMENT 4
397	#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
398	#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
399
400	/*
401	* On m68k thread stacks require no further alignment after allocation
402	* from the Workspace.
403	*/
404
405	#define CPU_STACK_ALIGNMENT 0
406
407	#ifndef ASM
408
409	/* macros */
410
411	/*
412	* ISR handler macros
413	*
414	* These macros perform the following functions:
415	* + initialize the RTEMS vector table
416	* + disable all maskable CPU interrupts
417	* + restore previous interrupt level (enable)
418	* + temporarily restore interrupts (flash)
419	* + set a particular level
420	*/
421
422	#define _CPU_Initialize_vectors()
423
424	#define _CPU_ISR_Disable( _level ) \
425	m68k_disable_interrupts( _level )
426
427	#define _CPU_ISR_Enable( _level ) \
428	m68k_enable_interrupts( _level )
429
430	#define _CPU_ISR_Flash( _level ) \
431	m68k_flash_interrupts( _level )
432
433	#define _CPU_ISR_Set_level( _newlevel ) \
434	m68k_set_interrupt_level( _newlevel )
435
436	uint32_t _CPU_ISR_Get_level( void );
437
438	/* end of ISR handler macros */
439
440	/*
441	* Context handler macros
442	*
443	* These macros perform the following functions:
444	* + initialize a context area
445	* + restart the current thread
446	* + calculate the initial pointer into a FP context area
447	* + initialize an FP context area
448	*/
449
450	#if (defined(__mcoldfire__) && ( M68K_HAS_FPU == 1 ))
451	#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
452	_isr, _entry_point, _is_fp ) \
453	do { \
454	uint32_t _stack; \
455	\
456	(_the_context)->sr = 0x3000 \| ((_isr) << 8); \
457	_stack = (uint32_t)(_stack_base) + (_size) - 4; \
458	(_the_context)->a7_msp = (void *)_stack; \
459	(void )_stack = (void )(_entry_point); \
460	(_the_context)->fpu_dis = (_is_fp == TRUE) ? 0x00 : 0x10; \
461	} while ( 0 )
462	#else
463	#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
464	_isr, _entry_point, _is_fp ) \
465	do { \
466	uint32_t _stack; \
467	\
468	(_the_context)->sr = 0x3000 \| ((_isr) << 8); \
469	_stack = (uint32_t )(_stack_base) + (_size) - 4; \
470	(_the_context)->a7_msp = (void *)_stack; \
471	(void )_stack = (void )(_entry_point); \
472	} while ( 0 )
473	#endif
474
475	#define _CPU_Context_Restart_self( _the_context ) \
476	{ asm volatile( "movew %0,%%sr ; " \
477	"moval %1,%%a7 ; " \
478	"rts" \
479	: "=d" ((_the_context)->sr), "=d" ((_the_context)->a7_msp) \
480	: "0" ((_the_context)->sr), "1" ((_the_context)->a7_msp) ); \
481	}
482
483	/* end of Context handler macros */
484
485	/*
486	* _CPU_Thread_Idle_body
487	*
488	* This routine is the CPU dependent IDLE thread body.
489	*
490	* NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
491	* is TRUE.
492	*/
493
494	void *_CPU_Thread_Idle_body( uintptr_t ignored );
495
496	/*
497	* Fatal Error manager macros
498	*
499	* These macros perform the following functions:
500	* + disable interrupts and halt the CPU
501	*/
502
503	#if ( defined(__mcoldfire__) )
504	#define _CPU_Fatal_halt( _error ) \
505	{ asm volatile( "move.w %%sr,%%d0\n\t" \
506	"or.l %2,%%d0\n\t" \
507	"move.w %%d0,%%sr\n\t" \
508	"move.l %1,%%d0\n\t" \
509	"move.l #0xDEADBEEF,%%d1\n\t" \
510	"halt" \
511	: "=g" (_error) \
512	: "0" (_error), "d"(0x0700) \
513	: "d0", "d1" ); \
514	}
515	#else
516	#define _CPU_Fatal_halt( _error ) \
517	{ asm volatile( "movl %0,%%d0; " \
518	"orw #0x0700,%%sr; " \
519	"stop #0x2700" : "=d" ((_error)) : "0" ((_error)) ); \
520	}
521	#endif
522
523	/* end of Fatal Error manager macros */
524
525	/*
526	* Bitfield handler macros
527	*
528	* These macros perform the following functions:
529	* + scan for the highest numbered (MSB) set in a 16 bit bitfield
530	*
531	* NOTE:
532	*
533	* It appears that on the M68020 bitfield are always 32 bits wide
534	* when in a register. This code forces the bitfield to be in
535	* memory (it really always is anyway). This allows us to
536	* have a real 16 bit wide bitfield which operates "correctly."
537	*/
538
539	#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
540	#define CPU_USE_GENERIC_BITFIELD_DATA FALSE
541
542	#if ( M68K_HAS_BFFFO != 1 )
543	/*
544	* Lookup table for BFFFO simulation
545	*/
546	extern const unsigned char _CPU_m68k_BFFFO_table[256];
547	#endif
548
549	#if ( M68K_HAS_BFFFO == 1 )
550
551	#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
552	asm volatile( "bfffo (%1),#0,#16,%0" : "=d" (_output) : "a" (&_value));
553
554	#elif ( __mcfisaaplus__ )
555	/* This is simplified by the fact that RTEMS never calls it with _value=0 */
556	#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
557	asm volatile ( \
558	" swap %0\n" \
559	" ff1.l %0\n" \
560	: "=d" ((_output)) \
561	: "0" ((_value)) \
562	: "cc" ) ;
563
564	#else
565	/* duplicates BFFFO results for 16 bits (i.e., 15-(_priority) in
566	_CPU_Priority_bits_index is not needed), handles the 0 case, and
567	does not molest _value -- jsg */
568	#if ( defined(__mcoldfire__) )
569
570	#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
571	{ \
572	register int dumby; \
573	\
574	asm volatile ( \
575	" clr.l %1\n" \
576	" move.w %2,%1\n" \
577	" lsr.l #8,%1\n" \
578	" beq.s 1f\n" \
579	" move.b (%3,%1),%0\n" \
580	" bra.s 0f\n" \
581	"1: move.w %2,%1\n" \
582	" move.b (%3,%1),%0\n" \
583	" addq.l #8,%0\n" \
584	"0: and.l #0xff,%0\n" \
585	: "=&d" ((_output)), "=&d" ((dumby)) \
586	: "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \
587	: "cc" ) ; \
588	}
589	#elif ( M68K_HAS_EXTB_L == 1 )
590	#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
591	{ \
592	register int dumby; \
593	\
594	asm volatile ( " move.w %2,%1\n" \
595	" lsr.w #8,%1\n" \
596	" beq.s 1f\n" \
597	" move.b (%3,%1.w),%0\n" \
598	" extb.l %0\n" \
599	" bra.s 0f\n" \
600	"1: moveq.l #8,%0\n" \
601	" add.b (%3,%2.w),%0\n" \
602	"0:\n" \
603	: "=&d" ((_output)), "=&d" ((dumby)) \
604	: "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \
605	: "cc" ) ; \
606	}
607	#else
608	#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
609	{ \
610	register int dumby; \
611	\
612	asm volatile ( " move.w %2,%1\n" \
613	" lsr.w #8,%1\n" \
614	" beq.s 1f\n" \
615	" move.b (%3,%1.w),%0\n" \
616	" and.l #0x000000ff,%0\n"\
617	" bra.s 0f\n" \
618	"1: moveq.l #8,%0\n" \
619	" add.b (%3,%2.w),%0\n" \
620	"0:\n" \
621	: "=&d" ((_output)), "=&d" ((dumby)) \
622	: "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \
623	: "cc" ) ; \
624	}
625	#endif
626
627	#endif
628
629	/* end of Bitfield handler macros */
630
631	/*
632	* Priority handler macros
633	*
634	* These macros perform the following functions:
635	* + return a mask with the bit for this major/minor portion of
636	* of thread priority set.
637	* + translate the bit number returned by "Bitfield_find_first_bit"
638	* into an index into the thread ready chain bit maps
639	*/
640
641	#define _CPU_Priority_Mask( _bit_number ) \
642	( 0x8000 >> (_bit_number) )
643
644	#define _CPU_Priority_bits_index( _priority ) \
645	(_priority)
646
647	/* end of Priority handler macros */
648
649	/* functions */
650
651	/*
652	* _CPU_Initialize
653	*
654	* This routine performs CPU dependent initialization.
655	*/
656
657	void _CPU_Initialize(void);
658
659	/*
660	* _CPU_ISR_install_raw_handler
661	*
662	* This routine installs a "raw" interrupt handler directly into the
663	* processor's vector table.
664	*/
665
666	void _CPU_ISR_install_raw_handler(
667	uint32_t vector,
668	proc_ptr new_handler,
669	proc_ptr *old_handler
670	);
671
672	/*
673	* _CPU_ISR_install_vector
674	*
675	* This routine installs an interrupt vector.
676	*/
677
678	void _CPU_ISR_install_vector(
679	uint32_t vector,
680	proc_ptr new_handler,
681	proc_ptr *old_handler
682	);
683
684	/*
685	* _CPU_Install_interrupt_stack
686	*
687	* This routine installs the hardware interrupt stack pointer.
688	*/
689
690	void _CPU_Install_interrupt_stack( void );
691
692	/*
693	* _CPU_Context_switch
694	*
695	* This routine switches from the run context to the heir context.
696	*/
697
698	void _CPU_Context_switch(
699	Context_Control *run,
700	Context_Control *heir
701	);
702
703	/*
704	* _CPU_Context_save_fp
705	*
706	* This routine saves the floating point context passed to it.
707	*/
708
709	void _CPU_Context_save_fp(
710	Context_Control_fp **fp_context_ptr
711	);
712
713	/*
714	* _CPU_Context_restore_fp
715	*
716	* This routine restores the floating point context passed to it.
717	*/
718
719	void _CPU_Context_restore_fp(
720	Context_Control_fp **fp_context_ptr
721	);
722
723	#if (M68K_HAS_FPSP_PACKAGE == 1)
724	/*
725	* Hooks for the Floating Point Support Package (FPSP) provided by Motorola
726	*
727	* NOTES:
728	*
729	* Motorola 68k family CPU's before the 68040 used a coprocessor
730	* (68881 or 68882) to handle floating point. The 68040 has internal
731	* floating point support -- but not the complete support provided by
732	* the 68881 or 68882. The leftover functions are taken care of by the
733	* M68040 Floating Point Support Package. Quoting from the MC68040
734	* Microprocessors User's Manual, Section 9, Floating-Point Unit (MC68040):
735	*
736	* "When used with the M68040FPSP, the MC68040 FPU is fully
737	* compliant with IEEE floating-point standards."
738	*
739	* M68KFPSPInstallExceptionHandlers is in libcpu/m68k/MODEL/fpsp and
740	* is invoked early in the application code to ensure that proper FP
741	* behavior is installed. This is not left to the BSP to call, since
742	* this would force all applications using that BSP to use FPSP which
743	* is not necessarily desirable.
744	*
745	* There is a similar package for the 68060 but RTEMS does not yet
746	* support the 68060.
747	*/
748
749	void M68KFPSPInstallExceptionHandlers (void);
750
751	SCORE_EXTERN int (*_FPSP_install_raw_handler)(
752	uint32_t vector,
753	proc_ptr new_handler,
754	proc_ptr *old_handler
755	);
756
757	#endif
758
759
760	#endif
761
762	#ifdef __cplusplus
763	}
764	#endif
765
766	#endif

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