source: rtems/cpukit/score/cpu/m68k/rtems/score/cpu.h @ d86bae8

4.104.114.84.95
Last change on this file since d86bae8 was d86bae8, checked in by Ralf Corsepius <ralf.corsepius@…>, on 03/30/04 at 11:47:03

2004-03-30 Ralf Corsepius <ralf_corsepius@…>

  • cpu.c, m68302.h, rtems/score/cpu.h, rtems/score/m68k.h: Convert to using c99 fixed size types.
  • Property mode set to 100644
File size: 17.8 KB
Line 
1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the Motorola
4 *  m68xxx processor family.
5 *
6 *  COPYRIGHT (c) 1989-1999.
7 *  On-Line Applications Research Corporation (OAR).
8 *
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.rtems.com/license/LICENSE.
12 *
13 *  $Id$
14 */
15
16#ifndef __CPU_h
17#define __CPU_h
18
19#ifdef __cplusplus
20extern "C" {
21#endif
22
23#include <rtems/score/m68k.h>              /* pick up machine definitions */
24#ifndef ASM
25#include <rtems/score/types.h>
26#endif
27
28/* conditional compilation parameters */
29
30#define CPU_INLINE_ENABLE_DISPATCH       TRUE
31#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
32
33/*
34 *  Use the m68k's hardware interrupt stack support and have the
35 *  interrupt manager allocate the memory for it.
36 */
37
38#if ( M68K_HAS_SEPARATE_STACKS == 1)
39#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 0
40#define CPU_HAS_HARDWARE_INTERRUPT_STACK 1
41#else
42#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 1
43#define CPU_HAS_HARDWARE_INTERRUPT_STACK 0
44#endif
45#define CPU_ALLOCATE_INTERRUPT_STACK     1
46
47/*
48 *  Does the RTEMS invoke the user's ISR with the vector number and
49 *  a pointer to the saved interrupt frame (1) or just the vector
50 *  number (0)?
51 */
52
53#define CPU_ISR_PASSES_FRAME_POINTER 0
54
55/*
56 *  Some family members have no FP, some have an FPU such as the
57 *  MC68881/MC68882 for the MC68020, others have it built in (MC68030, 040).
58 *
59 *  NOTE:  If on a CPU without hardware FP, then one can use software
60 *         emulation.  The gcc software FP emulation code has data which
61 *         must be contexted switched on a per task basis.
62 */
63
64#if ( M68K_HAS_FPU == 1 )
65#define CPU_HARDWARE_FP     TRUE
66#define CPU_SOFTWARE_FP     FALSE
67#else
68#define CPU_HARDWARE_FP     FALSE
69#if defined(__GNUC__)
70#define CPU_SOFTWARE_FP     TRUE
71#else
72#define CPU_SOFTWARE_FP     FALSE
73#endif
74#endif
75
76/*
77 *  All tasks are not by default floating point tasks on this CPU.
78 *  The IDLE task does not have a floating point context on this CPU.
79 *  It is safe to use the deferred floating point context switch
80 *  algorithm on this CPU.
81 */
82
83#define CPU_ALL_TASKS_ARE_FP             FALSE
84#define CPU_IDLE_TASK_IS_FP              FALSE
85#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
86
87#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
88#define CPU_STACK_GROWS_UP               FALSE
89#define CPU_STRUCTURE_ALIGNMENT
90
91/*
92 *  Define what is required to specify how the network to host conversion
93 *  routines are handled.
94 */
95
96#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
97#define CPU_BIG_ENDIAN                           TRUE
98#define CPU_LITTLE_ENDIAN                        FALSE
99
100#ifndef ASM
101/* structures */
102
103/*
104 *  Basic integer context for the m68k family.
105 */
106
107typedef struct {
108  uint32_t    sr;                /* (sr) status register */
109  uint32_t    d2;                /* (d2) data register 2 */
110  uint32_t    d3;                /* (d3) data register 3 */
111  uint32_t    d4;                /* (d4) data register 4 */
112  uint32_t    d5;                /* (d5) data register 5 */
113  uint32_t    d6;                /* (d6) data register 6 */
114  uint32_t    d7;                /* (d7) data register 7 */
115  void       *a2;                /* (a2) address register 2 */
116  void       *a3;                /* (a3) address register 3 */
117  void       *a4;                /* (a4) address register 4 */
118  void       *a5;                /* (a5) address register 5 */
119  void       *a6;                /* (a6) address register 6 */
120  void       *a7_msp;            /* (a7) master stack pointer */
121}   Context_Control;
122
123/*
124 *  Floating point context ares
125 */
126
127#if (CPU_SOFTWARE_FP == TRUE)
128
129/*
130 *  This is the same as gcc's view of the software FP condition code
131 *  register _fpCCR.  The implementation of the emulation code is
132 *  in the gcc-VERSION/config/m68k directory.  This structure is
133 *  correct as of gcc 2.7.2.2.
134 */
135
136typedef struct {
137  uint16_t     _exception_bits;
138  uint16_t     _trap_enable_bits;
139  uint16_t     _sticky_bits;
140  uint16_t     _rounding_mode;
141  uint16_t     _format;
142  uint16_t     _last_operation;
143  union {
144    float sf;
145    double df;
146  } _operand1;
147  union {
148    float sf;
149    double df;
150  } _operand2;
151} Context_Control_fp;
152
153#else
154
155/*
156 *  FP context save area for the M68881/M68882 numeric coprocessors.
157 */
158
159typedef struct {
160  uint8_t     fp_save_area[332];    /*   216 bytes for FSAVE/FRESTORE    */
161                                    /*    96 bytes for FMOVEM FP0-7      */
162                                    /*    12 bytes for FMOVEM CREGS      */
163                                    /*     4 bytes for non-null flag     */
164} Context_Control_fp;
165#endif
166
167/*
168 *  The following structures define the set of information saved
169 *  on the current stack by RTEMS upon receipt of each exc/interrupt.
170 *  These are not used by m68k handlers.
171 *  The exception frame is for rdbg.
172 */
173
174typedef struct {
175  uint32_t   vecnum; /* vector number */
176} CPU_Interrupt_frame;
177
178typedef struct {
179  uint32_t   vecnum; /* vector number */
180  uint32_t   sr; /* status register */
181  uint32_t   pc; /* program counter */
182  uint32_t   d0, d1, d2, d3, d4, d5, d6, d7;
183  uint32_t   a0, a1, a2, a3, a4, a5, a6, a7;
184} CPU_Exception_frame;
185
186/*
187 *  The following table contains the information required to configure
188 *  the m68k specific parameters.
189 */
190
191typedef struct {
192  void       (*pretasking_hook)( void );
193  void       (*predriver_hook)( void );
194  void       (*postdriver_hook)( void );
195  void       (*idle_task)( void );
196  boolean      do_zero_of_workspace;
197  uint32_t     idle_task_stack_size;
198  uint32_t     interrupt_stack_size;
199  uint32_t     extra_mpci_receive_server_stack;
200  void *     (*stack_allocate_hook)( uint32_t   );
201  void       (*stack_free_hook)( void* );
202  /* end of fields required on all CPUs */
203
204  m68k_isr    *interrupt_vector_table;
205}   rtems_cpu_table;
206
207/*
208 *  Macros to access required entires in the CPU Table are in
209 *  the file rtems/system.h.
210 */
211
212/*
213 *  Macros to access M68K specific additions to the CPU Table
214 */
215
216#define rtems_cpu_configuration_get_interrupt_vector_table() \
217   (_CPU_Table.interrupt_vector_table)
218
219/* variables */
220
221SCORE_EXTERN void                   *_CPU_Interrupt_stack_low;
222SCORE_EXTERN void                   *_CPU_Interrupt_stack_high;
223
224extern char                         _VBR[];
225
226#if ( M68K_HAS_VBR == 0 )
227
228/*
229 * Table of ISR handler entries that resides in RAM. The FORMAT/ID is
230 * pushed onto the stack. This is not is the same order as VBR processors.
231 * The ISR handler takes the format and uses it for dispatching the user
232 * handler.
233 *
234 * FIXME : should be moved to below CPU_INTERRUPT_NUMBER_OF_VECTORS
235 *
236 */
237
238typedef struct {
239  uint16_t   move_a7;            /* move #FORMAT_ID,%a7@- */
240  uint16_t   format_id;
241  uint16_t   jmp;                /* jmp  _ISR_Handlers */
242  uint32_t   isr_handler;
243} _CPU_ISR_handler_entry;
244
245#define M68K_MOVE_A7 0x3F3C
246#define M68K_JMP     0x4EF9
247
248      /* points to jsr-exception-table in targets wo/ VBR register */
249SCORE_EXTERN _CPU_ISR_handler_entry _CPU_ISR_jump_table[256];
250
251#endif /* M68K_HAS_VBR */
252#endif /* ASM */
253
254/* constants */
255
256/*
257 *  This defines the number of levels and the mask used to pick those
258 *  bits out of a thread mode.
259 */
260
261#define CPU_MODES_INTERRUPT_LEVEL  0x00000007 /* interrupt level in mode */
262#define CPU_MODES_INTERRUPT_MASK   0x00000007 /* interrupt level in mode */
263
264/*
265 *  context size area for floating point
266 */
267
268#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
269
270/*
271 *  extra stack required by the MPCI receive server thread
272 */
273
274#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
275
276/*
277 *  m68k family supports 256 distinct vectors.
278 */
279
280#define CPU_INTERRUPT_NUMBER_OF_VECTORS      256
281#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
282
283/*
284 *  This is defined if the port has a special way to report the ISR nesting
285 *  level.  Most ports maintain the variable _ISR_Nest_level.
286 */
287
288#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
289
290/*
291 *  Minimum size of a thread's stack.
292 */
293
294#define CPU_STACK_MINIMUM_SIZE           4096
295
296/*
297 *  m68k is pretty tolerant of alignment.  Just put things on 4 byte boundaries.
298 */
299
300#define CPU_ALIGNMENT                    4
301#define CPU_HEAP_ALIGNMENT               CPU_ALIGNMENT
302#define CPU_PARTITION_ALIGNMENT          CPU_ALIGNMENT
303
304/*
305 *  On m68k thread stacks require no further alignment after allocation
306 *  from the Workspace.
307 */
308
309#define CPU_STACK_ALIGNMENT        0
310
311#ifndef ASM
312
313/* macros */
314
315/*
316 *  ISR handler macros
317 *
318 *  These macros perform the following functions:
319 *     + initialize the RTEMS vector table
320 *     + disable all maskable CPU interrupts
321 *     + restore previous interrupt level (enable)
322 *     + temporarily restore interrupts (flash)
323 *     + set a particular level
324 */
325
326#define _CPU_Initialize_vectors()
327
328#define _CPU_ISR_Disable( _level ) \
329  m68k_disable_interrupts( _level )
330
331#define _CPU_ISR_Enable( _level ) \
332  m68k_enable_interrupts( _level )
333
334#define _CPU_ISR_Flash( _level ) \
335  m68k_flash_interrupts( _level )
336
337#define _CPU_ISR_Set_level( _newlevel ) \
338   m68k_set_interrupt_level( _newlevel )
339
340uint32_t   _CPU_ISR_Get_level( void );
341
342/* end of ISR handler macros */
343
344/*
345 *  Context handler macros
346 *
347 *  These macros perform the following functions:
348 *     + initialize a context area
349 *     + restart the current thread
350 *     + calculate the initial pointer into a FP context area
351 *     + initialize an FP context area
352 */
353
354#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
355                                 _isr, _entry_point, _is_fp ) \
356   do { \
357     uint32_t   _stack; \
358     \
359     (_the_context)->sr      = 0x3000 | ((_isr) << 8); \
360     _stack                  = (uint32_t  )(_stack_base) + (_size) - 4; \
361     (_the_context)->a7_msp  = (void *)_stack; \
362     *(void **)_stack        = (void *)(_entry_point); \
363   } while ( 0 )
364
365#define _CPU_Context_Restart_self( _the_context ) \
366  { asm volatile( "movew %0,%%sr ; " \
367                  "moval %1,%%a7 ; " \
368                  "rts"  \
369        : "=d" ((_the_context)->sr), "=d" ((_the_context)->a7_msp) \
370        : "0" ((_the_context)->sr), "1" ((_the_context)->a7_msp) ); \
371  }
372
373/*
374 *  Floating Point Context Area Support routines
375 */
376
377#if (CPU_SOFTWARE_FP == TRUE)
378
379/*
380 *  This software FP implementation is only for GCC.
381 */
382
383#define _CPU_Context_Fp_start( _base, _offset ) \
384   ((void *) _Addresses_Add_offset( (_base), (_offset) ) )
385
386
387#define _CPU_Context_Initialize_fp( _fp_area ) \
388   { \
389   Context_Control_fp *_fp; \
390   _fp = *(Context_Control_fp **)_fp_area; \
391   _fp->_exception_bits = 0; \
392   _fp->_trap_enable_bits = 0; \
393   _fp->_sticky_bits = 0; \
394   _fp->_rounding_mode = 0;  /* ROUND_TO_NEAREST */ \
395   _fp->_format = 0;         /* NIL */ \
396   _fp->_last_operation = 0;  /* NOOP */ \
397   _fp->_operand1.df = 0; \
398   _fp->_operand2.df = 0; \
399   }
400#else
401#define _CPU_Context_Fp_start( _base, _offset ) \
402   ((void *) \
403     _Addresses_Add_offset( \
404        (_base), \
405        (_offset) + CPU_CONTEXT_FP_SIZE - 4 \
406     ) \
407   )
408
409#define _CPU_Context_Initialize_fp( _fp_area ) \
410   { uint32_t   *_fp_context = (uint32_t   *)*(_fp_area); \
411     \
412     *(--(_fp_context)) = 0; \
413     *(_fp_area) = (uint8_t   *)(_fp_context); \
414   }
415#endif
416
417/* end of Context handler macros */
418
419/*
420 *  _CPU_Thread_Idle_body
421 *
422 *  This routine is the CPU dependent IDLE thread body.
423 *
424 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
425 *         is TRUE.
426 */
427
428void _CPU_Thread_Idle_body( void );
429
430/*
431 *  Fatal Error manager macros
432 *
433 *  These macros perform the following functions:
434 *    + disable interrupts and halt the CPU
435 */
436
437#if ( M68K_COLDFIRE_ARCH == 1 )
438#define _CPU_Fatal_halt( _error ) \
439  { asm volatile( "move.w %%sr,%%d0\n\t" \
440                  "or.l %2,%%d0\n\t" \
441                  "move.w %%d0,%%sr\n\t" \
442                  "move.l %1,%%d0\n\t" \
443                  "move.l #0xDEADBEEF,%%d1\n\t" \
444                  "halt" \
445                  : "=g" (_error) \
446                  : "0" (_error), "d"(0x0700) \
447                  : "d0", "d1" ); \
448  }
449#else
450#define _CPU_Fatal_halt( _error ) \
451  { asm volatile( "movl  %0,%%d0; " \
452                  "orw   #0x0700,%%sr; " \
453                  "stop  #0x2700" : "=d" ((_error)) : "0" ((_error)) ); \
454  }
455#endif
456
457/* end of Fatal Error manager macros */
458
459/*
460 *  Bitfield handler macros
461 *
462 *  These macros perform the following functions:
463 *     + scan for the highest numbered (MSB) set in a 16 bit bitfield
464 *
465 *  NOTE:
466 *
467 *    It appears that on the M68020 bitfield are always 32 bits wide
468 *    when in a register.  This code forces the bitfield to be in
469 *    memory (it really always is anyway). This allows us to
470 *    have a real 16 bit wide bitfield which operates "correctly."
471 */
472
473#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
474#define CPU_USE_GENERIC_BITFIELD_DATA FALSE
475
476#if ( M68K_HAS_BFFFO == 1 )
477
478#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
479  asm volatile( "bfffo (%1),#0,#16,%0" : "=d" (_output) : "a" (&_value));
480#else
481
482/* duplicates BFFFO results for 16 bits (i.e., 15-(_priority) in
483   _CPU_Priority_bits_index is not needed), handles the 0 case, and
484   does not molest _value -- jsg */
485#if ( M68K_COLDFIRE_ARCH == 1 )
486#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
487  { \
488    extern const unsigned char __BFFFOtable[256]; \
489    register int dumby; \
490    \
491    asm volatile ( \
492       "   clr.l   %1\n"         \
493       "   move.w  %2,%1\n"      \
494       "   lsr.l   #8,%1\n"      \
495       "   beq.s   1f\n"         \
496       "   move.b  (%3,%1),%0\n" \
497       "   bra.s   0f\n"         \
498       "1: move.w  %2,%1\n"      \
499       "   move.b  (%3,%1),%0\n" \
500       "   addq.l  #8,%0\n"      \
501       "0: and.l   #0xff,%0\n"   \
502       : "=&d" ((_output)), "=&d" ((dumby))    \
503       : "d" ((_value)), "ao" ((__BFFFOtable)) \
504       : "cc" ) ; \
505  }
506#elif ( M68K_HAS_EXTB_L == 1 )
507#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
508  { \
509    extern const unsigned char __BFFFOtable[256]; \
510    register int dumby; \
511    \
512    asm volatile ( "   move.w  %2,%1\n"        \
513       "   lsr.w   #8,%1\n"        \
514       "   beq.s   1f\n"           \
515       "   move.b  (%3,%1.w),%0\n" \
516       "   extb.l  %0\n"           \
517       "   bra.s   0f\n"           \
518       "1: moveq.l #8,%0\n"        \
519       "   add.b   (%3,%2.w),%0\n" \
520       "0:\n"                      \
521       : "=&d" ((_output)), "=&d" ((dumby)) \
522       : "d" ((_value)), "ao" ((__BFFFOtable)) \
523       : "cc" ) ; \
524  }
525#else
526#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
527  { \
528    extern const unsigned char __BFFFOtable[256]; \
529    register int dumby; \
530    \
531    asm volatile ( "   move.w  %2,%1\n"        \
532       "   lsr.w   #8,%1\n"        \
533       "   beq.s   1f\n"           \
534       "   move.b  (%3,%1.w),%0\n" \
535       "   and.l   #0x000000ff,%0\n"\
536       "   bra.s   0f\n"           \
537       "1: moveq.l #8,%0\n"        \
538       "   add.b   (%3,%2.w),%0\n" \
539       "0:\n"                      \
540       : "=&d" ((_output)), "=&d" ((dumby)) \
541       : "d" ((_value)), "ao" ((__BFFFOtable)) \
542       : "cc" ) ; \
543  }
544#endif
545
546#endif
547
548/* end of Bitfield handler macros */
549
550/*
551 *  Priority handler macros
552 *
553 *  These macros perform the following functions:
554 *    + return a mask with the bit for this major/minor portion of
555 *      of thread priority set.
556 *    + translate the bit number returned by "Bitfield_find_first_bit"
557 *      into an index into the thread ready chain bit maps
558 */
559
560#define _CPU_Priority_Mask( _bit_number ) \
561  ( 0x8000 >> (_bit_number) )
562
563#define _CPU_Priority_bits_index( _priority ) \
564  (_priority)
565
566/* end of Priority handler macros */
567
568/* functions */
569
570/*
571 *  _CPU_Initialize
572 *
573 *  This routine performs CPU dependent initialization.
574 */
575
576void _CPU_Initialize(
577  rtems_cpu_table  *cpu_table,
578  void      (*thread_dispatch)
579);
580
581/*
582 *  _CPU_ISR_install_raw_handler
583 *
584 *  This routine installs a "raw" interrupt handler directly into the
585 *  processor's vector table.
586 */
587 
588void _CPU_ISR_install_raw_handler(
589  uint32_t    vector,
590  proc_ptr    new_handler,
591  proc_ptr   *old_handler
592);
593
594/*
595 *  _CPU_ISR_install_vector
596 *
597 *  This routine installs an interrupt vector.
598 */
599
600void _CPU_ISR_install_vector(
601  uint32_t         vector,
602  proc_ptr         new_handler,
603  proc_ptr        *old_handler
604);
605
606/*
607 *  _CPU_Install_interrupt_stack
608 *
609 *  This routine installs the hardware interrupt stack pointer.
610 */
611
612void _CPU_Install_interrupt_stack( void );
613
614/*
615 *  _CPU_Context_switch
616 *
617 *  This routine switches from the run context to the heir context.
618 */
619
620void _CPU_Context_switch(
621  Context_Control  *run,
622  Context_Control  *heir
623);
624
625/*
626 *  _CPU_Context_save_fp
627 *
628 *  This routine saves the floating point context passed to it.
629 */
630
631void _CPU_Context_save_fp(
632  void **fp_context_ptr
633);
634
635/*
636 *  _CPU_Context_restore_fp
637 *
638 *  This routine restores the floating point context passed to it.
639 */
640
641void _CPU_Context_restore_fp(
642  void **fp_context_ptr
643);
644
645#if (M68K_HAS_FPSP_PACKAGE == 1)
646/*
647 *  Hooks for the Floating Point Support Package (FPSP) provided by Motorola
648 *
649 *  NOTES: 
650 *
651 *  Motorola 68k family CPU's before the 68040 used a coprocessor
652 *  (68881 or 68882) to handle floating point.  The 68040 has internal
653 *  floating point support -- but *not* the complete support provided by
654 *  the 68881 or 68882.  The leftover functions are taken care of by the
655 *  M68040 Floating Point Support Package.  Quoting from the MC68040
656 *  Microprocessors User's Manual, Section 9, Floating-Point Unit (MC68040):
657 *
658 *    "When used with the M68040FPSP, the MC68040 FPU is fully
659 *    compliant with IEEE floating-point standards."
660 *
661 *  M68KFPSPInstallExceptionHandlers is in libcpu/m68k/MODEL/fpsp and
662 *  is invoked early in the application code to insure that proper FP
663 *  behavior is installed.  This is not left to the BSP to call, since
664 *  this would force all applications using that BSP to use FPSP which
665 *  is not necessarily desirable.
666 *
667 *  There is a similar package for the 68060 but RTEMS does not yet
668 *  support the 68060.
669 */
670
671void M68KFPSPInstallExceptionHandlers (void);
672
673SCORE_EXTERN int (*_FPSP_install_raw_handler)(
674  uint32_t   vector,
675  proc_ptr new_handler,
676  proc_ptr *old_handler
677);
678
679#endif
680
681
682#endif
683
684#ifdef __cplusplus
685}
686#endif
687
688#endif
689/* end of include file */
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