source: rtems/cpukit/score/cpu/m68k/rtems/score/cpu.h @ a911a77

4.104.114.84.9
Last change on this file since a911a77 was a911a77, checked in by Ralf Corsepius <ralf.corsepius@…>, on Nov 2, 2004 at 7:39:25 AM

2004-10-02 Ralf Corsepius <ralf_corsepius@…>

  • rtems/score/cpu.h: Add doxygen preamble.
  • rtems/score/m68k.h: Add doxygen preamble.
  • rtems/score/types.h: Add doxygen preamble.
  • Property mode set to 100644
File size: 17.9 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  This include file contains information pertaining to the Motorola
7 *  m68xxx processor family.
8 *
9 *  COPYRIGHT (c) 1989-1999.
10 *  On-Line Applications Research Corporation (OAR).
11 *
12 *  The license and distribution terms for this file may be
13 *  found in the file LICENSE in this distribution or at
14 *  http://www.rtems.com/license/LICENSE.
15 *
16 *  $Id$
17 */
18
19#ifndef __CPU_h
20#define __CPU_h
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26#include <rtems/score/m68k.h>              /* pick up machine definitions */
27#ifndef ASM
28#include <rtems/score/types.h>
29#endif
30
31/* conditional compilation parameters */
32
33#define CPU_INLINE_ENABLE_DISPATCH       TRUE
34#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
35
36/*
37 *  Use the m68k's hardware interrupt stack support and have the
38 *  interrupt manager allocate the memory for it.
39 */
40
41#if ( M68K_HAS_SEPARATE_STACKS == 1)
42#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 0
43#define CPU_HAS_HARDWARE_INTERRUPT_STACK 1
44#else
45#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 1
46#define CPU_HAS_HARDWARE_INTERRUPT_STACK 0
47#endif
48#define CPU_ALLOCATE_INTERRUPT_STACK     1
49
50/*
51 *  Does the RTEMS invoke the user's ISR with the vector number and
52 *  a pointer to the saved interrupt frame (1) or just the vector
53 *  number (0)?
54 */
55
56#define CPU_ISR_PASSES_FRAME_POINTER 0
57
58/*
59 *  Some family members have no FP, some have an FPU such as the
60 *  MC68881/MC68882 for the MC68020, others have it built in (MC68030, 040).
61 *
62 *  NOTE:  If on a CPU without hardware FP, then one can use software
63 *         emulation.  The gcc software FP emulation code has data which
64 *         must be contexted switched on a per task basis.
65 */
66
67#if ( M68K_HAS_FPU == 1 )
68#define CPU_HARDWARE_FP     TRUE
69#define CPU_SOFTWARE_FP     FALSE
70#else
71#define CPU_HARDWARE_FP     FALSE
72#if defined(__GNUC__)
73#define CPU_SOFTWARE_FP     TRUE
74#else
75#define CPU_SOFTWARE_FP     FALSE
76#endif
77#endif
78
79/*
80 *  All tasks are not by default floating point tasks on this CPU.
81 *  The IDLE task does not have a floating point context on this CPU.
82 *  It is safe to use the deferred floating point context switch
83 *  algorithm on this CPU.
84 */
85
86#define CPU_ALL_TASKS_ARE_FP             FALSE
87#define CPU_IDLE_TASK_IS_FP              FALSE
88#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
89
90#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
91#define CPU_STACK_GROWS_UP               FALSE
92#define CPU_STRUCTURE_ALIGNMENT
93
94/*
95 *  Define what is required to specify how the network to host conversion
96 *  routines are handled.
97 */
98
99#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
100#define CPU_BIG_ENDIAN                           TRUE
101#define CPU_LITTLE_ENDIAN                        FALSE
102
103#ifndef ASM
104/* structures */
105
106/*
107 *  Basic integer context for the m68k family.
108 */
109
110typedef struct {
111  uint32_t    sr;                /* (sr) status register */
112  uint32_t    d2;                /* (d2) data register 2 */
113  uint32_t    d3;                /* (d3) data register 3 */
114  uint32_t    d4;                /* (d4) data register 4 */
115  uint32_t    d5;                /* (d5) data register 5 */
116  uint32_t    d6;                /* (d6) data register 6 */
117  uint32_t    d7;                /* (d7) data register 7 */
118  void       *a2;                /* (a2) address register 2 */
119  void       *a3;                /* (a3) address register 3 */
120  void       *a4;                /* (a4) address register 4 */
121  void       *a5;                /* (a5) address register 5 */
122  void       *a6;                /* (a6) address register 6 */
123  void       *a7_msp;            /* (a7) master stack pointer */
124}   Context_Control;
125
126/*
127 *  Floating point context ares
128 */
129
130#if (CPU_SOFTWARE_FP == TRUE)
131
132/*
133 *  This is the same as gcc's view of the software FP condition code
134 *  register _fpCCR.  The implementation of the emulation code is
135 *  in the gcc-VERSION/config/m68k directory.  This structure is
136 *  correct as of gcc 2.7.2.2.
137 */
138
139typedef struct {
140  uint16_t     _exception_bits;
141  uint16_t     _trap_enable_bits;
142  uint16_t     _sticky_bits;
143  uint16_t     _rounding_mode;
144  uint16_t     _format;
145  uint16_t     _last_operation;
146  union {
147    float sf;
148    double df;
149  } _operand1;
150  union {
151    float sf;
152    double df;
153  } _operand2;
154} Context_Control_fp;
155
156#else
157
158/*
159 *  FP context save area for the M68881/M68882 numeric coprocessors.
160 */
161
162typedef struct {
163  uint8_t     fp_save_area[332];    /*   216 bytes for FSAVE/FRESTORE    */
164                                    /*    96 bytes for FMOVEM FP0-7      */
165                                    /*    12 bytes for FMOVEM CREGS      */
166                                    /*     4 bytes for non-null flag     */
167} Context_Control_fp;
168#endif
169
170/*
171 *  The following structures define the set of information saved
172 *  on the current stack by RTEMS upon receipt of each exc/interrupt.
173 *  These are not used by m68k handlers.
174 *  The exception frame is for rdbg.
175 */
176
177typedef struct {
178  uint32_t   vecnum; /* vector number */
179} CPU_Interrupt_frame;
180
181typedef struct {
182  uint32_t   vecnum; /* vector number */
183  uint32_t   sr; /* status register */
184  uint32_t   pc; /* program counter */
185  uint32_t   d0, d1, d2, d3, d4, d5, d6, d7;
186  uint32_t   a0, a1, a2, a3, a4, a5, a6, a7;
187} CPU_Exception_frame;
188
189/*
190 *  The following table contains the information required to configure
191 *  the m68k specific parameters.
192 */
193
194typedef struct {
195  void       (*pretasking_hook)( void );
196  void       (*predriver_hook)( void );
197  void       (*postdriver_hook)( void );
198  void       (*idle_task)( void );
199  boolean      do_zero_of_workspace;
200  uint32_t     idle_task_stack_size;
201  uint32_t     interrupt_stack_size;
202  uint32_t     extra_mpci_receive_server_stack;
203  void *     (*stack_allocate_hook)( uint32_t   );
204  void       (*stack_free_hook)( void* );
205  /* end of fields required on all CPUs */
206
207  m68k_isr    *interrupt_vector_table;
208}   rtems_cpu_table;
209
210/*
211 *  Macros to access required entires in the CPU Table are in
212 *  the file rtems/system.h.
213 */
214
215/*
216 *  Macros to access M68K specific additions to the CPU Table
217 */
218
219#define rtems_cpu_configuration_get_interrupt_vector_table() \
220   (_CPU_Table.interrupt_vector_table)
221
222/* variables */
223
224SCORE_EXTERN void                   *_CPU_Interrupt_stack_low;
225SCORE_EXTERN void                   *_CPU_Interrupt_stack_high;
226
227extern char                         _VBR[]; 
228
229#if ( M68K_HAS_VBR == 0 )
230
231/*
232 * Table of ISR handler entries that resides in RAM. The FORMAT/ID is
233 * pushed onto the stack. This is not is the same order as VBR processors.
234 * The ISR handler takes the format and uses it for dispatching the user
235 * handler.
236 *
237 * FIXME : should be moved to below CPU_INTERRUPT_NUMBER_OF_VECTORS
238 *
239 */
240
241typedef struct {
242  uint16_t   move_a7;            /* move #FORMAT_ID,%a7@- */
243  uint16_t   format_id;
244  uint16_t   jmp;                /* jmp  _ISR_Handlers */
245  uint32_t   isr_handler;
246} _CPU_ISR_handler_entry;
247
248#define M68K_MOVE_A7 0x3F3C
249#define M68K_JMP     0x4EF9
250
251      /* points to jsr-exception-table in targets wo/ VBR register */
252SCORE_EXTERN _CPU_ISR_handler_entry _CPU_ISR_jump_table[256]; 
253
254#endif /* M68K_HAS_VBR */
255#endif /* ASM */
256
257/* constants */
258
259/*
260 *  This defines the number of levels and the mask used to pick those
261 *  bits out of a thread mode.
262 */
263
264#define CPU_MODES_INTERRUPT_LEVEL  0x00000007 /* interrupt level in mode */
265#define CPU_MODES_INTERRUPT_MASK   0x00000007 /* interrupt level in mode */
266
267/*
268 *  context size area for floating point
269 */
270
271#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
272
273/*
274 *  extra stack required by the MPCI receive server thread
275 */
276
277#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
278
279/*
280 *  m68k family supports 256 distinct vectors.
281 */
282
283#define CPU_INTERRUPT_NUMBER_OF_VECTORS      256
284#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
285
286/*
287 *  This is defined if the port has a special way to report the ISR nesting
288 *  level.  Most ports maintain the variable _ISR_Nest_level.
289 */
290
291#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
292
293/*
294 *  Minimum size of a thread's stack.
295 */
296
297#define CPU_STACK_MINIMUM_SIZE           4096
298
299/*
300 *  m68k is pretty tolerant of alignment.  Just put things on 4 byte boundaries.
301 */
302
303#define CPU_ALIGNMENT                    4
304#define CPU_HEAP_ALIGNMENT               CPU_ALIGNMENT
305#define CPU_PARTITION_ALIGNMENT          CPU_ALIGNMENT
306
307/*
308 *  On m68k thread stacks require no further alignment after allocation
309 *  from the Workspace.
310 */
311
312#define CPU_STACK_ALIGNMENT        0
313
314#ifndef ASM
315
316/* macros */
317
318/*
319 *  ISR handler macros
320 *
321 *  These macros perform the following functions:
322 *     + initialize the RTEMS vector table
323 *     + disable all maskable CPU interrupts
324 *     + restore previous interrupt level (enable)
325 *     + temporarily restore interrupts (flash)
326 *     + set a particular level
327 */
328
329#define _CPU_Initialize_vectors()
330
331#define _CPU_ISR_Disable( _level ) \
332  m68k_disable_interrupts( _level )
333
334#define _CPU_ISR_Enable( _level ) \
335  m68k_enable_interrupts( _level )
336
337#define _CPU_ISR_Flash( _level ) \
338  m68k_flash_interrupts( _level )
339
340#define _CPU_ISR_Set_level( _newlevel ) \
341   m68k_set_interrupt_level( _newlevel )
342
343uint32_t   _CPU_ISR_Get_level( void );
344
345/* end of ISR handler macros */
346
347/*
348 *  Context handler macros
349 *
350 *  These macros perform the following functions:
351 *     + initialize a context area
352 *     + restart the current thread
353 *     + calculate the initial pointer into a FP context area
354 *     + initialize an FP context area
355 */
356
357#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
358                                 _isr, _entry_point, _is_fp ) \
359   do { \
360     uint32_t   _stack; \
361     \
362     (_the_context)->sr      = 0x3000 | ((_isr) << 8); \
363     _stack                  = (uint32_t  )(_stack_base) + (_size) - 4; \
364     (_the_context)->a7_msp  = (void *)_stack; \
365     *(void **)_stack        = (void *)(_entry_point); \
366   } while ( 0 )
367
368#define _CPU_Context_Restart_self( _the_context ) \
369  { asm volatile( "movew %0,%%sr ; " \
370                  "moval %1,%%a7 ; " \
371                  "rts"  \
372        : "=d" ((_the_context)->sr), "=d" ((_the_context)->a7_msp) \
373        : "0" ((_the_context)->sr), "1" ((_the_context)->a7_msp) ); \
374  }
375
376/*
377 *  Floating Point Context Area Support routines
378 */
379
380#if (CPU_SOFTWARE_FP == TRUE)
381
382/*
383 *  This software FP implementation is only for GCC.
384 */
385
386#define _CPU_Context_Fp_start( _base, _offset ) \
387   ((void *) _Addresses_Add_offset( (_base), (_offset) ) )
388
389
390#define _CPU_Context_Initialize_fp( _fp_area ) \
391   { \
392   Context_Control_fp *_fp; \
393   _fp = *(Context_Control_fp **)_fp_area; \
394   _fp->_exception_bits = 0; \
395   _fp->_trap_enable_bits = 0; \
396   _fp->_sticky_bits = 0; \
397   _fp->_rounding_mode = 0;  /* ROUND_TO_NEAREST */ \
398   _fp->_format = 0;         /* NIL */ \
399   _fp->_last_operation = 0;  /* NOOP */ \
400   _fp->_operand1.df = 0; \
401   _fp->_operand2.df = 0; \
402   }
403#else
404#define _CPU_Context_Fp_start( _base, _offset ) \
405   ((void *) \
406     _Addresses_Add_offset( \
407        (_base), \
408        (_offset) + CPU_CONTEXT_FP_SIZE - 4 \
409     ) \
410   )
411
412#define _CPU_Context_Initialize_fp( _fp_area ) \
413   { uint32_t   *_fp_context = (uint32_t   *)*(_fp_area); \
414     \
415     *(--(_fp_context)) = 0; \
416     *(_fp_area) = (uint8_t   *)(_fp_context); \
417   }
418#endif
419
420/* end of Context handler macros */
421
422/*
423 *  _CPU_Thread_Idle_body
424 *
425 *  This routine is the CPU dependent IDLE thread body.
426 *
427 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
428 *         is TRUE.
429 */
430
431void _CPU_Thread_Idle_body( void );
432
433/*
434 *  Fatal Error manager macros
435 *
436 *  These macros perform the following functions:
437 *    + disable interrupts and halt the CPU
438 */
439
440#if ( M68K_COLDFIRE_ARCH == 1 )
441#define _CPU_Fatal_halt( _error ) \
442  { asm volatile( "move.w %%sr,%%d0\n\t" \
443                  "or.l %2,%%d0\n\t" \
444                  "move.w %%d0,%%sr\n\t" \
445                  "move.l %1,%%d0\n\t" \
446                  "move.l #0xDEADBEEF,%%d1\n\t" \
447                  "halt" \
448                  : "=g" (_error) \
449                  : "0" (_error), "d"(0x0700) \
450                  : "d0", "d1" ); \
451  }
452#else
453#define _CPU_Fatal_halt( _error ) \
454  { asm volatile( "movl  %0,%%d0; " \
455                  "orw   #0x0700,%%sr; " \
456                  "stop  #0x2700" : "=d" ((_error)) : "0" ((_error)) ); \
457  }
458#endif
459
460/* end of Fatal Error manager macros */
461
462/*
463 *  Bitfield handler macros
464 *
465 *  These macros perform the following functions:
466 *     + scan for the highest numbered (MSB) set in a 16 bit bitfield
467 *
468 *  NOTE:
469 *
470 *    It appears that on the M68020 bitfield are always 32 bits wide
471 *    when in a register.  This code forces the bitfield to be in
472 *    memory (it really always is anyway). This allows us to
473 *    have a real 16 bit wide bitfield which operates "correctly."
474 */
475
476#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
477#define CPU_USE_GENERIC_BITFIELD_DATA FALSE
478
479#if ( M68K_HAS_BFFFO == 1 )
480
481#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
482  asm volatile( "bfffo (%1),#0,#16,%0" : "=d" (_output) : "a" (&_value));
483#else
484
485/* duplicates BFFFO results for 16 bits (i.e., 15-(_priority) in
486   _CPU_Priority_bits_index is not needed), handles the 0 case, and
487   does not molest _value -- jsg */
488#if ( M68K_COLDFIRE_ARCH == 1 )
489#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
490  { \
491    extern const unsigned char __BFFFOtable[256]; \
492    register int dumby; \
493    \
494    asm volatile ( \
495       "   clr.l   %1\n"         \
496       "   move.w  %2,%1\n"      \
497       "   lsr.l   #8,%1\n"      \
498       "   beq.s   1f\n"         \
499       "   move.b  (%3,%1),%0\n" \
500       "   bra.s   0f\n"         \
501       "1: move.w  %2,%1\n"      \
502       "   move.b  (%3,%1),%0\n" \
503       "   addq.l  #8,%0\n"      \
504       "0: and.l   #0xff,%0\n"   \
505       : "=&d" ((_output)), "=&d" ((dumby))    \
506       : "d" ((_value)), "ao" ((__BFFFOtable)) \
507       : "cc" ) ; \
508  }
509#elif ( M68K_HAS_EXTB_L == 1 )
510#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
511  { \
512    extern const unsigned char __BFFFOtable[256]; \
513    register int dumby; \
514    \
515    asm volatile ( "   move.w  %2,%1\n"        \
516       "   lsr.w   #8,%1\n"        \
517       "   beq.s   1f\n"           \
518       "   move.b  (%3,%1.w),%0\n" \
519       "   extb.l  %0\n"           \
520       "   bra.s   0f\n"           \
521       "1: moveq.l #8,%0\n"        \
522       "   add.b   (%3,%2.w),%0\n" \
523       "0:\n"                      \
524       : "=&d" ((_output)), "=&d" ((dumby)) \
525       : "d" ((_value)), "ao" ((__BFFFOtable)) \
526       : "cc" ) ; \
527  }
528#else
529#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
530  { \
531    extern const unsigned char __BFFFOtable[256]; \
532    register int dumby; \
533    \
534    asm volatile ( "   move.w  %2,%1\n"        \
535       "   lsr.w   #8,%1\n"        \
536       "   beq.s   1f\n"           \
537       "   move.b  (%3,%1.w),%0\n" \
538       "   and.l   #0x000000ff,%0\n"\
539       "   bra.s   0f\n"           \
540       "1: moveq.l #8,%0\n"        \
541       "   add.b   (%3,%2.w),%0\n" \
542       "0:\n"                      \
543       : "=&d" ((_output)), "=&d" ((dumby)) \
544       : "d" ((_value)), "ao" ((__BFFFOtable)) \
545       : "cc" ) ; \
546  }
547#endif
548
549#endif
550
551/* end of Bitfield handler macros */
552
553/*
554 *  Priority handler macros
555 *
556 *  These macros perform the following functions:
557 *    + return a mask with the bit for this major/minor portion of
558 *      of thread priority set.
559 *    + translate the bit number returned by "Bitfield_find_first_bit"
560 *      into an index into the thread ready chain bit maps
561 */
562
563#define _CPU_Priority_Mask( _bit_number ) \
564  ( 0x8000 >> (_bit_number) )
565
566#define _CPU_Priority_bits_index( _priority ) \
567  (_priority)
568
569/* end of Priority handler macros */
570
571/* functions */
572
573/*
574 *  _CPU_Initialize
575 *
576 *  This routine performs CPU dependent initialization.
577 */
578
579void _CPU_Initialize(
580  rtems_cpu_table  *cpu_table,
581  void      (*thread_dispatch)
582);
583
584/*
585 *  _CPU_ISR_install_raw_handler
586 *
587 *  This routine installs a "raw" interrupt handler directly into the
588 *  processor's vector table.
589 */
590 
591void _CPU_ISR_install_raw_handler(
592  uint32_t    vector,
593  proc_ptr    new_handler,
594  proc_ptr   *old_handler
595);
596
597/*
598 *  _CPU_ISR_install_vector
599 *
600 *  This routine installs an interrupt vector.
601 */
602
603void _CPU_ISR_install_vector(
604  uint32_t         vector,
605  proc_ptr         new_handler,
606  proc_ptr        *old_handler
607);
608
609/*
610 *  _CPU_Install_interrupt_stack
611 *
612 *  This routine installs the hardware interrupt stack pointer.
613 */
614
615void _CPU_Install_interrupt_stack( void );
616
617/*
618 *  _CPU_Context_switch
619 *
620 *  This routine switches from the run context to the heir context.
621 */
622
623void _CPU_Context_switch(
624  Context_Control  *run,
625  Context_Control  *heir
626);
627
628/*
629 *  _CPU_Context_save_fp
630 *
631 *  This routine saves the floating point context passed to it.
632 */
633
634void _CPU_Context_save_fp(
635  void **fp_context_ptr
636);
637
638/*
639 *  _CPU_Context_restore_fp
640 *
641 *  This routine restores the floating point context passed to it.
642 */
643
644void _CPU_Context_restore_fp(
645  void **fp_context_ptr
646);
647
648#if (M68K_HAS_FPSP_PACKAGE == 1)
649/*
650 *  Hooks for the Floating Point Support Package (FPSP) provided by Motorola
651 *
652 *  NOTES: 
653 *
654 *  Motorola 68k family CPU's before the 68040 used a coprocessor
655 *  (68881 or 68882) to handle floating point.  The 68040 has internal
656 *  floating point support -- but *not* the complete support provided by
657 *  the 68881 or 68882.  The leftover functions are taken care of by the
658 *  M68040 Floating Point Support Package.  Quoting from the MC68040
659 *  Microprocessors User's Manual, Section 9, Floating-Point Unit (MC68040):
660 *
661 *    "When used with the M68040FPSP, the MC68040 FPU is fully
662 *    compliant with IEEE floating-point standards."
663 *
664 *  M68KFPSPInstallExceptionHandlers is in libcpu/m68k/MODEL/fpsp and
665 *  is invoked early in the application code to insure that proper FP
666 *  behavior is installed.  This is not left to the BSP to call, since
667 *  this would force all applications using that BSP to use FPSP which
668 *  is not necessarily desirable.
669 *
670 *  There is a similar package for the 68060 but RTEMS does not yet
671 *  support the 68060.
672 */
673
674void M68KFPSPInstallExceptionHandlers (void);
675
676SCORE_EXTERN int (*_FPSP_install_raw_handler)(
677  uint32_t   vector,
678  proc_ptr new_handler,
679  proc_ptr *old_handler
680);
681
682#endif
683
684
685#endif
686
687#ifdef __cplusplus
688}
689#endif
690
691#endif
692/* end of include file */
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