1 | /** |
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2 | * @file rtems/score/cpu.h |
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3 | */ |
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4 | |
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5 | /* |
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6 | * This include file contains information pertaining to the Motorola |
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7 | * m68xxx processor family. |
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8 | * |
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9 | * COPYRIGHT (c) 1989-2006. |
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10 | * On-Line Applications Research Corporation (OAR). |
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11 | * |
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12 | * The license and distribution terms for this file may be |
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13 | * found in the file LICENSE in this distribution or at |
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14 | * http://www.rtems.com/license/LICENSE. |
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15 | * |
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16 | * $Id$ |
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17 | */ |
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18 | |
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19 | #ifndef _RTEMS_SCORE_CPU_H |
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20 | #define _RTEMS_SCORE_CPU_H |
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21 | |
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22 | #ifdef __cplusplus |
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23 | extern "C" { |
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24 | #endif |
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25 | |
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26 | #include <rtems/score/m68k.h> /* pick up machine definitions */ |
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27 | #ifndef ASM |
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28 | #include <rtems/score/types.h> |
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29 | #endif |
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30 | |
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31 | /* conditional compilation parameters */ |
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32 | |
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33 | #define CPU_INLINE_ENABLE_DISPATCH TRUE |
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34 | #define CPU_UNROLL_ENQUEUE_PRIORITY FALSE |
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35 | |
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36 | /* |
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37 | * Use the m68k's hardware interrupt stack support and have the |
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38 | * interrupt manager allocate the memory for it. |
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39 | */ |
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40 | |
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41 | #if ( M68K_HAS_SEPARATE_STACKS == 1) |
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42 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK 0 |
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43 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK 1 |
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44 | #else |
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45 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK 1 |
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46 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK 0 |
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47 | #endif |
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48 | #define CPU_ALLOCATE_INTERRUPT_STACK 1 |
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49 | |
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50 | /* |
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51 | * Does the RTEMS invoke the user's ISR with the vector number and |
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52 | * a pointer to the saved interrupt frame (1) or just the vector |
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53 | * number (0)? |
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54 | */ |
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55 | |
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56 | #define CPU_ISR_PASSES_FRAME_POINTER 0 |
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57 | |
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58 | /* |
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59 | * Some family members have no FP, some have an FPU such as the |
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60 | * MC68881/MC68882 for the MC68020, others have it built in (MC68030, 040). |
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61 | * |
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62 | * NOTE: If on a CPU without hardware FP, then one can use software |
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63 | * emulation. The gcc software FP emulation code has data which |
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64 | * must be contexted switched on a per task basis. |
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65 | */ |
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66 | |
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67 | #if ( M68K_HAS_FPU == 1 ) |
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68 | #define CPU_HARDWARE_FP TRUE |
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69 | #define CPU_SOFTWARE_FP FALSE |
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70 | #else |
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71 | #define CPU_HARDWARE_FP FALSE |
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72 | #if defined(__GNUC__) |
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73 | #define CPU_SOFTWARE_FP TRUE |
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74 | #else |
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75 | #define CPU_SOFTWARE_FP FALSE |
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76 | #endif |
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77 | #endif |
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78 | |
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79 | /* |
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80 | * All tasks are not by default floating point tasks on this CPU. |
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81 | * The IDLE task does not have a floating point context on this CPU. |
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82 | * It is safe to use the deferred floating point context switch |
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83 | * algorithm on this CPU. |
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84 | */ |
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85 | |
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86 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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87 | #define CPU_IDLE_TASK_IS_FP FALSE |
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88 | #define CPU_USE_DEFERRED_FP_SWITCH TRUE |
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89 | |
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90 | #define CPU_PROVIDES_IDLE_THREAD_BODY TRUE |
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91 | #define CPU_STACK_GROWS_UP FALSE |
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92 | #define CPU_STRUCTURE_ALIGNMENT |
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93 | |
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94 | /* |
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95 | * Define what is required to specify how the network to host conversion |
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96 | * routines are handled. |
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97 | */ |
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98 | |
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99 | #define CPU_BIG_ENDIAN TRUE |
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100 | #define CPU_LITTLE_ENDIAN FALSE |
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101 | |
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102 | #ifndef ASM |
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103 | /* structures */ |
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104 | |
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105 | /* |
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106 | * Basic integer context for the m68k family. |
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107 | */ |
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108 | |
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109 | typedef struct { |
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110 | uint32_t sr; /* (sr) status register */ |
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111 | uint32_t d2; /* (d2) data register 2 */ |
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112 | uint32_t d3; /* (d3) data register 3 */ |
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113 | uint32_t d4; /* (d4) data register 4 */ |
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114 | uint32_t d5; /* (d5) data register 5 */ |
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115 | uint32_t d6; /* (d6) data register 6 */ |
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116 | uint32_t d7; /* (d7) data register 7 */ |
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117 | void *a2; /* (a2) address register 2 */ |
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118 | void *a3; /* (a3) address register 3 */ |
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119 | void *a4; /* (a4) address register 4 */ |
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120 | void *a5; /* (a5) address register 5 */ |
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121 | void *a6; /* (a6) address register 6 */ |
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122 | void *a7_msp; /* (a7) master stack pointer */ |
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123 | } Context_Control; |
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124 | |
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125 | /* |
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126 | * Floating point context ares |
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127 | */ |
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128 | |
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129 | #if (CPU_SOFTWARE_FP == TRUE) |
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130 | |
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131 | /* |
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132 | * This is the same as gcc's view of the software FP condition code |
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133 | * register _fpCCR. The implementation of the emulation code is |
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134 | * in the gcc-VERSION/config/m68k directory. This structure is |
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135 | * correct as of gcc 2.7.2.2. |
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136 | */ |
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137 | |
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138 | typedef struct { |
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139 | uint16_t _exception_bits; |
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140 | uint16_t _trap_enable_bits; |
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141 | uint16_t _sticky_bits; |
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142 | uint16_t _rounding_mode; |
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143 | uint16_t _format; |
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144 | uint16_t _last_operation; |
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145 | union { |
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146 | float sf; |
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147 | double df; |
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148 | } _operand1; |
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149 | union { |
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150 | float sf; |
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151 | double df; |
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152 | } _operand2; |
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153 | } Context_Control_fp; |
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154 | |
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155 | #else |
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156 | |
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157 | /* |
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158 | * FP context save area for the M68881/M68882 numeric coprocessors. |
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159 | */ |
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160 | |
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161 | typedef struct { |
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162 | uint8_t fp_save_area[332]; /* 216 bytes for FSAVE/FRESTORE */ |
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163 | /* 96 bytes for FMOVEM FP0-7 */ |
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164 | /* 12 bytes for FMOVEM CREGS */ |
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165 | /* 4 bytes for non-null flag */ |
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166 | } Context_Control_fp; |
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167 | #endif |
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168 | |
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169 | /* |
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170 | * The following structures define the set of information saved |
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171 | * on the current stack by RTEMS upon receipt of each exc/interrupt. |
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172 | * These are not used by m68k handlers. |
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173 | * The exception frame is for rdbg. |
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174 | */ |
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175 | |
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176 | typedef struct { |
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177 | uint32_t vecnum; /* vector number */ |
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178 | } CPU_Interrupt_frame; |
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179 | |
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180 | typedef struct { |
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181 | uint32_t vecnum; /* vector number */ |
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182 | uint32_t sr; /* status register */ |
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183 | uint32_t pc; /* program counter */ |
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184 | uint32_t d0, d1, d2, d3, d4, d5, d6, d7; |
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185 | uint32_t a0, a1, a2, a3, a4, a5, a6, a7; |
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186 | } CPU_Exception_frame; |
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187 | |
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188 | /* |
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189 | * The following table contains the information required to configure |
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190 | * the m68k specific parameters. |
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191 | */ |
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192 | |
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193 | typedef struct { |
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194 | void (*pretasking_hook)( void ); |
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195 | void (*predriver_hook)( void ); |
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196 | void (*postdriver_hook)( void ); |
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197 | void (*idle_task)( void ); |
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198 | boolean do_zero_of_workspace; |
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199 | uint32_t idle_task_stack_size; |
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200 | uint32_t interrupt_stack_size; |
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201 | uint32_t extra_mpci_receive_server_stack; |
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202 | void * (*stack_allocate_hook)( uint32_t ); |
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203 | void (*stack_free_hook)( void* ); |
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204 | /* end of fields required on all CPUs */ |
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205 | |
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206 | m68k_isr *interrupt_vector_table; |
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207 | } rtems_cpu_table; |
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208 | |
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209 | /* |
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210 | * Macros to access required entires in the CPU Table are in |
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211 | * the file rtems/system.h. |
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212 | */ |
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213 | |
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214 | /* |
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215 | * Macros to access M68K specific additions to the CPU Table |
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216 | */ |
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217 | |
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218 | #define rtems_cpu_configuration_get_interrupt_vector_table() \ |
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219 | (_CPU_Table.interrupt_vector_table) |
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220 | |
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221 | /* variables */ |
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222 | |
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223 | SCORE_EXTERN void *_CPU_Interrupt_stack_low; |
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224 | SCORE_EXTERN void *_CPU_Interrupt_stack_high; |
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225 | |
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226 | extern void* _VBR; |
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227 | |
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228 | #if ( M68K_HAS_VBR == 0 ) |
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229 | |
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230 | /* |
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231 | * Table of ISR handler entries that resides in RAM. The FORMAT/ID is |
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232 | * pushed onto the stack. This is not is the same order as VBR processors. |
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233 | * The ISR handler takes the format and uses it for dispatching the user |
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234 | * handler. |
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235 | * |
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236 | * FIXME : should be moved to below CPU_INTERRUPT_NUMBER_OF_VECTORS |
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237 | * |
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238 | */ |
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239 | |
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240 | typedef struct { |
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241 | uint16_t move_a7; /* move #FORMAT_ID,%a7@- */ |
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242 | uint16_t format_id; |
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243 | uint16_t jmp; /* jmp _ISR_Handlers */ |
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244 | uint32_t isr_handler; |
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245 | } _CPU_ISR_handler_entry; |
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246 | |
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247 | #define M68K_MOVE_A7 0x3F3C |
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248 | #define M68K_JMP 0x4EF9 |
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249 | |
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250 | /* points to jsr-exception-table in targets wo/ VBR register */ |
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251 | SCORE_EXTERN _CPU_ISR_handler_entry _CPU_ISR_jump_table[256]; |
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252 | |
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253 | #endif /* M68K_HAS_VBR */ |
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254 | #endif /* ASM */ |
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255 | |
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256 | /* constants */ |
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257 | |
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258 | /* |
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259 | * This defines the number of levels and the mask used to pick those |
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260 | * bits out of a thread mode. |
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261 | */ |
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262 | |
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263 | #define CPU_MODES_INTERRUPT_LEVEL 0x00000007 /* interrupt level in mode */ |
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264 | #define CPU_MODES_INTERRUPT_MASK 0x00000007 /* interrupt level in mode */ |
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265 | |
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266 | /* |
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267 | * context size area for floating point |
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268 | */ |
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269 | |
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270 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
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271 | |
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272 | /* |
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273 | * extra stack required by the MPCI receive server thread |
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274 | */ |
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275 | |
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276 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 |
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277 | |
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278 | /* |
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279 | * m68k family supports 256 distinct vectors. |
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280 | */ |
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281 | |
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282 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 |
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283 | #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) |
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284 | |
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285 | /* |
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286 | * This is defined if the port has a special way to report the ISR nesting |
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287 | * level. Most ports maintain the variable _ISR_Nest_level. |
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288 | */ |
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289 | |
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290 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
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291 | |
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292 | /* |
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293 | * Minimum size of a thread's stack. |
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294 | */ |
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295 | |
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296 | #define CPU_STACK_MINIMUM_SIZE 4096 |
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297 | |
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298 | /* |
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299 | * m68k is pretty tolerant of alignment. Just put things on 4 byte boundaries. |
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300 | */ |
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301 | |
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302 | #define CPU_ALIGNMENT 4 |
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303 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
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304 | #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT |
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305 | |
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306 | /* |
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307 | * On m68k thread stacks require no further alignment after allocation |
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308 | * from the Workspace. |
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309 | */ |
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310 | |
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311 | #define CPU_STACK_ALIGNMENT 0 |
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312 | |
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313 | #ifndef ASM |
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314 | |
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315 | /* macros */ |
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316 | |
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317 | /* |
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318 | * ISR handler macros |
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319 | * |
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320 | * These macros perform the following functions: |
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321 | * + initialize the RTEMS vector table |
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322 | * + disable all maskable CPU interrupts |
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323 | * + restore previous interrupt level (enable) |
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324 | * + temporarily restore interrupts (flash) |
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325 | * + set a particular level |
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326 | */ |
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327 | |
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328 | #define _CPU_Initialize_vectors() |
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329 | |
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330 | #define _CPU_ISR_Disable( _level ) \ |
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331 | m68k_disable_interrupts( _level ) |
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332 | |
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333 | #define _CPU_ISR_Enable( _level ) \ |
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334 | m68k_enable_interrupts( _level ) |
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335 | |
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336 | #define _CPU_ISR_Flash( _level ) \ |
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337 | m68k_flash_interrupts( _level ) |
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338 | |
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339 | #define _CPU_ISR_Set_level( _newlevel ) \ |
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340 | m68k_set_interrupt_level( _newlevel ) |
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341 | |
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342 | uint32_t _CPU_ISR_Get_level( void ); |
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343 | |
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344 | /* end of ISR handler macros */ |
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345 | |
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346 | /* |
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347 | * Context handler macros |
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348 | * |
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349 | * These macros perform the following functions: |
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350 | * + initialize a context area |
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351 | * + restart the current thread |
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352 | * + calculate the initial pointer into a FP context area |
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353 | * + initialize an FP context area |
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354 | */ |
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355 | |
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356 | #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ |
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357 | _isr, _entry_point, _is_fp ) \ |
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358 | do { \ |
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359 | uint32_t _stack; \ |
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360 | \ |
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361 | (_the_context)->sr = 0x3000 | ((_isr) << 8); \ |
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362 | _stack = (uint32_t )(_stack_base) + (_size) - 4; \ |
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363 | (_the_context)->a7_msp = (void *)_stack; \ |
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364 | *(void **)_stack = (void *)(_entry_point); \ |
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365 | } while ( 0 ) |
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366 | |
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367 | #define _CPU_Context_Restart_self( _the_context ) \ |
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368 | { asm volatile( "movew %0,%%sr ; " \ |
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369 | "moval %1,%%a7 ; " \ |
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370 | "rts" \ |
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371 | : "=d" ((_the_context)->sr), "=d" ((_the_context)->a7_msp) \ |
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372 | : "0" ((_the_context)->sr), "1" ((_the_context)->a7_msp) ); \ |
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373 | } |
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374 | |
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375 | /* |
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376 | * Floating Point Context Area Support routines |
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377 | */ |
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378 | |
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379 | #if (CPU_SOFTWARE_FP == TRUE) |
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380 | |
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381 | /* |
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382 | * This software FP implementation is only for GCC. |
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383 | */ |
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384 | |
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385 | #define _CPU_Context_Fp_start( _base, _offset ) \ |
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386 | ((void *) _Addresses_Add_offset( (_base), (_offset) ) ) |
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387 | |
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388 | |
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389 | #define _CPU_Context_Initialize_fp( _fp_area ) \ |
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390 | { \ |
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391 | Context_Control_fp *_fp; \ |
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392 | _fp = *(Context_Control_fp **)_fp_area; \ |
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393 | _fp->_exception_bits = 0; \ |
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394 | _fp->_trap_enable_bits = 0; \ |
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395 | _fp->_sticky_bits = 0; \ |
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396 | _fp->_rounding_mode = 0; /* ROUND_TO_NEAREST */ \ |
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397 | _fp->_format = 0; /* NIL */ \ |
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398 | _fp->_last_operation = 0; /* NOOP */ \ |
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399 | _fp->_operand1.df = 0; \ |
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400 | _fp->_operand2.df = 0; \ |
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401 | } |
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402 | #else |
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403 | #define _CPU_Context_Fp_start( _base, _offset ) \ |
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404 | ((void *) \ |
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405 | _Addresses_Add_offset( \ |
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406 | (_base), \ |
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407 | (_offset) + CPU_CONTEXT_FP_SIZE - 4 \ |
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408 | ) \ |
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409 | ) |
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410 | |
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411 | #define _CPU_Context_Initialize_fp( _fp_area ) \ |
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412 | { uint32_t *_fp_context = (uint32_t *)*(_fp_area); \ |
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413 | \ |
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414 | *(--(_fp_context)) = 0; \ |
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415 | *(_fp_area) = (uint8_t *)(_fp_context); \ |
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416 | } |
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417 | #endif |
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418 | |
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419 | /* end of Context handler macros */ |
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420 | |
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421 | /* |
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422 | * _CPU_Thread_Idle_body |
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423 | * |
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424 | * This routine is the CPU dependent IDLE thread body. |
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425 | * |
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426 | * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY |
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427 | * is TRUE. |
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428 | */ |
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429 | |
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430 | void _CPU_Thread_Idle_body( void ); |
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431 | |
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432 | /* |
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433 | * Fatal Error manager macros |
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434 | * |
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435 | * These macros perform the following functions: |
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436 | * + disable interrupts and halt the CPU |
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437 | */ |
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438 | |
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439 | #if ( defined(__mcoldfire__) ) |
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440 | #define _CPU_Fatal_halt( _error ) \ |
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441 | { asm volatile( "move.w %%sr,%%d0\n\t" \ |
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442 | "or.l %2,%%d0\n\t" \ |
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443 | "move.w %%d0,%%sr\n\t" \ |
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444 | "move.l %1,%%d0\n\t" \ |
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445 | "move.l #0xDEADBEEF,%%d1\n\t" \ |
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446 | "halt" \ |
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447 | : "=g" (_error) \ |
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448 | : "0" (_error), "d"(0x0700) \ |
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449 | : "d0", "d1" ); \ |
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450 | } |
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451 | #else |
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452 | #define _CPU_Fatal_halt( _error ) \ |
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453 | { asm volatile( "movl %0,%%d0; " \ |
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454 | "orw #0x0700,%%sr; " \ |
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455 | "stop #0x2700" : "=d" ((_error)) : "0" ((_error)) ); \ |
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456 | } |
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457 | #endif |
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458 | |
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459 | /* end of Fatal Error manager macros */ |
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460 | |
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461 | /* |
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462 | * Bitfield handler macros |
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463 | * |
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464 | * These macros perform the following functions: |
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465 | * + scan for the highest numbered (MSB) set in a 16 bit bitfield |
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466 | * |
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467 | * NOTE: |
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468 | * |
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469 | * It appears that on the M68020 bitfield are always 32 bits wide |
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470 | * when in a register. This code forces the bitfield to be in |
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471 | * memory (it really always is anyway). This allows us to |
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472 | * have a real 16 bit wide bitfield which operates "correctly." |
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473 | */ |
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474 | |
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475 | #define CPU_USE_GENERIC_BITFIELD_CODE FALSE |
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476 | #define CPU_USE_GENERIC_BITFIELD_DATA FALSE |
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477 | |
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478 | #if ( M68K_HAS_BFFFO == 1 ) |
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479 | |
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480 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
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481 | asm volatile( "bfffo (%1),#0,#16,%0" : "=d" (_output) : "a" (&_value)); |
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482 | |
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483 | #elif ( M68K_HAS_ISA_APLUS == 1 ) |
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484 | /* This is simplified by the fact that RTEMS never calls it with _value=0 */ |
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485 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
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486 | asm volatile ( \ |
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487 | " swap %0\n" \ |
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488 | " ff1.l %0\n" \ |
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489 | : "=d" ((_output)) \ |
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490 | : "0" ((_value)) \ |
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491 | : "cc" ) ; |
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492 | |
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493 | #else |
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494 | /* duplicates BFFFO results for 16 bits (i.e., 15-(_priority) in |
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495 | _CPU_Priority_bits_index is not needed), handles the 0 case, and |
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496 | does not molest _value -- jsg */ |
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497 | #if ( defined(__mcoldfire__) ) |
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498 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
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499 | { \ |
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500 | extern const unsigned char __BFFFOtable[256]; \ |
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501 | register int dumby; \ |
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502 | \ |
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503 | asm volatile ( \ |
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504 | " clr.l %1\n" \ |
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505 | " move.w %2,%1\n" \ |
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506 | " lsr.l #8,%1\n" \ |
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507 | " beq.s 1f\n" \ |
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508 | " move.b (%3,%1),%0\n" \ |
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509 | " bra.s 0f\n" \ |
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510 | "1: move.w %2,%1\n" \ |
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511 | " move.b (%3,%1),%0\n" \ |
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512 | " addq.l #8,%0\n" \ |
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513 | "0: and.l #0xff,%0\n" \ |
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514 | : "=&d" ((_output)), "=&d" ((dumby)) \ |
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515 | : "d" ((_value)), "ao" ((__BFFFOtable)) \ |
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516 | : "cc" ) ; \ |
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517 | } |
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518 | #elif ( M68K_HAS_EXTB_L == 1 ) |
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519 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
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520 | { \ |
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521 | extern const unsigned char __BFFFOtable[256]; \ |
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522 | register int dumby; \ |
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523 | \ |
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524 | asm volatile ( " move.w %2,%1\n" \ |
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525 | " lsr.w #8,%1\n" \ |
---|
526 | " beq.s 1f\n" \ |
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527 | " move.b (%3,%1.w),%0\n" \ |
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528 | " extb.l %0\n" \ |
---|
529 | " bra.s 0f\n" \ |
---|
530 | "1: moveq.l #8,%0\n" \ |
---|
531 | " add.b (%3,%2.w),%0\n" \ |
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532 | "0:\n" \ |
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533 | : "=&d" ((_output)), "=&d" ((dumby)) \ |
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534 | : "d" ((_value)), "ao" ((__BFFFOtable)) \ |
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535 | : "cc" ) ; \ |
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536 | } |
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537 | #else |
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538 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
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539 | { \ |
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540 | extern const unsigned char __BFFFOtable[256]; \ |
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541 | register int dumby; \ |
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542 | \ |
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543 | asm volatile ( " move.w %2,%1\n" \ |
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544 | " lsr.w #8,%1\n" \ |
---|
545 | " beq.s 1f\n" \ |
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546 | " move.b (%3,%1.w),%0\n" \ |
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547 | " and.l #0x000000ff,%0\n"\ |
---|
548 | " bra.s 0f\n" \ |
---|
549 | "1: moveq.l #8,%0\n" \ |
---|
550 | " add.b (%3,%2.w),%0\n" \ |
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551 | "0:\n" \ |
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552 | : "=&d" ((_output)), "=&d" ((dumby)) \ |
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553 | : "d" ((_value)), "ao" ((__BFFFOtable)) \ |
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554 | : "cc" ) ; \ |
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555 | } |
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556 | #endif |
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557 | |
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558 | #endif |
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559 | |
---|
560 | /* end of Bitfield handler macros */ |
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561 | |
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562 | /* |
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563 | * Priority handler macros |
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564 | * |
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565 | * These macros perform the following functions: |
---|
566 | * + return a mask with the bit for this major/minor portion of |
---|
567 | * of thread priority set. |
---|
568 | * + translate the bit number returned by "Bitfield_find_first_bit" |
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569 | * into an index into the thread ready chain bit maps |
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570 | */ |
---|
571 | |
---|
572 | #define _CPU_Priority_Mask( _bit_number ) \ |
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573 | ( 0x8000 >> (_bit_number) ) |
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574 | |
---|
575 | #define _CPU_Priority_bits_index( _priority ) \ |
---|
576 | (_priority) |
---|
577 | |
---|
578 | /* end of Priority handler macros */ |
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579 | |
---|
580 | /* functions */ |
---|
581 | |
---|
582 | /* |
---|
583 | * _CPU_Initialize |
---|
584 | * |
---|
585 | * This routine performs CPU dependent initialization. |
---|
586 | */ |
---|
587 | |
---|
588 | void _CPU_Initialize( |
---|
589 | rtems_cpu_table *cpu_table, |
---|
590 | void (*thread_dispatch) |
---|
591 | ); |
---|
592 | |
---|
593 | /* |
---|
594 | * _CPU_ISR_install_raw_handler |
---|
595 | * |
---|
596 | * This routine installs a "raw" interrupt handler directly into the |
---|
597 | * processor's vector table. |
---|
598 | */ |
---|
599 | |
---|
600 | void _CPU_ISR_install_raw_handler( |
---|
601 | uint32_t vector, |
---|
602 | proc_ptr new_handler, |
---|
603 | proc_ptr *old_handler |
---|
604 | ); |
---|
605 | |
---|
606 | /* |
---|
607 | * _CPU_ISR_install_vector |
---|
608 | * |
---|
609 | * This routine installs an interrupt vector. |
---|
610 | */ |
---|
611 | |
---|
612 | void _CPU_ISR_install_vector( |
---|
613 | uint32_t vector, |
---|
614 | proc_ptr new_handler, |
---|
615 | proc_ptr *old_handler |
---|
616 | ); |
---|
617 | |
---|
618 | /* |
---|
619 | * _CPU_Install_interrupt_stack |
---|
620 | * |
---|
621 | * This routine installs the hardware interrupt stack pointer. |
---|
622 | */ |
---|
623 | |
---|
624 | void _CPU_Install_interrupt_stack( void ); |
---|
625 | |
---|
626 | /* |
---|
627 | * _CPU_Context_switch |
---|
628 | * |
---|
629 | * This routine switches from the run context to the heir context. |
---|
630 | */ |
---|
631 | |
---|
632 | void _CPU_Context_switch( |
---|
633 | Context_Control *run, |
---|
634 | Context_Control *heir |
---|
635 | ); |
---|
636 | |
---|
637 | /* |
---|
638 | * _CPU_Context_save_fp |
---|
639 | * |
---|
640 | * This routine saves the floating point context passed to it. |
---|
641 | */ |
---|
642 | |
---|
643 | void _CPU_Context_save_fp( |
---|
644 | Context_Control_fp **fp_context_ptr |
---|
645 | ); |
---|
646 | |
---|
647 | /* |
---|
648 | * _CPU_Context_restore_fp |
---|
649 | * |
---|
650 | * This routine restores the floating point context passed to it. |
---|
651 | */ |
---|
652 | |
---|
653 | void _CPU_Context_restore_fp( |
---|
654 | Context_Control_fp **fp_context_ptr |
---|
655 | ); |
---|
656 | |
---|
657 | #if (M68K_HAS_FPSP_PACKAGE == 1) |
---|
658 | /* |
---|
659 | * Hooks for the Floating Point Support Package (FPSP) provided by Motorola |
---|
660 | * |
---|
661 | * NOTES: |
---|
662 | * |
---|
663 | * Motorola 68k family CPU's before the 68040 used a coprocessor |
---|
664 | * (68881 or 68882) to handle floating point. The 68040 has internal |
---|
665 | * floating point support -- but *not* the complete support provided by |
---|
666 | * the 68881 or 68882. The leftover functions are taken care of by the |
---|
667 | * M68040 Floating Point Support Package. Quoting from the MC68040 |
---|
668 | * Microprocessors User's Manual, Section 9, Floating-Point Unit (MC68040): |
---|
669 | * |
---|
670 | * "When used with the M68040FPSP, the MC68040 FPU is fully |
---|
671 | * compliant with IEEE floating-point standards." |
---|
672 | * |
---|
673 | * M68KFPSPInstallExceptionHandlers is in libcpu/m68k/MODEL/fpsp and |
---|
674 | * is invoked early in the application code to ensure that proper FP |
---|
675 | * behavior is installed. This is not left to the BSP to call, since |
---|
676 | * this would force all applications using that BSP to use FPSP which |
---|
677 | * is not necessarily desirable. |
---|
678 | * |
---|
679 | * There is a similar package for the 68060 but RTEMS does not yet |
---|
680 | * support the 68060. |
---|
681 | */ |
---|
682 | |
---|
683 | void M68KFPSPInstallExceptionHandlers (void); |
---|
684 | |
---|
685 | SCORE_EXTERN int (*_FPSP_install_raw_handler)( |
---|
686 | uint32_t vector, |
---|
687 | proc_ptr new_handler, |
---|
688 | proc_ptr *old_handler |
---|
689 | ); |
---|
690 | |
---|
691 | #endif |
---|
692 | |
---|
693 | |
---|
694 | #endif |
---|
695 | |
---|
696 | #ifdef __cplusplus |
---|
697 | } |
---|
698 | #endif |
---|
699 | |
---|
700 | #endif |
---|