source: rtems/cpukit/score/cpu/m68k/rtems/score/cpu.h @ 815994f

4.11
Last change on this file since 815994f was 815994f, checked in by Sebastian Huber <sebastian.huber@…>, on Nov 25, 2012 at 4:48:11 PM

score: Add CPU_Exception_frame

Add CPU port type CPU_Exception_frame and function
_CPU_Exception_frame_print().

The CPU ports of avr, bfin, h8300, lm32, m32c, m32r, m68k, nios2, sh,
sparc64, and v850 use an empty default implementation of
_CPU_Exception_frame_print().

Add rtems_exception_frame and rtems_exception_frame_print().

Add RTEMS_FATAL_SOURCE_EXCEPTION for CPU exceptions. Use rtems_fatal()
with source RTEMS_FATAL_SOURCE_EXCEPTION in CPU ports of i386, powerpc,
and sparc for unexpected exceptions.

Add third parameter to RTEMS_BSP_CLEANUP_OPTIONS() which controls the
BSP_PRINT_EXCEPTION_CONTEXT define used in the default
bsp_fatal_extension().

Add test sptests/spfatal26.

  • Property mode set to 100644
File size: 20.5 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  This include file contains information pertaining to the Motorola
7 *  m68xxx processor family.
8 *
9 *  COPYRIGHT (c) 1989-2011.
10 *  On-Line Applications Research Corporation (OAR).
11 *
12 *  The license and distribution terms for this file may be
13 *  found in the file LICENSE in this distribution or at
14 *  http://www.rtems.com/license/LICENSE.
15 */
16
17#ifndef _RTEMS_SCORE_CPU_H
18#define _RTEMS_SCORE_CPU_H
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
24#include <rtems/score/types.h>
25#include <rtems/score/m68k.h>
26
27/* conditional compilation parameters */
28
29#define CPU_INLINE_ENABLE_DISPATCH       TRUE
30#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
31
32/*
33 *  Does the CPU follow the simple vectored interrupt model?
34 *
35 *  If TRUE, then RTEMS allocates the vector table it internally manages.
36 *  If FALSE, then the BSP is assumed to allocate and manage the vector
37 *  table
38 *
39 *  M68K Specific Information:
40 *
41 *  XXX document implementation including references if appropriate
42 */
43#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
44
45/*
46 *  Use the m68k's hardware interrupt stack support and have the
47 *  interrupt manager allocate the memory for it.
48 */
49
50#if ( M68K_HAS_SEPARATE_STACKS == 1)
51#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 0
52#define CPU_HAS_HARDWARE_INTERRUPT_STACK 1
53#else
54#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 1
55#define CPU_HAS_HARDWARE_INTERRUPT_STACK 0
56#endif
57#define CPU_ALLOCATE_INTERRUPT_STACK     1
58
59/*
60 *  Does the RTEMS invoke the user's ISR with the vector number and
61 *  a pointer to the saved interrupt frame (1) or just the vector
62 *  number (0)?
63 */
64
65#define CPU_ISR_PASSES_FRAME_POINTER 0
66
67/*
68 *  Some family members have no FP, some have an FPU such as the
69 *  MC68881/MC68882 for the MC68020, others have it built in (MC68030, 040).
70 *
71 *  NOTE:  If on a CPU without hardware FP, then one can use software
72 *         emulation.  The gcc software FP emulation code has data which
73 *         must be contexted switched on a per task basis.
74 */
75
76#if ( M68K_HAS_FPU == 1 ) || ( M68K_HAS_EMAC == 1 )
77  #define CPU_HARDWARE_FP TRUE
78  #define CPU_SOFTWARE_FP FALSE
79#else
80  #define CPU_HARDWARE_FP FALSE
81  #if defined( __GNUC__ )
82    #define CPU_SOFTWARE_FP TRUE
83  #else
84    #define CPU_SOFTWARE_FP FALSE
85  #endif
86#endif
87
88/*
89 *  All tasks are not by default floating point tasks on this CPU.
90 *  The IDLE task does not have a floating point context on this CPU.
91 *  It is safe to use the deferred floating point context switch
92 *  algorithm on this CPU.
93 */
94
95#define CPU_ALL_TASKS_ARE_FP             FALSE
96#define CPU_IDLE_TASK_IS_FP              FALSE
97#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
98
99#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
100#define CPU_STACK_GROWS_UP               FALSE
101#define CPU_STRUCTURE_ALIGNMENT          __attribute__ ((aligned (4)))
102
103#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
104
105/*
106 *  Define what is required to specify how the network to host conversion
107 *  routines are handled.
108 */
109
110#define CPU_BIG_ENDIAN                           TRUE
111#define CPU_LITTLE_ENDIAN                        FALSE
112
113#if ( CPU_HARDWARE_FP == TRUE ) && !defined( __mcoldfire__ )
114  #if defined( __mc68060__ )
115    #define M68K_FP_STATE_SIZE 16
116  #else
117    #define M68K_FP_STATE_SIZE 216
118  #endif
119#endif
120
121#ifndef ASM
122
123/* structures */
124
125/*
126 *  Basic integer context for the m68k family.
127 */
128
129typedef struct {
130  uint32_t    sr;                /* (sr) status register */
131  uint32_t    d2;                /* (d2) data register 2 */
132  uint32_t    d3;                /* (d3) data register 3 */
133  uint32_t    d4;                /* (d4) data register 4 */
134  uint32_t    d5;                /* (d5) data register 5 */
135  uint32_t    d6;                /* (d6) data register 6 */
136  uint32_t    d7;                /* (d7) data register 7 */
137  void       *a2;                /* (a2) address register 2 */
138  void       *a3;                /* (a3) address register 3 */
139  void       *a4;                /* (a4) address register 4 */
140  void       *a5;                /* (a5) address register 5 */
141  void       *a6;                /* (a6) address register 6 */
142  void       *a7_msp;            /* (a7) master stack pointer */
143  #if defined( __mcoldfire__ ) && ( M68K_HAS_FPU == 1 )
144    uint8_t   fpu_dis;
145  #endif
146} Context_Control;
147
148#define _CPU_Context_Get_SP( _context ) \
149  (_context)->a7_msp
150
151/*
152 *  Floating point context areas and support routines
153 */
154
155#if ( CPU_SOFTWARE_FP == TRUE )
156  /*
157   *  This is the same as gcc's view of the software FP condition code
158   *  register _fpCCR.  The implementation of the emulation code is
159   *  in the gcc-VERSION/config/m68k directory.  This structure is
160   *  correct as of gcc 2.7.2.2.
161   */
162  typedef struct {
163    uint16_t _exception_bits;
164    uint16_t _trap_enable_bits;
165    uint16_t _sticky_bits;
166    uint16_t _rounding_mode;
167    uint16_t _format;
168    uint16_t _last_operation;
169    union {
170      float sf;
171      double df;
172    } _operand1;
173    union {
174      float sf;
175      double df;
176    } _operand2;
177  } Context_Control_fp;
178
179  /*
180   *  This software FP implementation is only for GCC.
181   */
182  #define _CPU_Context_Fp_start( _base, _offset ) \
183     ((void *) _Addresses_Add_offset( (_base), (_offset) ) )
184
185  #define _CPU_Context_Initialize_fp( _fp_area ) \
186     { \
187       Context_Control_fp *_fp; \
188       _fp = *(Context_Control_fp **)_fp_area; \
189       _fp->_exception_bits = 0; \
190       _fp->_trap_enable_bits = 0; \
191       _fp->_sticky_bits = 0; \
192       _fp->_rounding_mode = 0;  /* ROUND_TO_NEAREST */ \
193       _fp->_format = 0;         /* NIL */ \
194       _fp->_last_operation = 0; /* NOOP */ \
195       _fp->_operand1.df = 0; \
196       _fp->_operand2.df = 0; \
197     }
198#endif
199
200#if ( CPU_HARDWARE_FP == TRUE )
201  #if defined( __mcoldfire__ )
202    /* We need memset() to initialize the FP context */
203    #include <string.h>
204
205    #if ( M68K_HAS_FPU == 1 )
206      /*
207       * The Cache Control Register (CACR) has write-only access.  It is also
208       * used to enable and disable the FPU.  We need to maintain a copy of
209       * this register to allow per thread values.
210       */
211      extern uint32_t _CPU_cacr_shadow;
212    #endif
213
214    /* We assume that each ColdFire core with a FPU has also an EMAC unit */
215    typedef struct {
216      uint32_t emac_macsr;
217      uint32_t emac_acc0;
218      uint32_t emac_acc1;
219      uint32_t emac_acc2;
220      uint32_t emac_acc3;
221      uint32_t emac_accext01;
222      uint32_t emac_accext23;
223      uint32_t emac_mask;
224      #if ( M68K_HAS_FPU == 1 )
225        uint16_t fp_state_format;
226        uint16_t fp_state_fpcr;
227        double fp_state_op;
228        uint32_t fp_state_fpsr;
229
230        /*
231         * We need to save the FP Instruction Address Register (FPIAR), because
232         * a context switch can occur within a FP exception before the handler
233         * was able to save this register.
234         */
235        uint32_t fp_fpiar;
236
237        double fp_data [8];
238      #endif
239    } Context_Control_fp;
240
241    #define _CPU_Context_Fp_start( _base, _offset ) \
242      ((void *) _Addresses_Add_offset( (_base), (_offset) ))
243
244    /*
245     * The reset value for all context relevant registers except the FP data
246     * registers is zero.  The reset value of the FP data register is NAN.  The
247     * restore of the reset FP state will reset the FP data registers, so the
248     * initial value of them can be arbitrary here.
249     */
250    #define _CPU_Context_Initialize_fp( _fp_area ) \
251      memset( *(_fp_area), 0, sizeof( Context_Control_fp ) )
252  #else
253    /*
254     *  FP context save area for the M68881/M68882 and 68060 numeric coprocessors.
255     */
256
257    typedef struct {
258      /*
259       * M68K_FP_STATE_SIZE bytes for FSAVE/FRESTORE
260       * 96 bytes for FMOVEM FP0-7
261       * 12 bytes for FMOVEM CREGS
262       * 4 bytes for non-null flag
263       */
264      uint8_t fp_save_area [M68K_FP_STATE_SIZE + 112];
265    } Context_Control_fp;
266
267    #define _CPU_Context_Fp_start( _base, _offset ) \
268       ( \
269         (void *) _Addresses_Add_offset( \
270            (_base), \
271            (_offset) + CPU_CONTEXT_FP_SIZE - 4 \
272         ) \
273       )
274
275    #define _CPU_Context_Initialize_fp( _fp_area ) \
276       { \
277         uint32_t   *_fp_context = (uint32_t *)*(_fp_area); \
278         *(--(_fp_context)) = 0; \
279         *(_fp_area) = (void *)(_fp_context); \
280       }
281  #endif
282#endif
283
284/*
285 *  The following structures define the set of information saved
286 *  on the current stack by RTEMS upon receipt of each exc/interrupt.
287 *  These are not used by m68k handlers.
288 *  The exception frame is for rdbg.
289 */
290
291typedef struct {
292  uint32_t   vecnum; /* vector number */
293} CPU_Interrupt_frame;
294
295typedef struct {
296  uint32_t   vecnum; /* vector number */
297  uint32_t   sr; /* status register */
298  uint32_t   pc; /* program counter */
299  uint32_t   d0, d1, d2, d3, d4, d5, d6, d7;
300  uint32_t   a0, a1, a2, a3, a4, a5, a6, a7;
301} CPU_Exception_frame;
302
303/* variables */
304
305extern void*                     _VBR;
306
307#if ( M68K_HAS_VBR == 0 )
308
309/*
310 * Table of ISR handler entries that resides in RAM. The FORMAT/ID is
311 * pushed onto the stack. This is not is the same order as VBR processors.
312 * The ISR handler takes the format and uses it for dispatching the user
313 * handler.
314 *
315 * FIXME : should be moved to below CPU_INTERRUPT_NUMBER_OF_VECTORS
316 *
317 */
318
319typedef struct {
320  uint16_t   move_a7;            /* move #FORMAT_ID,%a7@- */
321  uint16_t   format_id;
322  uint16_t   jmp;                /* jmp  _ISR_Handlers */
323  uint32_t   isr_handler;
324} _CPU_ISR_handler_entry;
325
326#define M68K_MOVE_A7 0x3F3C
327#define M68K_JMP     0x4EF9
328
329      /* points to jsr-exception-table in targets wo/ VBR register */
330SCORE_EXTERN _CPU_ISR_handler_entry _CPU_ISR_jump_table[256];
331
332#endif /* M68K_HAS_VBR */
333
334#endif /* ASM */
335
336/* constants */
337
338/*
339 *  This defines the number of levels and the mask used to pick those
340 *  bits out of a thread mode.
341 */
342
343#define CPU_MODES_INTERRUPT_LEVEL  0x00000007 /* interrupt level in mode */
344#define CPU_MODES_INTERRUPT_MASK   0x00000007 /* interrupt level in mode */
345
346/*
347 *  context size area for floating point
348 */
349
350#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
351
352/*
353 *  extra stack required by the MPCI receive server thread
354 */
355
356#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
357
358/*
359 *  m68k family supports 256 distinct vectors.
360 */
361
362#define CPU_INTERRUPT_NUMBER_OF_VECTORS      256
363#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
364
365/*
366 *  This is defined if the port has a special way to report the ISR nesting
367 *  level.  Most ports maintain the variable _ISR_Nest_level.
368 */
369
370#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
371
372/*
373 *  Minimum size of a thread's stack.
374 */
375
376#define CPU_STACK_MINIMUM_SIZE           M68K_CPU_STACK_MINIMUM_SIZE
377
378/*
379 *  Maximum priority of a thread. Note based from 0 which is the idle task.
380 */
381#define CPU_PRIORITY_MAXIMUM             M68K_CPU_PRIORITY_MAXIMUM
382
383#define CPU_SIZEOF_POINTER 4
384
385/*
386 *  m68k is pretty tolerant of alignment.  Just put things on 4 byte boundaries.
387 */
388
389#define CPU_ALIGNMENT                    4
390#define CPU_HEAP_ALIGNMENT               CPU_ALIGNMENT
391#define CPU_PARTITION_ALIGNMENT          CPU_ALIGNMENT
392
393/*
394 *  On m68k thread stacks require no further alignment after allocation
395 *  from the Workspace.
396 */
397
398#define CPU_STACK_ALIGNMENT        0
399
400#ifndef ASM
401
402/* macros */
403
404/*
405 *  ISR handler macros
406 *
407 *  These macros perform the following functions:
408 *     + initialize the RTEMS vector table
409 *     + disable all maskable CPU interrupts
410 *     + restore previous interrupt level (enable)
411 *     + temporarily restore interrupts (flash)
412 *     + set a particular level
413 */
414
415#define _CPU_Initialize_vectors()
416
417#define _CPU_ISR_Disable( _level ) \
418  m68k_disable_interrupts( _level )
419
420#define _CPU_ISR_Enable( _level ) \
421  m68k_enable_interrupts( _level )
422
423#define _CPU_ISR_Flash( _level ) \
424  m68k_flash_interrupts( _level )
425
426#define _CPU_ISR_Set_level( _newlevel ) \
427   m68k_set_interrupt_level( _newlevel )
428
429uint32_t   _CPU_ISR_Get_level( void );
430
431/* end of ISR handler macros */
432
433/*
434 *  Context handler macros
435 *
436 *  These macros perform the following functions:
437 *     + initialize a context area
438 *     + restart the current thread
439 *     + calculate the initial pointer into a FP context area
440 *     + initialize an FP context area
441 */
442
443#if (defined(__mcoldfire__) && ( M68K_HAS_FPU == 1 ))
444#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
445                                 _isr, _entry_point, _is_fp ) \
446   do { \
447     uint32_t   _stack; \
448     \
449     (_the_context)->sr      = 0x3000 | ((_isr) << 8); \
450     _stack                  = (uint32_t)(_stack_base) + (_size) - 4; \
451     (_the_context)->a7_msp  = (void *)_stack; \
452     *(void **)_stack        = (void *)(_entry_point); \
453     (_the_context)->fpu_dis = (_is_fp == TRUE) ? 0x00 : 0x10;          \
454   } while ( 0 )
455#else
456#define _CPU_Context_Initialize( _the_context, _stack_base, _size,      \
457                                 _isr, _entry_point, _is_fp )           \
458   do {                                                                 \
459     uint32_t   _stack;                                                 \
460                                                                        \
461     (_the_context)->sr      = 0x3000 | ((_isr) << 8);                  \
462     _stack                  = (uint32_t)(_stack_base) + (_size) - 4;   \
463     (_the_context)->a7_msp  = (void *)_stack;                          \
464     *(void **)_stack        = (void *)(_entry_point);                  \
465   } while ( 0 )
466#endif
467
468/* end of Context handler macros */
469
470/*
471 *  _CPU_Thread_Idle_body
472 *
473 *  This routine is the CPU dependent IDLE thread body.
474 *
475 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
476 *         is TRUE.
477 */
478
479void *_CPU_Thread_Idle_body( uintptr_t ignored );
480
481/*
482 *  Fatal Error manager macros
483 *
484 *  These macros perform the following functions:
485 *    + disable interrupts and halt the CPU
486 */
487
488#if ( defined(__mcoldfire__) )
489#define _CPU_Fatal_halt( _error ) \
490  { __asm__ volatile( "move.w %%sr,%%d0\n\t" \
491                  "or.l %2,%%d0\n\t" \
492                  "move.w %%d0,%%sr\n\t" \
493                  "move.l %1,%%d0\n\t" \
494                  "move.l #0xDEADBEEF,%%d1\n\t" \
495                  "halt" \
496                  : "=g" (_error) \
497                  : "0" (_error), "d"(0x0700) \
498                  : "d0", "d1" ); \
499  }
500#else
501#define _CPU_Fatal_halt( _error ) \
502  { __asm__ volatile( "movl  %0,%%d0; " \
503                  "orw   #0x0700,%%sr; " \
504                  "stop  #0x2700" : "=d" ((_error)) : "0" ((_error)) ); \
505  }
506#endif
507
508/* end of Fatal Error manager macros */
509
510/*
511 *  Bitfield handler macros
512 *
513 *  These macros perform the following functions:
514 *     + scan for the highest numbered (MSB) set in a 16 bit bitfield
515 *
516 *  NOTE:
517 *
518 *    It appears that on the M68020 bitfield are always 32 bits wide
519 *    when in a register.  This code forces the bitfield to be in
520 *    memory (it really always is anyway). This allows us to
521 *    have a real 16 bit wide bitfield which operates "correctly."
522 */
523
524#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
525#define CPU_USE_GENERIC_BITFIELD_DATA FALSE
526
527#if ( M68K_HAS_BFFFO != 1 )
528/*
529 *  Lookup table for BFFFO simulation
530 */
531extern const unsigned char _CPU_m68k_BFFFO_table[256];
532#endif
533
534#if ( M68K_HAS_BFFFO == 1 )
535
536#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
537  __asm__ volatile( "bfffo (%1),#0,#16,%0" : "=d" (_output) : "a" (&_value));
538
539#elif ( __mcfisaaplus__ )
540  /* This is simplified by the fact that RTEMS never calls it with _value=0 */
541#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
542    __asm__ volatile ( \
543       "   swap     %0\n"        \
544       "   ff1.l    %0\n"        \
545       : "=d" ((_output))        \
546       : "0" ((_value))          \
547       : "cc" ) ;
548
549#else
550/* duplicates BFFFO results for 16 bits (i.e., 15-(_priority) in
551   _CPU_Priority_bits_index is not needed), handles the 0 case, and
552   does not molest _value -- jsg */
553#if ( defined(__mcoldfire__) )
554
555#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
556  { \
557    register int dumby; \
558    \
559    __asm__ volatile ( \
560       "   clr.l   %1\n"         \
561       "   move.w  %2,%1\n"      \
562       "   lsr.l   #8,%1\n"      \
563       "   beq.s   1f\n"         \
564       "   move.b  (%3,%1),%0\n" \
565       "   bra.s   0f\n"         \
566       "1: move.w  %2,%1\n"      \
567       "   move.b  (%3,%1),%0\n" \
568       "   addq.l  #8,%0\n"      \
569       "0: and.l   #0xff,%0\n"   \
570       : "=&d" ((_output)), "=&d" ((dumby))    \
571       : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \
572       : "cc" ) ; \
573  }
574#elif ( M68K_HAS_EXTB_L == 1 )
575#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
576  { \
577    register int dumby; \
578    \
579    __asm__ volatile ( "   move.w  %2,%1\n"        \
580       "   lsr.w   #8,%1\n"        \
581       "   beq.s   1f\n"           \
582       "   move.b  (%3,%1.w),%0\n" \
583       "   extb.l  %0\n"           \
584       "   bra.s   0f\n"           \
585       "1: moveq.l #8,%0\n"        \
586       "   add.b   (%3,%2.w),%0\n" \
587       "0:\n"                      \
588       : "=&d" ((_output)), "=&d" ((dumby)) \
589       : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \
590       : "cc" ) ; \
591  }
592#else
593#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
594  { \
595    register int dumby; \
596    \
597    __asm__ volatile ( "   move.w  %2,%1\n"        \
598       "   lsr.w   #8,%1\n"        \
599       "   beq.s   1f\n"           \
600       "   move.b  (%3,%1.w),%0\n" \
601       "   and.l   #0x000000ff,%0\n"\
602       "   bra.s   0f\n"           \
603       "1: moveq.l #8,%0\n"        \
604       "   add.b   (%3,%2.w),%0\n" \
605       "0:\n"                      \
606       : "=&d" ((_output)), "=&d" ((dumby)) \
607       : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \
608       : "cc" ) ; \
609  }
610#endif
611
612#endif
613
614/* end of Bitfield handler macros */
615
616/*
617 *  Priority handler macros
618 *
619 *  These macros perform the following functions:
620 *    + return a mask with the bit for this major/minor portion of
621 *      of thread priority set.
622 *    + translate the bit number returned by "Bitfield_find_first_bit"
623 *      into an index into the thread ready chain bit maps
624 */
625
626#define _CPU_Priority_Mask( _bit_number ) \
627  ( 0x8000 >> (_bit_number) )
628
629#define _CPU_Priority_bits_index( _priority ) \
630  (_priority)
631
632/* end of Priority handler macros */
633
634/* functions */
635
636/*
637 *  _CPU_Initialize
638 *
639 *  This routine performs CPU dependent initialization.
640 */
641
642void _CPU_Initialize(void);
643
644/*
645 *  _CPU_ISR_install_raw_handler
646 *
647 *  This routine installs a "raw" interrupt handler directly into the
648 *  processor's vector table.
649 */
650
651void _CPU_ISR_install_raw_handler(
652  uint32_t    vector,
653  proc_ptr    new_handler,
654  proc_ptr   *old_handler
655);
656
657/*
658 *  _CPU_ISR_install_vector
659 *
660 *  This routine installs an interrupt vector.
661 */
662
663void _CPU_ISR_install_vector(
664  uint32_t         vector,
665  proc_ptr         new_handler,
666  proc_ptr        *old_handler
667);
668
669/*
670 *  _CPU_Install_interrupt_stack
671 *
672 *  This routine installs the hardware interrupt stack pointer.
673 */
674
675void _CPU_Install_interrupt_stack( void );
676
677/*
678 *  _CPU_Context_switch
679 *
680 *  This routine switches from the run context to the heir context.
681 */
682
683void _CPU_Context_switch(
684  Context_Control  *run,
685  Context_Control  *heir
686);
687
688void _CPU_Context_Restart_self(
689  Context_Control  *the_context
690);
691
692/*
693 *  _CPU_Context_save_fp
694 *
695 *  This routine saves the floating point context passed to it.
696 */
697
698void _CPU_Context_save_fp(
699  Context_Control_fp **fp_context_ptr
700);
701
702/*
703 *  _CPU_Context_restore_fp
704 *
705 *  This routine restores the floating point context passed to it.
706 */
707
708void _CPU_Context_restore_fp(
709  Context_Control_fp **fp_context_ptr
710);
711
712void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
713
714#if (M68K_HAS_FPSP_PACKAGE == 1)
715/*
716 *  Hooks for the Floating Point Support Package (FPSP) provided by Motorola
717 *
718 *  NOTES:
719 *
720 *  Motorola 68k family CPU's before the 68040 used a coprocessor
721 *  (68881 or 68882) to handle floating point.  The 68040 has internal
722 *  floating point support -- but *not* the complete support provided by
723 *  the 68881 or 68882.  The leftover functions are taken care of by the
724 *  M68040 Floating Point Support Package.  Quoting from the MC68040
725 *  Microprocessors User's Manual, Section 9, Floating-Point Unit (MC68040):
726 *
727 *    "When used with the M68040FPSP, the MC68040 FPU is fully
728 *    compliant with IEEE floating-point standards."
729 *
730 *  M68KFPSPInstallExceptionHandlers is in libcpu/m68k/MODEL/fpsp and
731 *  is invoked early in the application code to ensure that proper FP
732 *  behavior is installed.  This is not left to the BSP to call, since
733 *  this would force all applications using that BSP to use FPSP which
734 *  is not necessarily desirable.
735 *
736 *  There is a similar package for the 68060 but RTEMS does not yet
737 *  support the 68060.
738 */
739
740void M68KFPSPInstallExceptionHandlers (void);
741
742SCORE_EXTERN int (*_FPSP_install_raw_handler)(
743  uint32_t   vector,
744  proc_ptr new_handler,
745  proc_ptr *old_handler
746);
747
748#endif
749
750
751#endif
752
753#ifdef __cplusplus
754}
755#endif
756
757#endif
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