source: rtems/cpukit/score/cpu/m68k/rtems/score/cpu.h @ 66fffc7

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1/**
2 * @file
3 *
4 * @brief Motorola M68K CPU Dependent Source
5 *
6 * This include file contains information pertaining to the Motorola
7 * m68xxx processor family.
8 */
9
10/*
11 *  COPYRIGHT (c) 1989-2011.
12 *  On-Line Applications Research Corporation (OAR).
13 *
14 *  The license and distribution terms for this file may be
15 *  found in the file LICENSE in this distribution or at
16 *  http://www.rtems.com/license/LICENSE.
17 */
18
19#ifndef _RTEMS_SCORE_CPU_H
20#define _RTEMS_SCORE_CPU_H
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26#include <rtems/score/types.h>
27#include <rtems/score/m68k.h>
28
29/* conditional compilation parameters */
30
31#define CPU_INLINE_ENABLE_DISPATCH       TRUE
32#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
33
34/*
35 *  Does the CPU follow the simple vectored interrupt model?
36 *
37 *  If TRUE, then RTEMS allocates the vector table it internally manages.
38 *  If FALSE, then the BSP is assumed to allocate and manage the vector
39 *  table
40 *
41 *  M68K Specific Information:
42 *
43 *  XXX document implementation including references if appropriate
44 */
45#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
46
47/*
48 *  Use the m68k's hardware interrupt stack support and have the
49 *  interrupt manager allocate the memory for it.
50 */
51
52#if ( M68K_HAS_SEPARATE_STACKS == 1)
53#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 0
54#define CPU_HAS_HARDWARE_INTERRUPT_STACK 1
55#else
56#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 1
57#define CPU_HAS_HARDWARE_INTERRUPT_STACK 0
58#endif
59#define CPU_ALLOCATE_INTERRUPT_STACK     1
60
61/*
62 *  Does the RTEMS invoke the user's ISR with the vector number and
63 *  a pointer to the saved interrupt frame (1) or just the vector
64 *  number (0)?
65 */
66
67#define CPU_ISR_PASSES_FRAME_POINTER 0
68
69/*
70 *  Some family members have no FP, some have an FPU such as the
71 *  MC68881/MC68882 for the MC68020, others have it built in (MC68030, 040).
72 *
73 *  NOTE:  If on a CPU without hardware FP, then one can use software
74 *         emulation.  The gcc software FP emulation code has data which
75 *         must be contexted switched on a per task basis.
76 */
77
78#if ( M68K_HAS_FPU == 1 ) || ( M68K_HAS_EMAC == 1 )
79  #define CPU_HARDWARE_FP TRUE
80  #define CPU_SOFTWARE_FP FALSE
81#else
82  #define CPU_HARDWARE_FP FALSE
83  #if defined( __GNUC__ )
84    #define CPU_SOFTWARE_FP TRUE
85  #else
86    #define CPU_SOFTWARE_FP FALSE
87  #endif
88#endif
89
90/*
91 *  All tasks are not by default floating point tasks on this CPU.
92 *  The IDLE task does not have a floating point context on this CPU.
93 *  It is safe to use the deferred floating point context switch
94 *  algorithm on this CPU.
95 */
96
97#define CPU_ALL_TASKS_ARE_FP             FALSE
98#define CPU_IDLE_TASK_IS_FP              FALSE
99#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
100
101#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
102#define CPU_STACK_GROWS_UP               FALSE
103#define CPU_STRUCTURE_ALIGNMENT          __attribute__ ((aligned (4)))
104
105#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
106
107/*
108 *  Define what is required to specify how the network to host conversion
109 *  routines are handled.
110 */
111
112#define CPU_BIG_ENDIAN                           TRUE
113#define CPU_LITTLE_ENDIAN                        FALSE
114
115#if ( CPU_HARDWARE_FP == TRUE ) && !defined( __mcoldfire__ )
116  #if defined( __mc68060__ )
117    #define M68K_FP_STATE_SIZE 16
118  #else
119    #define M68K_FP_STATE_SIZE 216
120  #endif
121#endif
122
123#ifndef ASM
124
125/* structures */
126
127/*
128 *  Basic integer context for the m68k family.
129 */
130
131typedef struct {
132  uint32_t    sr;                /* (sr) status register */
133  uint32_t    d2;                /* (d2) data register 2 */
134  uint32_t    d3;                /* (d3) data register 3 */
135  uint32_t    d4;                /* (d4) data register 4 */
136  uint32_t    d5;                /* (d5) data register 5 */
137  uint32_t    d6;                /* (d6) data register 6 */
138  uint32_t    d7;                /* (d7) data register 7 */
139  void       *a2;                /* (a2) address register 2 */
140  void       *a3;                /* (a3) address register 3 */
141  void       *a4;                /* (a4) address register 4 */
142  void       *a5;                /* (a5) address register 5 */
143  void       *a6;                /* (a6) address register 6 */
144  void       *a7_msp;            /* (a7) master stack pointer */
145  #if defined( __mcoldfire__ ) && ( M68K_HAS_FPU == 1 )
146    uint8_t   fpu_dis;
147  #endif
148} Context_Control;
149
150#define _CPU_Context_Get_SP( _context ) \
151  (_context)->a7_msp
152
153/*
154 *  Floating point context areas and support routines
155 */
156
157#if ( CPU_SOFTWARE_FP == TRUE )
158  /*
159   *  This is the same as gcc's view of the software FP condition code
160   *  register _fpCCR.  The implementation of the emulation code is
161   *  in the gcc-VERSION/config/m68k directory.  This structure is
162   *  correct as of gcc 2.7.2.2.
163   */
164  typedef struct {
165    uint16_t _exception_bits;
166    uint16_t _trap_enable_bits;
167    uint16_t _sticky_bits;
168    uint16_t _rounding_mode;
169    uint16_t _format;
170    uint16_t _last_operation;
171    union {
172      float sf;
173      double df;
174    } _operand1;
175    union {
176      float sf;
177      double df;
178    } _operand2;
179  } Context_Control_fp;
180
181  /*
182   *  This software FP implementation is only for GCC.
183   */
184  #define _CPU_Context_Fp_start( _base, _offset ) \
185     ((void *) _Addresses_Add_offset( (_base), (_offset) ) )
186
187  #define _CPU_Context_Initialize_fp( _fp_area ) \
188     { \
189       Context_Control_fp *_fp; \
190       _fp = *(Context_Control_fp **)_fp_area; \
191       _fp->_exception_bits = 0; \
192       _fp->_trap_enable_bits = 0; \
193       _fp->_sticky_bits = 0; \
194       _fp->_rounding_mode = 0;  /* ROUND_TO_NEAREST */ \
195       _fp->_format = 0;         /* NIL */ \
196       _fp->_last_operation = 0; /* NOOP */ \
197       _fp->_operand1.df = 0; \
198       _fp->_operand2.df = 0; \
199     }
200#endif
201
202#if ( CPU_HARDWARE_FP == TRUE )
203  #if defined( __mcoldfire__ )
204    /* We need memset() to initialize the FP context */
205    #include <string.h>
206
207    #if ( M68K_HAS_FPU == 1 )
208      /*
209       * The Cache Control Register (CACR) has write-only access.  It is also
210       * used to enable and disable the FPU.  We need to maintain a copy of
211       * this register to allow per thread values.
212       */
213      extern uint32_t _CPU_cacr_shadow;
214    #endif
215
216    /* We assume that each ColdFire core with a FPU has also an EMAC unit */
217    typedef struct {
218      uint32_t emac_macsr;
219      uint32_t emac_acc0;
220      uint32_t emac_acc1;
221      uint32_t emac_acc2;
222      uint32_t emac_acc3;
223      uint32_t emac_accext01;
224      uint32_t emac_accext23;
225      uint32_t emac_mask;
226      #if ( M68K_HAS_FPU == 1 )
227        uint16_t fp_state_format;
228        uint16_t fp_state_fpcr;
229        double fp_state_op;
230        uint32_t fp_state_fpsr;
231
232        /*
233         * We need to save the FP Instruction Address Register (FPIAR), because
234         * a context switch can occur within a FP exception before the handler
235         * was able to save this register.
236         */
237        uint32_t fp_fpiar;
238
239        double fp_data [8];
240      #endif
241    } Context_Control_fp;
242
243    #define _CPU_Context_Fp_start( _base, _offset ) \
244      ((void *) _Addresses_Add_offset( (_base), (_offset) ))
245
246    /*
247     * The reset value for all context relevant registers except the FP data
248     * registers is zero.  The reset value of the FP data register is NAN.  The
249     * restore of the reset FP state will reset the FP data registers, so the
250     * initial value of them can be arbitrary here.
251     */
252    #define _CPU_Context_Initialize_fp( _fp_area ) \
253      memset( *(_fp_area), 0, sizeof( Context_Control_fp ) )
254  #else
255    /*
256     *  FP context save area for the M68881/M68882 and 68060 numeric coprocessors.
257     */
258
259    typedef struct {
260      /*
261       * M68K_FP_STATE_SIZE bytes for FSAVE/FRESTORE
262       * 96 bytes for FMOVEM FP0-7
263       * 12 bytes for FMOVEM CREGS
264       * 4 bytes for non-null flag
265       */
266      uint8_t fp_save_area [M68K_FP_STATE_SIZE + 112];
267    } Context_Control_fp;
268
269    #define _CPU_Context_Fp_start( _base, _offset ) \
270       ( \
271         (void *) _Addresses_Add_offset( \
272            (_base), \
273            (_offset) + CPU_CONTEXT_FP_SIZE - 4 \
274         ) \
275       )
276
277    #define _CPU_Context_Initialize_fp( _fp_area ) \
278       { \
279         uint32_t   *_fp_context = (uint32_t *)*(_fp_area); \
280         *(--(_fp_context)) = 0; \
281         *(_fp_area) = (void *)(_fp_context); \
282       }
283  #endif
284#endif
285
286/*
287 *  The following structures define the set of information saved
288 *  on the current stack by RTEMS upon receipt of each exc/interrupt.
289 *  These are not used by m68k handlers.
290 *  The exception frame is for rdbg.
291 */
292
293typedef struct {
294  uint32_t   vecnum; /* vector number */
295} CPU_Interrupt_frame;
296
297typedef struct {
298  uint32_t   vecnum; /* vector number */
299  uint32_t   sr; /* status register */
300  uint32_t   pc; /* program counter */
301  uint32_t   d0, d1, d2, d3, d4, d5, d6, d7;
302  uint32_t   a0, a1, a2, a3, a4, a5, a6, a7;
303} CPU_Exception_frame;
304
305/* variables */
306
307extern void*                     _VBR;
308
309#if ( M68K_HAS_VBR == 0 )
310
311/*
312 * Table of ISR handler entries that resides in RAM. The FORMAT/ID is
313 * pushed onto the stack. This is not is the same order as VBR processors.
314 * The ISR handler takes the format and uses it for dispatching the user
315 * handler.
316 *
317 * FIXME : should be moved to below CPU_INTERRUPT_NUMBER_OF_VECTORS
318 *
319 */
320
321typedef struct {
322  uint16_t   move_a7;            /* move #FORMAT_ID,%a7@- */
323  uint16_t   format_id;
324  uint16_t   jmp;                /* jmp  _ISR_Handlers */
325  uint32_t   isr_handler;
326} _CPU_ISR_handler_entry;
327
328#define M68K_MOVE_A7 0x3F3C
329#define M68K_JMP     0x4EF9
330
331      /* points to jsr-exception-table in targets wo/ VBR register */
332SCORE_EXTERN _CPU_ISR_handler_entry _CPU_ISR_jump_table[256];
333
334#endif /* M68K_HAS_VBR */
335
336#endif /* ASM */
337
338/* constants */
339
340/*
341 *  This defines the number of levels and the mask used to pick those
342 *  bits out of a thread mode.
343 */
344
345#define CPU_MODES_INTERRUPT_LEVEL  0x00000007 /* interrupt level in mode */
346#define CPU_MODES_INTERRUPT_MASK   0x00000007 /* interrupt level in mode */
347
348/*
349 *  context size area for floating point
350 */
351
352#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
353
354/*
355 *  extra stack required by the MPCI receive server thread
356 */
357
358#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
359
360/*
361 *  m68k family supports 256 distinct vectors.
362 */
363
364#define CPU_INTERRUPT_NUMBER_OF_VECTORS      256
365#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
366
367/*
368 *  This is defined if the port has a special way to report the ISR nesting
369 *  level.  Most ports maintain the variable _ISR_Nest_level.
370 */
371
372#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
373
374/*
375 *  Minimum size of a thread's stack.
376 */
377
378#define CPU_STACK_MINIMUM_SIZE           M68K_CPU_STACK_MINIMUM_SIZE
379
380/*
381 *  Maximum priority of a thread. Note based from 0 which is the idle task.
382 */
383#define CPU_PRIORITY_MAXIMUM             M68K_CPU_PRIORITY_MAXIMUM
384
385#define CPU_SIZEOF_POINTER 4
386
387/*
388 *  m68k is pretty tolerant of alignment.  Just put things on 4 byte boundaries.
389 */
390
391#define CPU_ALIGNMENT                    4
392#define CPU_HEAP_ALIGNMENT               CPU_ALIGNMENT
393#define CPU_PARTITION_ALIGNMENT          CPU_ALIGNMENT
394
395/*
396 *  On m68k thread stacks require no further alignment after allocation
397 *  from the Workspace.
398 */
399
400#define CPU_STACK_ALIGNMENT        0
401
402#ifndef ASM
403
404/* macros */
405
406/*
407 *  ISR handler macros
408 *
409 *  These macros perform the following functions:
410 *     + initialize the RTEMS vector table
411 *     + disable all maskable CPU interrupts
412 *     + restore previous interrupt level (enable)
413 *     + temporarily restore interrupts (flash)
414 *     + set a particular level
415 */
416
417#define _CPU_Initialize_vectors()
418
419#define _CPU_ISR_Disable( _level ) \
420  m68k_disable_interrupts( _level )
421
422#define _CPU_ISR_Enable( _level ) \
423  m68k_enable_interrupts( _level )
424
425#define _CPU_ISR_Flash( _level ) \
426  m68k_flash_interrupts( _level )
427
428#define _CPU_ISR_Set_level( _newlevel ) \
429   m68k_set_interrupt_level( _newlevel )
430
431uint32_t   _CPU_ISR_Get_level( void );
432
433/* end of ISR handler macros */
434
435/*
436 *  Context handler macros
437 *
438 *  These macros perform the following functions:
439 *     + initialize a context area
440 *     + restart the current thread
441 *     + calculate the initial pointer into a FP context area
442 *     + initialize an FP context area
443 */
444
445#if (defined(__mcoldfire__) && ( M68K_HAS_FPU == 1 ))
446#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
447                                 _isr, _entry_point, _is_fp ) \
448   do { \
449     uint32_t   _stack; \
450     \
451     (_the_context)->sr      = 0x3000 | ((_isr) << 8); \
452     _stack                  = (uint32_t)(_stack_base) + (_size) - 4; \
453     (_the_context)->a7_msp  = (void *)_stack; \
454     *(void **)_stack        = (void *)(_entry_point); \
455     (_the_context)->fpu_dis = (_is_fp == TRUE) ? 0x00 : 0x10;          \
456   } while ( 0 )
457#else
458#define _CPU_Context_Initialize( _the_context, _stack_base, _size,      \
459                                 _isr, _entry_point, _is_fp )           \
460   do {                                                                 \
461     uint32_t   _stack;                                                 \
462                                                                        \
463     (_the_context)->sr      = 0x3000 | ((_isr) << 8);                  \
464     _stack                  = (uint32_t)(_stack_base) + (_size) - 4;   \
465     (_the_context)->a7_msp  = (void *)_stack;                          \
466     *(void **)_stack        = (void *)(_entry_point);                  \
467   } while ( 0 )
468#endif
469
470/* end of Context handler macros */
471
472/*
473 *  _CPU_Thread_Idle_body
474 *
475 *  This routine is the CPU dependent IDLE thread body.
476 *
477 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
478 *         is TRUE.
479 */
480
481void *_CPU_Thread_Idle_body( uintptr_t ignored );
482
483/*
484 *  Fatal Error manager macros
485 *
486 *  These macros perform the following functions:
487 *    + disable interrupts and halt the CPU
488 */
489
490#if ( defined(__mcoldfire__) )
491#define _CPU_Fatal_halt( _error ) \
492  { __asm__ volatile( "move.w %%sr,%%d0\n\t" \
493                  "or.l %2,%%d0\n\t" \
494                  "move.w %%d0,%%sr\n\t" \
495                  "move.l %1,%%d0\n\t" \
496                  "move.l #0xDEADBEEF,%%d1\n\t" \
497                  "halt" \
498                  : "=g" (_error) \
499                  : "0" (_error), "d"(0x0700) \
500                  : "d0", "d1" ); \
501  }
502#else
503#define _CPU_Fatal_halt( _error ) \
504  { __asm__ volatile( "movl  %0,%%d0; " \
505                  "orw   #0x0700,%%sr; " \
506                  "stop  #0x2700" : "=d" ((_error)) : "0" ((_error)) ); \
507  }
508#endif
509
510/* end of Fatal Error manager macros */
511
512/*
513 *  Bitfield handler macros
514 *
515 *  These macros perform the following functions:
516 *     + scan for the highest numbered (MSB) set in a 16 bit bitfield
517 *
518 *  NOTE:
519 *
520 *    It appears that on the M68020 bitfield are always 32 bits wide
521 *    when in a register.  This code forces the bitfield to be in
522 *    memory (it really always is anyway). This allows us to
523 *    have a real 16 bit wide bitfield which operates "correctly."
524 */
525
526#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
527#define CPU_USE_GENERIC_BITFIELD_DATA FALSE
528
529#if ( M68K_HAS_BFFFO != 1 )
530/*
531 *  Lookup table for BFFFO simulation
532 */
533extern const unsigned char _CPU_m68k_BFFFO_table[256];
534#endif
535
536#if ( M68K_HAS_BFFFO == 1 )
537
538#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
539  __asm__ volatile( "bfffo (%1),#0,#16,%0" : "=d" (_output) : "a" (&_value));
540
541#elif ( __mcfisaaplus__ )
542  /* This is simplified by the fact that RTEMS never calls it with _value=0 */
543#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
544    __asm__ volatile ( \
545       "   swap     %0\n"        \
546       "   ff1.l    %0\n"        \
547       : "=d" ((_output))        \
548       : "0" ((_value))          \
549       : "cc" ) ;
550
551#else
552/* duplicates BFFFO results for 16 bits (i.e., 15-(_priority) in
553   _CPU_Priority_bits_index is not needed), handles the 0 case, and
554   does not molest _value -- jsg */
555#if ( defined(__mcoldfire__) )
556
557#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
558  { \
559    register int dumby; \
560    \
561    __asm__ volatile ( \
562       "   clr.l   %1\n"         \
563       "   move.w  %2,%1\n"      \
564       "   lsr.l   #8,%1\n"      \
565       "   beq.s   1f\n"         \
566       "   move.b  (%3,%1),%0\n" \
567       "   bra.s   0f\n"         \
568       "1: move.w  %2,%1\n"      \
569       "   move.b  (%3,%1),%0\n" \
570       "   addq.l  #8,%0\n"      \
571       "0: and.l   #0xff,%0\n"   \
572       : "=&d" ((_output)), "=&d" ((dumby))    \
573       : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \
574       : "cc" ) ; \
575  }
576#elif ( M68K_HAS_EXTB_L == 1 )
577#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
578  { \
579    register int dumby; \
580    \
581    __asm__ volatile ( "   move.w  %2,%1\n"        \
582       "   lsr.w   #8,%1\n"        \
583       "   beq.s   1f\n"           \
584       "   move.b  (%3,%1.w),%0\n" \
585       "   extb.l  %0\n"           \
586       "   bra.s   0f\n"           \
587       "1: moveq.l #8,%0\n"        \
588       "   add.b   (%3,%2.w),%0\n" \
589       "0:\n"                      \
590       : "=&d" ((_output)), "=&d" ((dumby)) \
591       : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \
592       : "cc" ) ; \
593  }
594#else
595#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
596  { \
597    register int dumby; \
598    \
599    __asm__ volatile ( "   move.w  %2,%1\n"        \
600       "   lsr.w   #8,%1\n"        \
601       "   beq.s   1f\n"           \
602       "   move.b  (%3,%1.w),%0\n" \
603       "   and.l   #0x000000ff,%0\n"\
604       "   bra.s   0f\n"           \
605       "1: moveq.l #8,%0\n"        \
606       "   add.b   (%3,%2.w),%0\n" \
607       "0:\n"                      \
608       : "=&d" ((_output)), "=&d" ((dumby)) \
609       : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \
610       : "cc" ) ; \
611  }
612#endif
613
614#endif
615
616/* end of Bitfield handler macros */
617
618/*
619 *  Priority handler macros
620 *
621 *  These macros perform the following functions:
622 *    + return a mask with the bit for this major/minor portion of
623 *      of thread priority set.
624 *    + translate the bit number returned by "Bitfield_find_first_bit"
625 *      into an index into the thread ready chain bit maps
626 */
627
628#define _CPU_Priority_Mask( _bit_number ) \
629  ( 0x8000 >> (_bit_number) )
630
631#define _CPU_Priority_bits_index( _priority ) \
632  (_priority)
633
634/* end of Priority handler macros */
635
636/* functions */
637
638/*
639 *  _CPU_Initialize
640 *
641 *  This routine performs CPU dependent initialization.
642 */
643
644void _CPU_Initialize(void);
645
646/*
647 *  _CPU_ISR_install_raw_handler
648 *
649 *  This routine installs a "raw" interrupt handler directly into the
650 *  processor's vector table.
651 */
652
653void _CPU_ISR_install_raw_handler(
654  uint32_t    vector,
655  proc_ptr    new_handler,
656  proc_ptr   *old_handler
657);
658
659/*
660 *  _CPU_ISR_install_vector
661 *
662 *  This routine installs an interrupt vector.
663 */
664
665void _CPU_ISR_install_vector(
666  uint32_t         vector,
667  proc_ptr         new_handler,
668  proc_ptr        *old_handler
669);
670
671/*
672 *  _CPU_Install_interrupt_stack
673 *
674 *  This routine installs the hardware interrupt stack pointer.
675 */
676
677void _CPU_Install_interrupt_stack( void );
678
679/*
680 *  _CPU_Context_switch
681 *
682 *  This routine switches from the run context to the heir context.
683 */
684
685void _CPU_Context_switch(
686  Context_Control  *run,
687  Context_Control  *heir
688);
689
690void _CPU_Context_Restart_self(
691  Context_Control  *the_context
692);
693
694/*
695 *  _CPU_Context_save_fp
696 *
697 *  This routine saves the floating point context passed to it.
698 */
699
700void _CPU_Context_save_fp(
701  Context_Control_fp **fp_context_ptr
702);
703
704/*
705 *  _CPU_Context_restore_fp
706 *
707 *  This routine restores the floating point context passed to it.
708 */
709
710void _CPU_Context_restore_fp(
711  Context_Control_fp **fp_context_ptr
712);
713
714void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
715
716#if (M68K_HAS_FPSP_PACKAGE == 1)
717/*
718 *  Hooks for the Floating Point Support Package (FPSP) provided by Motorola
719 *
720 *  NOTES:
721 *
722 *  Motorola 68k family CPU's before the 68040 used a coprocessor
723 *  (68881 or 68882) to handle floating point.  The 68040 has internal
724 *  floating point support -- but *not* the complete support provided by
725 *  the 68881 or 68882.  The leftover functions are taken care of by the
726 *  M68040 Floating Point Support Package.  Quoting from the MC68040
727 *  Microprocessors User's Manual, Section 9, Floating-Point Unit (MC68040):
728 *
729 *    "When used with the M68040FPSP, the MC68040 FPU is fully
730 *    compliant with IEEE floating-point standards."
731 *
732 *  M68KFPSPInstallExceptionHandlers is in libcpu/m68k/MODEL/fpsp and
733 *  is invoked early in the application code to ensure that proper FP
734 *  behavior is installed.  This is not left to the BSP to call, since
735 *  this would force all applications using that BSP to use FPSP which
736 *  is not necessarily desirable.
737 *
738 *  There is a similar package for the 68060 but RTEMS does not yet
739 *  support the 68060.
740 */
741
742void M68KFPSPInstallExceptionHandlers (void);
743
744SCORE_EXTERN int (*_FPSP_install_raw_handler)(
745  uint32_t   vector,
746  proc_ptr new_handler,
747  proc_ptr *old_handler
748);
749
750#endif
751
752
753#endif
754
755#ifdef __cplusplus
756}
757#endif
758
759#endif
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