source: rtems/cpukit/score/cpu/m68k/rtems/score/cpu.h @ 4aa23c96

5
Last change on this file since 4aa23c96 was 4aa23c96, checked in by Sebastian Huber <sebastian.huber@…>, on Jan 23, 2017 at 7:12:18 AM

Remove CPU_BIG_ENDIAN and CPU_LITTLE_ENDIAN

Use de-facto standard BYTE_ORDER instead.

Close #2803.

  • Property mode set to 100644
File size: 19.1 KB
Line 
1/**
2 * @file
3 *
4 * @brief Motorola M68K CPU Dependent Source
5 *
6 * This include file contains information pertaining to the Motorola
7 * m68xxx processor family.
8 */
9
10/*
11 *  COPYRIGHT (c) 1989-2011.
12 *  On-Line Applications Research Corporation (OAR).
13 *
14 *  The license and distribution terms for this file may be
15 *  found in the file LICENSE in this distribution or at
16 *  http://www.rtems.org/license/LICENSE.
17 */
18
19#ifndef _RTEMS_SCORE_CPU_H
20#define _RTEMS_SCORE_CPU_H
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26#include <rtems/score/types.h>
27#include <rtems/score/m68k.h>
28
29/* conditional compilation parameters */
30
31/*
32 *  Does the CPU follow the simple vectored interrupt model?
33 *
34 *  If TRUE, then RTEMS allocates the vector table it internally manages.
35 *  If FALSE, then the BSP is assumed to allocate and manage the vector
36 *  table
37 *
38 *  M68K Specific Information:
39 *
40 *  XXX document implementation including references if appropriate
41 */
42#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
43
44/*
45 *  Use the m68k's hardware interrupt stack support and have the
46 *  interrupt manager allocate the memory for it.
47 */
48
49#if ( M68K_HAS_SEPARATE_STACKS == 1)
50#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 0
51#define CPU_HAS_HARDWARE_INTERRUPT_STACK 1
52#else
53#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 1
54#define CPU_HAS_HARDWARE_INTERRUPT_STACK 0
55#endif
56#define CPU_ALLOCATE_INTERRUPT_STACK     1
57
58/*
59 *  Does the RTEMS invoke the user's ISR with the vector number and
60 *  a pointer to the saved interrupt frame (1) or just the vector
61 *  number (0)?
62 */
63
64#define CPU_ISR_PASSES_FRAME_POINTER FALSE
65
66/*
67 *  Some family members have no FP, some have an FPU such as the
68 *  MC68881/MC68882 for the MC68020, others have it built in (MC68030, 040).
69 *
70 *  NOTE:  If on a CPU without hardware FP, then one can use software
71 *         emulation.  The gcc software FP emulation code has data which
72 *         must be contexted switched on a per task basis.
73 */
74
75#if ( M68K_HAS_FPU == 1 ) || ( M68K_HAS_EMAC == 1 )
76  #define CPU_HARDWARE_FP TRUE
77  #define CPU_SOFTWARE_FP FALSE
78#else
79  #define CPU_HARDWARE_FP FALSE
80  #if defined( __GNUC__ )
81    #define CPU_SOFTWARE_FP TRUE
82  #else
83    #define CPU_SOFTWARE_FP FALSE
84  #endif
85#endif
86
87/*
88 *  All tasks are not by default floating point tasks on this CPU.
89 *  The IDLE task does not have a floating point context on this CPU.
90 *  It is safe to use the deferred floating point context switch
91 *  algorithm on this CPU.
92 */
93
94#define CPU_ALL_TASKS_ARE_FP             FALSE
95#define CPU_IDLE_TASK_IS_FP              FALSE
96#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
97#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
98
99#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
100#define CPU_STACK_GROWS_UP               FALSE
101
102/* FIXME: Is this the right value? */
103#define CPU_CACHE_LINE_BYTES 16
104
105#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
106
107#define CPU_MAXIMUM_PROCESSORS 32
108
109#if ( CPU_HARDWARE_FP == TRUE ) && !defined( __mcoldfire__ )
110  #if defined( __mc68060__ )
111    #define M68K_FP_STATE_SIZE 16
112  #else
113    #define M68K_FP_STATE_SIZE 216
114  #endif
115#endif
116
117#ifndef ASM
118
119/* structures */
120
121/*
122 *  Basic integer context for the m68k family.
123 */
124
125typedef struct {
126  uint32_t    sr;                /* (sr) status register */
127  uint32_t    d2;                /* (d2) data register 2 */
128  uint32_t    d3;                /* (d3) data register 3 */
129  uint32_t    d4;                /* (d4) data register 4 */
130  uint32_t    d5;                /* (d5) data register 5 */
131  uint32_t    d6;                /* (d6) data register 6 */
132  uint32_t    d7;                /* (d7) data register 7 */
133  void       *a2;                /* (a2) address register 2 */
134  void       *a3;                /* (a3) address register 3 */
135  void       *a4;                /* (a4) address register 4 */
136  void       *a5;                /* (a5) address register 5 */
137  void       *a6;                /* (a6) address register 6 */
138  void       *a7_msp;            /* (a7) master stack pointer */
139  #if defined( __mcoldfire__ ) && ( M68K_HAS_FPU == 1 )
140    uint8_t   fpu_dis;
141  #endif
142} Context_Control;
143
144#define _CPU_Context_Get_SP( _context ) \
145  (_context)->a7_msp
146
147/*
148 *  Floating point context areas and support routines
149 */
150
151#if ( CPU_SOFTWARE_FP == TRUE )
152  /*
153   *  This is the same as gcc's view of the software FP condition code
154   *  register _fpCCR.  The implementation of the emulation code is
155   *  in the gcc-VERSION/config/m68k directory.  This structure is
156   *  correct as of gcc 2.7.2.2.
157   */
158  typedef struct {
159    uint16_t _exception_bits;
160    uint16_t _trap_enable_bits;
161    uint16_t _sticky_bits;
162    uint16_t _rounding_mode;
163    uint16_t _format;
164    uint16_t _last_operation;
165    union {
166      float sf;
167      double df;
168    } _operand1;
169    union {
170      float sf;
171      double df;
172    } _operand2;
173  } Context_Control_fp;
174
175  /*
176   *  This software FP implementation is only for GCC.
177   */
178  #define _CPU_Context_Fp_start( _base, _offset ) \
179     ((void *) _Addresses_Add_offset( (_base), (_offset) ) )
180
181  #define _CPU_Context_Initialize_fp( _fp_area ) \
182     { \
183       Context_Control_fp *_fp; \
184       _fp = *(Context_Control_fp **)_fp_area; \
185       _fp->_exception_bits = 0; \
186       _fp->_trap_enable_bits = 0; \
187       _fp->_sticky_bits = 0; \
188       _fp->_rounding_mode = 0;  /* ROUND_TO_NEAREST */ \
189       _fp->_format = 0;         /* NIL */ \
190       _fp->_last_operation = 0; /* NOOP */ \
191       _fp->_operand1.df = 0; \
192       _fp->_operand2.df = 0; \
193     }
194#endif
195
196#if ( CPU_HARDWARE_FP == TRUE )
197  #if defined( __mcoldfire__ )
198    /* We need memset() to initialize the FP context */
199    #include <string.h>
200
201    #if ( M68K_HAS_FPU == 1 )
202      /*
203       * The Cache Control Register (CACR) has write-only access.  It is also
204       * used to enable and disable the FPU.  We need to maintain a copy of
205       * this register to allow per thread values.
206       */
207      extern uint32_t _CPU_cacr_shadow;
208    #endif
209
210    /* We assume that each ColdFire core with a FPU has also an EMAC unit */
211    typedef struct {
212      uint32_t emac_macsr;
213      uint32_t emac_acc0;
214      uint32_t emac_acc1;
215      uint32_t emac_acc2;
216      uint32_t emac_acc3;
217      uint32_t emac_accext01;
218      uint32_t emac_accext23;
219      uint32_t emac_mask;
220      #if ( M68K_HAS_FPU == 1 )
221        uint16_t fp_state_format;
222        uint16_t fp_state_fpcr;
223        double fp_state_op;
224        uint32_t fp_state_fpsr;
225
226        /*
227         * We need to save the FP Instruction Address Register (FPIAR), because
228         * a context switch can occur within a FP exception before the handler
229         * was able to save this register.
230         */
231        uint32_t fp_fpiar;
232
233        double fp_data [8];
234      #endif
235    } Context_Control_fp;
236
237    #define _CPU_Context_Fp_start( _base, _offset ) \
238      ((void *) _Addresses_Add_offset( (_base), (_offset) ))
239
240    /*
241     * The reset value for all context relevant registers except the FP data
242     * registers is zero.  The reset value of the FP data register is NAN.  The
243     * restore of the reset FP state will reset the FP data registers, so the
244     * initial value of them can be arbitrary here.
245     */
246    #define _CPU_Context_Initialize_fp( _fp_area ) \
247      memset( *(_fp_area), 0, sizeof( Context_Control_fp ) )
248  #else
249    /*
250     *  FP context save area for the M68881/M68882 and 68060 numeric
251     *  coprocessors.
252     */
253    typedef struct {
254      /*
255       * M68K_FP_STATE_SIZE bytes for FSAVE/FRESTORE
256       * 96 bytes for FMOVEM FP0-7
257       * 12 bytes for FMOVEM CREGS
258       * 4 bytes for non-null flag
259       */
260      uint8_t fp_save_area [M68K_FP_STATE_SIZE + 112];
261    } Context_Control_fp;
262
263    #define _CPU_Context_Fp_start( _base, _offset ) \
264       ( \
265         (void *) _Addresses_Add_offset( \
266            (_base), \
267            (_offset) + CPU_CONTEXT_FP_SIZE - 4 \
268         ) \
269       )
270
271    #define _CPU_Context_Initialize_fp( _fp_area ) \
272       { \
273         uint32_t   *_fp_context = (uint32_t *)*(_fp_area); \
274         *(--(_fp_context)) = 0; \
275         *(_fp_area) = (void *)(_fp_context); \
276       }
277  #endif
278#endif
279
280/*
281 *  The following structures define the set of information saved
282 *  on the current stack by RTEMS upon receipt of each exc/interrupt.
283 *  These are not used by m68k handlers.
284 *  The exception frame is for rdbg.
285 */
286
287typedef struct {
288  uint32_t   vecnum; /* vector number */
289} CPU_Interrupt_frame;
290
291typedef struct {
292  uint32_t   vecnum; /* vector number */
293  uint32_t   sr; /* status register */
294  uint32_t   pc; /* program counter */
295  uint32_t   d0, d1, d2, d3, d4, d5, d6, d7;
296  uint32_t   a0, a1, a2, a3, a4, a5, a6, a7;
297} CPU_Exception_frame;
298
299/* variables */
300
301extern void*                     _VBR;
302
303#endif /* ASM */
304
305/* constants */
306
307/*
308 *  This defines the number of levels and the mask used to pick those
309 *  bits out of a thread mode.
310 */
311
312#define CPU_MODES_INTERRUPT_LEVEL  0x00000007 /* interrupt level in mode */
313#define CPU_MODES_INTERRUPT_MASK   0x00000007 /* interrupt level in mode */
314
315/*
316 *  context size area for floating point
317 */
318
319#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
320
321/*
322 *  extra stack required by the MPCI receive server thread
323 */
324
325#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
326
327/*
328 *  m68k family supports 256 distinct vectors.
329 */
330
331#define CPU_INTERRUPT_NUMBER_OF_VECTORS      256
332#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
333
334/*
335 *  This is defined if the port has a special way to report the ISR nesting
336 *  level.  Most ports maintain the variable _ISR_Nest_level.
337 */
338
339#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
340
341/*
342 *  Minimum size of a thread's stack.
343 */
344
345#define CPU_STACK_MINIMUM_SIZE           M68K_CPU_STACK_MINIMUM_SIZE
346
347/*
348 *  Maximum priority of a thread. Note based from 0 which is the idle task.
349 */
350#define CPU_PRIORITY_MAXIMUM             M68K_CPU_PRIORITY_MAXIMUM
351
352#define CPU_SIZEOF_POINTER 4
353
354/*
355 *  m68k is pretty tolerant of alignment.  Just put things on 4 byte boundaries.
356 */
357
358#define CPU_ALIGNMENT                    4
359#define CPU_HEAP_ALIGNMENT               CPU_ALIGNMENT
360#define CPU_PARTITION_ALIGNMENT          CPU_ALIGNMENT
361
362/*
363 *  On m68k thread stacks require no further alignment after allocation
364 *  from the Workspace.
365 */
366
367#define CPU_STACK_ALIGNMENT        0
368
369#ifndef ASM
370
371/* macros */
372
373/*
374 *  ISR handler macros
375 *
376 *  These macros perform the following functions:
377 *     + initialize the RTEMS vector table
378 *     + disable all maskable CPU interrupts
379 *     + restore previous interrupt level (enable)
380 *     + temporarily restore interrupts (flash)
381 *     + set a particular level
382 */
383
384#define _CPU_Initialize_vectors()
385
386#define _CPU_ISR_Disable( _level ) \
387  m68k_disable_interrupts( _level )
388
389#define _CPU_ISR_Enable( _level ) \
390  m68k_enable_interrupts( _level )
391
392#define _CPU_ISR_Flash( _level ) \
393  m68k_flash_interrupts( _level )
394
395RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
396{
397  return ( level & 0x0700 ) == 0;
398}
399
400#define _CPU_ISR_Set_level( _newlevel ) \
401   m68k_set_interrupt_level( _newlevel )
402
403uint32_t   _CPU_ISR_Get_level( void );
404
405/* end of ISR handler macros */
406
407/*
408 *  Context handler macros
409 *
410 *  These macros perform the following functions:
411 *     + initialize a context area
412 *     + restart the current thread
413 *     + calculate the initial pointer into a FP context area
414 *     + initialize an FP context area
415 */
416
417void _CPU_Context_Initialize(
418  Context_Control *the_context,
419  void *stack_area_begin,
420  size_t stack_area_size,
421  uint32_t new_level,
422  void (*entry_point)( void ),
423  bool is_fp,
424  void *tls_area
425);
426
427/* end of Context handler macros */
428
429/*
430 *  _CPU_Thread_Idle_body
431 *
432 *  This routine is the CPU dependent IDLE thread body.
433 *
434 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
435 *         is TRUE.
436 */
437
438void *_CPU_Thread_Idle_body( uintptr_t ignored );
439
440/*
441 *  Fatal Error manager macros
442 *
443 *  These macros perform the following functions:
444 *    + disable interrupts and halt the CPU
445 */
446
447#if ( defined(__mcoldfire__) )
448#define _CPU_Fatal_halt( _source, _error ) \
449  { __asm__ volatile( "move.w %%sr,%%d0\n\t" \
450                  "or.l %2,%%d0\n\t" \
451                  "move.w %%d0,%%sr\n\t" \
452                  "move.l %1,%%d0\n\t" \
453                  "move.l #0xDEADBEEF,%%d1\n\t" \
454                  "halt" \
455                  : "=g" (_error) \
456                  : "0" (_error), "d"(0x0700) \
457                  : "d0", "d1" ); \
458  }
459#else
460#define _CPU_Fatal_halt( _source, _error ) \
461  { __asm__ volatile( "movl  %0,%%d0; " \
462                  "orw   #0x0700,%%sr; " \
463                  "stop  #0x2700" : "=d" ((_error)) : "0" ((_error)) ); \
464  }
465#endif
466
467/* end of Fatal Error manager macros */
468
469/*
470 *  Bitfield handler macros
471 *
472 *  These macros perform the following functions:
473 *     + scan for the highest numbered (MSB) set in a 16 bit bitfield
474 *
475 *  NOTE:
476 *
477 *    It appears that on the M68020 bitfield are always 32 bits wide
478 *    when in a register.  This code forces the bitfield to be in
479 *    memory (it really always is anyway). This allows us to
480 *    have a real 16 bit wide bitfield which operates "correctly."
481 */
482
483#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
484
485#if ( M68K_HAS_BFFFO != 1 )
486/*
487 *  Lookup table for BFFFO simulation
488 */
489extern const unsigned char _CPU_m68k_BFFFO_table[256];
490#endif
491
492#if ( M68K_HAS_BFFFO == 1 )
493
494#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
495  __asm__ volatile( "bfffo (%1),#0,#16,%0" : "=d" (_output) : "a" (&_value));
496
497#elif ( __mcfisaaplus__ )
498  /* This is simplified by the fact that RTEMS never calls it with _value=0 */
499#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
500    __asm__ volatile ( \
501       "   swap     %0\n"        \
502       "   ff1.l    %0\n"        \
503       : "=d" ((_output))        \
504       : "0" ((_value))          \
505       : "cc" ) ;
506
507#else
508/* duplicates BFFFO results for 16 bits (i.e., 15-(_priority) in
509   _CPU_Priority_bits_index is not needed), handles the 0 case, and
510   does not molest _value -- jsg */
511#if ( defined(__mcoldfire__) )
512
513#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
514  { \
515    register int dumby; \
516    \
517    __asm__ volatile ( \
518       "   clr.l   %1\n"         \
519       "   move.w  %2,%1\n"      \
520       "   lsr.l   #8,%1\n"      \
521       "   beq.s   1f\n"         \
522       "   move.b  (%3,%1),%0\n" \
523       "   bra.s   0f\n"         \
524       "1: move.w  %2,%1\n"      \
525       "   move.b  (%3,%1),%0\n" \
526       "   addq.l  #8,%0\n"      \
527       "0: and.l   #0xff,%0\n"   \
528       : "=&d" ((_output)), "=&d" ((dumby))    \
529       : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \
530       : "cc" ) ; \
531  }
532#elif ( M68K_HAS_EXTB_L == 1 )
533#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
534  { \
535    register int dumby; \
536    \
537    __asm__ volatile ( "   move.w  %2,%1\n"        \
538       "   lsr.w   #8,%1\n"        \
539       "   beq.s   1f\n"           \
540       "   move.b  (%3,%1.w),%0\n" \
541       "   extb.l  %0\n"           \
542       "   bra.s   0f\n"           \
543       "1: moveq.l #8,%0\n"        \
544       "   add.b   (%3,%2.w),%0\n" \
545       "0:\n"                      \
546       : "=&d" ((_output)), "=&d" ((dumby)) \
547       : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \
548       : "cc" ) ; \
549  }
550#else
551#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
552  { \
553    register int dumby; \
554    \
555    __asm__ volatile ( "   move.w  %2,%1\n"        \
556       "   lsr.w   #8,%1\n"        \
557       "   beq.s   1f\n"           \
558       "   move.b  (%3,%1.w),%0\n" \
559       "   and.l   #0x000000ff,%0\n"\
560       "   bra.s   0f\n"           \
561       "1: moveq.l #8,%0\n"        \
562       "   add.b   (%3,%2.w),%0\n" \
563       "0:\n"                      \
564       : "=&d" ((_output)), "=&d" ((dumby)) \
565       : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \
566       : "cc" ) ; \
567  }
568#endif
569
570#endif
571
572/* end of Bitfield handler macros */
573
574/*
575 *  Priority handler macros
576 *
577 *  These macros perform the following functions:
578 *    + return a mask with the bit for this major/minor portion of
579 *      of thread priority set.
580 *    + translate the bit number returned by "Bitfield_find_first_bit"
581 *      into an index into the thread ready chain bit maps
582 */
583
584#define _CPU_Priority_Mask( _bit_number ) \
585  ( 0x8000 >> (_bit_number) )
586
587#define _CPU_Priority_bits_index( _priority ) \
588  (_priority)
589
590/* end of Priority handler macros */
591
592/* functions */
593
594/*
595 *  _CPU_Initialize
596 *
597 *  This routine performs CPU dependent initialization.
598 */
599
600void _CPU_Initialize(void);
601
602/*
603 *  _CPU_ISR_install_raw_handler
604 *
605 *  This routine installs a "raw" interrupt handler directly into the
606 *  processor's vector table.
607 */
608
609void _CPU_ISR_install_raw_handler(
610  uint32_t    vector,
611  proc_ptr    new_handler,
612  proc_ptr   *old_handler
613);
614
615/*
616 *  _CPU_ISR_install_vector
617 *
618 *  This routine installs an interrupt vector.
619 */
620
621void _CPU_ISR_install_vector(
622  uint32_t         vector,
623  proc_ptr         new_handler,
624  proc_ptr        *old_handler
625);
626
627/*
628 *  _CPU_Install_interrupt_stack
629 *
630 *  This routine installs the hardware interrupt stack pointer.
631 */
632
633void _CPU_Install_interrupt_stack( void );
634
635/*
636 *  _CPU_Context_switch
637 *
638 *  This routine switches from the run context to the heir context.
639 */
640
641void _CPU_Context_switch(
642  Context_Control  *run,
643  Context_Control  *heir
644);
645
646void _CPU_Context_Restart_self(
647  Context_Control  *the_context
648) RTEMS_NO_RETURN;
649
650/*
651 *  _CPU_Context_save_fp
652 *
653 *  This routine saves the floating point context passed to it.
654 */
655
656void _CPU_Context_save_fp(
657  Context_Control_fp **fp_context_ptr
658);
659
660/*
661 *  _CPU_Context_restore_fp
662 *
663 *  This routine restores the floating point context passed to it.
664 */
665
666void _CPU_Context_restore_fp(
667  Context_Control_fp **fp_context_ptr
668);
669
670static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
671{
672  /* TODO */
673}
674
675static inline void _CPU_Context_validate( uintptr_t pattern )
676{
677  while (1) {
678    /* TODO */
679  }
680}
681
682/**
683 *  This method prints the CPU exception frame.
684 *
685 *  @param[in] frame points to the frame to be printed
686 */
687void _CPU_Exception_frame_print(
688  const CPU_Exception_frame *frame
689);
690
691typedef uint32_t CPU_Counter_ticks;
692
693CPU_Counter_ticks _CPU_Counter_read( void );
694
695static inline CPU_Counter_ticks _CPU_Counter_difference(
696  CPU_Counter_ticks second,
697  CPU_Counter_ticks first
698)
699{
700  return second - first;
701}
702
703#if (M68K_HAS_FPSP_PACKAGE == 1)
704/*
705 *  Hooks for the Floating Point Support Package (FPSP) provided by Motorola
706 *
707 *  NOTES:
708 *
709 *  Motorola 68k family CPU's before the 68040 used a coprocessor
710 *  (68881 or 68882) to handle floating point.  The 68040 has internal
711 *  floating point support -- but *not* the complete support provided by
712 *  the 68881 or 68882.  The leftover functions are taken care of by the
713 *  M68040 Floating Point Support Package.  Quoting from the MC68040
714 *  Microprocessors User's Manual, Section 9, Floating-Point Unit (MC68040):
715 *
716 *    "When used with the M68040FPSP, the MC68040 FPU is fully
717 *    compliant with IEEE floating-point standards."
718 *
719 *  M68KFPSPInstallExceptionHandlers is in libcpu/m68k/MODEL/fpsp and
720 *  is invoked early in the application code to ensure that proper FP
721 *  behavior is installed.  This is not left to the BSP to call, since
722 *  this would force all applications using that BSP to use FPSP which
723 *  is not necessarily desirable.
724 *
725 *  There is a similar package for the 68060 but RTEMS does not yet
726 *  support the 68060.
727 */
728
729void M68KFPSPInstallExceptionHandlers (void);
730
731extern int (*_FPSP_install_raw_handler)(
732  uint32_t   vector,
733  proc_ptr new_handler,
734  proc_ptr *old_handler
735);
736
737#endif
738
739
740#endif
741
742#ifdef __cplusplus
743}
744#endif
745
746#endif
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