source: rtems/cpukit/score/cpu/m68k/rtems/score/cpu.h @ 3b7e9bc

4.104.115
Last change on this file since 3b7e9bc was 3b7e9bc, checked in by Thomas Doerfler <Thomas.Doerfler@…>, on 05/15/09 at 07:20:38

cpu.c, cpu_asm.S, rtems/score/cpu.h: Cleanup of the floating point context initialization, save and restore code.

  • Property mode set to 100644
File size: 20.7 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  This include file contains information pertaining to the Motorola
7 *  m68xxx processor family.
8 *
9 *  COPYRIGHT (c) 1989-2006.
10 *  On-Line Applications Research Corporation (OAR).
11 *
12 *  The license and distribution terms for this file may be
13 *  found in the file LICENSE in this distribution or at
14 *  http://www.rtems.com/license/LICENSE.
15 *
16 *  $Id$
17 */
18
19#ifndef _RTEMS_SCORE_CPU_H
20#define _RTEMS_SCORE_CPU_H
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26#include <rtems/score/m68k.h>              /* pick up machine definitions */
27#ifndef ASM
28  #include <rtems/score/types.h>
29#else
30  /* FIXME */
31  #define TRUE 1
32  #define FALSE 0
33#endif
34
35/* conditional compilation parameters */
36
37#define CPU_INLINE_ENABLE_DISPATCH       TRUE
38#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
39
40/*
41 *  Does the CPU follow the simple vectored interrupt model?
42 *
43 *  If TRUE, then RTEMS allocates the vector table it internally manages.
44 *  If FALSE, then the BSP is assumed to allocate and manage the vector
45 *  table
46 *
47 *  M68K Specific Information:
48 *
49 *  XXX document implementation including references if appropriate
50 */
51#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
52
53/*
54 *  Use the m68k's hardware interrupt stack support and have the
55 *  interrupt manager allocate the memory for it.
56 */
57
58#if ( M68K_HAS_SEPARATE_STACKS == 1)
59#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 0
60#define CPU_HAS_HARDWARE_INTERRUPT_STACK 1
61#else
62#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 1
63#define CPU_HAS_HARDWARE_INTERRUPT_STACK 0
64#endif
65#define CPU_ALLOCATE_INTERRUPT_STACK     1
66
67/*
68 *  Does the RTEMS invoke the user's ISR with the vector number and
69 *  a pointer to the saved interrupt frame (1) or just the vector
70 *  number (0)?
71 */
72
73#define CPU_ISR_PASSES_FRAME_POINTER 0
74
75/*
76 *  Some family members have no FP, some have an FPU such as the
77 *  MC68881/MC68882 for the MC68020, others have it built in (MC68030, 040).
78 *
79 *  NOTE:  If on a CPU without hardware FP, then one can use software
80 *         emulation.  The gcc software FP emulation code has data which
81 *         must be contexted switched on a per task basis.
82 */
83
84#if ( M68K_HAS_FPU == 1 ) || ( M68K_HAS_EMAC == 1 )
85  #define CPU_HARDWARE_FP TRUE
86  #define CPU_SOFTWARE_FP FALSE
87#else
88  #define CPU_HARDWARE_FP FALSE
89  #if defined( __GNUC__ )
90    #define CPU_SOFTWARE_FP TRUE
91  #else
92    #define CPU_SOFTWARE_FP FALSE
93  #endif
94#endif
95
96/*
97 *  All tasks are not by default floating point tasks on this CPU.
98 *  The IDLE task does not have a floating point context on this CPU.
99 *  It is safe to use the deferred floating point context switch
100 *  algorithm on this CPU.
101 */
102
103#define CPU_ALL_TASKS_ARE_FP             FALSE
104#define CPU_IDLE_TASK_IS_FP              FALSE
105#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
106
107#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
108#define CPU_STACK_GROWS_UP               FALSE
109#define CPU_STRUCTURE_ALIGNMENT
110
111/*
112 *  Define what is required to specify how the network to host conversion
113 *  routines are handled.
114 */
115
116#define CPU_BIG_ENDIAN                           TRUE
117#define CPU_LITTLE_ENDIAN                        FALSE
118
119#ifndef ASM
120
121/* structures */
122
123/*
124 *  Basic integer context for the m68k family.
125 */
126
127typedef struct {
128  uint32_t    sr;                /* (sr) status register */
129  uint32_t    d2;                /* (d2) data register 2 */
130  uint32_t    d3;                /* (d3) data register 3 */
131  uint32_t    d4;                /* (d4) data register 4 */
132  uint32_t    d5;                /* (d5) data register 5 */
133  uint32_t    d6;                /* (d6) data register 6 */
134  uint32_t    d7;                /* (d7) data register 7 */
135  void       *a2;                /* (a2) address register 2 */
136  void       *a3;                /* (a3) address register 3 */
137  void       *a4;                /* (a4) address register 4 */
138  void       *a5;                /* (a5) address register 5 */
139  void       *a6;                /* (a6) address register 6 */
140  void       *a7_msp;            /* (a7) master stack pointer */
141  #if defined( __mcoldfire__ ) && ( M68K_HAS_FPU == 1 )
142    uint8_t   fpu_dis;
143  #endif
144} Context_Control;
145
146#define _CPU_Context_Get_SP( _context ) \
147  (_context)->a7_msp
148
149/*
150 *  Floating point context areas and support routines
151 */
152
153#if ( CPU_SOFTWARE_FP == TRUE )
154  /*
155   *  This is the same as gcc's view of the software FP condition code
156   *  register _fpCCR.  The implementation of the emulation code is
157   *  in the gcc-VERSION/config/m68k directory.  This structure is
158   *  correct as of gcc 2.7.2.2.
159   */
160  typedef struct {
161    uint16_t _exception_bits;
162    uint16_t _trap_enable_bits;
163    uint16_t _sticky_bits;
164    uint16_t _rounding_mode;
165    uint16_t _format;
166    uint16_t _last_operation;
167    union {
168      float sf;
169      double df;
170    } _operand1;
171    union {
172      float sf;
173      double df;
174    } _operand2;
175  } Context_Control_fp;
176
177  /*
178   *  This software FP implementation is only for GCC.
179   */
180  #define _CPU_Context_Fp_start( _base, _offset ) \
181     ((void *) _Addresses_Add_offset( (_base), (_offset) ) )
182
183  #define _CPU_Context_Initialize_fp( _fp_area ) \
184     { \
185       Context_Control_fp *_fp; \
186       _fp = *(Context_Control_fp **)_fp_area; \
187       _fp->_exception_bits = 0; \
188       _fp->_trap_enable_bits = 0; \
189       _fp->_sticky_bits = 0; \
190       _fp->_rounding_mode = 0;  /* ROUND_TO_NEAREST */ \
191       _fp->_format = 0;         /* NIL */ \
192       _fp->_last_operation = 0; /* NOOP */ \
193       _fp->_operand1.df = 0; \
194       _fp->_operand2.df = 0; \
195     }
196#endif
197
198#if ( CPU_HARDWARE_FP == TRUE )
199  #if defined( __mcoldfire__ )
200    /* We need memset() to initialize the FP context */
201    #include <string.h>
202
203    #if ( M68K_HAS_FPU == 1 )
204      /*
205       * The Cache Control Register (CACR) has write-only access.  It is also
206       * used to enable and disable the FPU.  We need to maintain a copy of
207       * this register to allow per thread values.
208       */
209      extern uint32_t _CPU_cacr_shadow;
210    #endif
211
212    /* We assume that each ColdFire core with a FPU has also an EMAC unit */
213    typedef struct {
214      uint32_t emac_macsr;
215      uint32_t emac_acc0;
216      uint32_t emac_acc1;
217      uint32_t emac_acc2;
218      uint32_t emac_acc3;
219      uint32_t emac_accext01;
220      uint32_t emac_accext23;
221      uint32_t emac_mask;
222      #if ( M68K_HAS_FPU == 1 )
223        uint16_t fp_state_format;
224        uint16_t fp_state_fpcr;
225        double fp_state_op;
226        uint32_t fp_state_fpsr;
227
228        /*
229         * We need to save the FP Instruction Address Register (FPIAR), because
230         * a context switch can occur within a FP exception before the handler
231         * was able to save this register.
232         */
233        uint32_t fp_fpiar;
234
235        double fp_data [8];
236      #endif
237    } Context_Control_fp;
238
239    #define _CPU_Context_Fp_start( _base, _offset ) \
240      ((void *) _Addresses_Add_offset( (_base), (_offset) ))
241
242    /*
243     * The reset value for all context relevant registers except the FP data
244     * registers is zero.  The reset value of the FP data register is NAN.  The
245     * restore of the reset FP state will reset the FP data registers, so the
246     * initial value of them can be arbitrary here.
247     */
248    #define _CPU_Context_Initialize_fp( _fp_area ) \
249      memset( *(_fp_area), 0, sizeof( Context_Control_fp ) )
250  #else
251    /*
252     *  FP context save area for the M68881/M68882 and 68060 numeric coprocessors.
253     */
254
255    #if defined( __mc68060__ )
256      #define M68K_FP_STATE_SIZE 16
257    #else
258      #define M68K_FP_STATE_SIZE 216
259    #endif
260
261    typedef struct {
262      /*
263       * M68K_FP_STATE_SIZE bytes for FSAVE/FRESTORE
264       * 96 bytes for FMOVEM FP0-7
265       * 12 bytes for FMOVEM CREGS
266       * 4 bytes for non-null flag
267       */
268      uint8_t fp_save_area [M68K_FP_STATE_SIZE + 112];
269    } Context_Control_fp;
270
271    #define _CPU_Context_Fp_start( _base, _offset ) \
272       ( \
273         (void *) _Addresses_Add_offset( \
274            (_base), \
275            (_offset) + CPU_CONTEXT_FP_SIZE - 4 \
276         ) \
277       )
278
279    #define _CPU_Context_Initialize_fp( _fp_area ) \
280       { \
281         uint32_t   *_fp_context = (uint32_t *)*(_fp_area); \
282         *(--(_fp_context)) = 0; \
283         *(_fp_area) = (void *)(_fp_context); \
284       }
285    #endif
286#endif
287
288/*
289 *  The following structures define the set of information saved
290 *  on the current stack by RTEMS upon receipt of each exc/interrupt.
291 *  These are not used by m68k handlers.
292 *  The exception frame is for rdbg.
293 */
294
295typedef struct {
296  uint32_t   vecnum; /* vector number */
297} CPU_Interrupt_frame;
298
299typedef struct {
300  uint32_t   vecnum; /* vector number */
301  uint32_t   sr; /* status register */
302  uint32_t   pc; /* program counter */
303  uint32_t   d0, d1, d2, d3, d4, d5, d6, d7;
304  uint32_t   a0, a1, a2, a3, a4, a5, a6, a7;
305} CPU_Exception_frame;
306
307/* variables */
308
309SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
310SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
311
312extern void*                     _VBR;
313
314#if ( M68K_HAS_VBR == 0 )
315
316/*
317 * Table of ISR handler entries that resides in RAM. The FORMAT/ID is
318 * pushed onto the stack. This is not is the same order as VBR processors.
319 * The ISR handler takes the format and uses it for dispatching the user
320 * handler.
321 *
322 * FIXME : should be moved to below CPU_INTERRUPT_NUMBER_OF_VECTORS
323 *
324 */
325
326typedef struct {
327  uint16_t   move_a7;            /* move #FORMAT_ID,%a7@- */
328  uint16_t   format_id;
329  uint16_t   jmp;                /* jmp  _ISR_Handlers */
330  uint32_t   isr_handler;
331} _CPU_ISR_handler_entry;
332
333#define M68K_MOVE_A7 0x3F3C
334#define M68K_JMP     0x4EF9
335
336      /* points to jsr-exception-table in targets wo/ VBR register */
337SCORE_EXTERN _CPU_ISR_handler_entry _CPU_ISR_jump_table[256];
338
339#endif /* M68K_HAS_VBR */
340
341#endif /* ASM */
342
343/* constants */
344
345/*
346 *  This defines the number of levels and the mask used to pick those
347 *  bits out of a thread mode.
348 */
349
350#define CPU_MODES_INTERRUPT_LEVEL  0x00000007 /* interrupt level in mode */
351#define CPU_MODES_INTERRUPT_MASK   0x00000007 /* interrupt level in mode */
352
353/*
354 *  context size area for floating point
355 */
356
357#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
358
359/*
360 *  extra stack required by the MPCI receive server thread
361 */
362
363#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
364
365/*
366 *  m68k family supports 256 distinct vectors.
367 */
368
369#define CPU_INTERRUPT_NUMBER_OF_VECTORS      256
370#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
371
372/*
373 *  This is defined if the port has a special way to report the ISR nesting
374 *  level.  Most ports maintain the variable _ISR_Nest_level.
375 */
376
377#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
378
379/*
380 *  Minimum size of a thread's stack.
381 */
382
383#define CPU_STACK_MINIMUM_SIZE           M68K_CPU_STACK_MINIMUM_SIZE
384
385/*
386 *  Maximum priority of a thread. Note based from 0 which is the idle task.
387 */
388#define CPU_PRIORITY_MAXIMUM             M68K_CPU_PRIORITY_MAXIMUM
389
390/*
391 *  m68k is pretty tolerant of alignment.  Just put things on 4 byte boundaries.
392 */
393
394#define CPU_ALIGNMENT                    4
395#define CPU_HEAP_ALIGNMENT               CPU_ALIGNMENT
396#define CPU_PARTITION_ALIGNMENT          CPU_ALIGNMENT
397
398/*
399 *  On m68k thread stacks require no further alignment after allocation
400 *  from the Workspace.
401 */
402
403#define CPU_STACK_ALIGNMENT        0
404
405#ifndef ASM
406
407/* macros */
408
409/*
410 *  ISR handler macros
411 *
412 *  These macros perform the following functions:
413 *     + initialize the RTEMS vector table
414 *     + disable all maskable CPU interrupts
415 *     + restore previous interrupt level (enable)
416 *     + temporarily restore interrupts (flash)
417 *     + set a particular level
418 */
419
420#define _CPU_Initialize_vectors()
421
422#define _CPU_ISR_Disable( _level ) \
423  m68k_disable_interrupts( _level )
424
425#define _CPU_ISR_Enable( _level ) \
426  m68k_enable_interrupts( _level )
427
428#define _CPU_ISR_Flash( _level ) \
429  m68k_flash_interrupts( _level )
430
431#define _CPU_ISR_Set_level( _newlevel ) \
432   m68k_set_interrupt_level( _newlevel )
433
434uint32_t   _CPU_ISR_Get_level( void );
435
436/* end of ISR handler macros */
437
438/*
439 *  Context handler macros
440 *
441 *  These macros perform the following functions:
442 *     + initialize a context area
443 *     + restart the current thread
444 *     + calculate the initial pointer into a FP context area
445 *     + initialize an FP context area
446 */
447
448#if (defined(__mcoldfire__) && ( M68K_HAS_FPU == 1 ))
449#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
450                                 _isr, _entry_point, _is_fp ) \
451   do { \
452     uint32_t   _stack; \
453     \
454     (_the_context)->sr      = 0x3000 | ((_isr) << 8); \
455     _stack                  = (uint32_t)(_stack_base) + (_size) - 4; \
456     (_the_context)->a7_msp  = (void *)_stack; \
457     *(void **)_stack        = (void *)(_entry_point); \
458     (_the_context)->fpu_dis = (_is_fp == TRUE) ? 0x00 : 0x10;          \
459   } while ( 0 )
460#else
461#define _CPU_Context_Initialize( _the_context, _stack_base, _size,      \
462                                 _isr, _entry_point, _is_fp )           \
463   do {                                                                 \
464     uint32_t   _stack;                                                 \
465                                                                        \
466     (_the_context)->sr      = 0x3000 | ((_isr) << 8);                  \
467     _stack                  = (uint32_t  )(_stack_base) + (_size) - 4; \
468     (_the_context)->a7_msp  = (void *)_stack;                          \
469     *(void **)_stack        = (void *)(_entry_point);                  \
470   } while ( 0 )
471#endif
472
473#define _CPU_Context_Restart_self( _the_context ) \
474  { asm volatile( "movew %0,%%sr ; " \
475                  "moval %1,%%a7 ; " \
476                  "rts"  \
477        : "=d" ((_the_context)->sr), "=d" ((_the_context)->a7_msp) \
478        : "0" ((_the_context)->sr), "1" ((_the_context)->a7_msp) ); \
479  }
480
481/* end of Context handler macros */
482
483/*
484 *  _CPU_Thread_Idle_body
485 *
486 *  This routine is the CPU dependent IDLE thread body.
487 *
488 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
489 *         is TRUE.
490 */
491
492void *_CPU_Thread_Idle_body( uintptr_t ignored );
493
494/*
495 *  Fatal Error manager macros
496 *
497 *  These macros perform the following functions:
498 *    + disable interrupts and halt the CPU
499 */
500
501#if ( defined(__mcoldfire__) )
502#define _CPU_Fatal_halt( _error ) \
503  { asm volatile( "move.w %%sr,%%d0\n\t" \
504                  "or.l %2,%%d0\n\t" \
505                  "move.w %%d0,%%sr\n\t" \
506                  "move.l %1,%%d0\n\t" \
507                  "move.l #0xDEADBEEF,%%d1\n\t" \
508                  "halt" \
509                  : "=g" (_error) \
510                  : "0" (_error), "d"(0x0700) \
511                  : "d0", "d1" ); \
512  }
513#else
514#define _CPU_Fatal_halt( _error ) \
515  { asm volatile( "movl  %0,%%d0; " \
516                  "orw   #0x0700,%%sr; " \
517                  "stop  #0x2700" : "=d" ((_error)) : "0" ((_error)) ); \
518  }
519#endif
520
521/* end of Fatal Error manager macros */
522
523/*
524 *  Bitfield handler macros
525 *
526 *  These macros perform the following functions:
527 *     + scan for the highest numbered (MSB) set in a 16 bit bitfield
528 *
529 *  NOTE:
530 *
531 *    It appears that on the M68020 bitfield are always 32 bits wide
532 *    when in a register.  This code forces the bitfield to be in
533 *    memory (it really always is anyway). This allows us to
534 *    have a real 16 bit wide bitfield which operates "correctly."
535 */
536
537#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
538#define CPU_USE_GENERIC_BITFIELD_DATA FALSE
539
540#if ( M68K_HAS_BFFFO != 1 )
541/*
542 *  Lookup table for BFFFO simulation
543 */
544extern const unsigned char _CPU_m68k_BFFFO_table[256];
545#endif
546
547#if ( M68K_HAS_BFFFO == 1 )
548
549#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
550  asm volatile( "bfffo (%1),#0,#16,%0" : "=d" (_output) : "a" (&_value));
551
552#elif ( __mcfisaaplus__ )
553  /* This is simplified by the fact that RTEMS never calls it with _value=0 */
554#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
555    asm volatile ( \
556       "   swap     %0\n"        \
557       "   ff1.l    %0\n"        \
558       : "=d" ((_output))        \
559       : "0" ((_value))          \
560       : "cc" ) ;
561
562#else
563/* duplicates BFFFO results for 16 bits (i.e., 15-(_priority) in
564   _CPU_Priority_bits_index is not needed), handles the 0 case, and
565   does not molest _value -- jsg */
566#if ( defined(__mcoldfire__) )
567
568#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
569  { \
570    register int dumby; \
571    \
572    asm volatile ( \
573       "   clr.l   %1\n"         \
574       "   move.w  %2,%1\n"      \
575       "   lsr.l   #8,%1\n"      \
576       "   beq.s   1f\n"         \
577       "   move.b  (%3,%1),%0\n" \
578       "   bra.s   0f\n"         \
579       "1: move.w  %2,%1\n"      \
580       "   move.b  (%3,%1),%0\n" \
581       "   addq.l  #8,%0\n"      \
582       "0: and.l   #0xff,%0\n"   \
583       : "=&d" ((_output)), "=&d" ((dumby))    \
584       : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \
585       : "cc" ) ; \
586  }
587#elif ( M68K_HAS_EXTB_L == 1 )
588#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
589  { \
590    register int dumby; \
591    \
592    asm volatile ( "   move.w  %2,%1\n"        \
593       "   lsr.w   #8,%1\n"        \
594       "   beq.s   1f\n"           \
595       "   move.b  (%3,%1.w),%0\n" \
596       "   extb.l  %0\n"           \
597       "   bra.s   0f\n"           \
598       "1: moveq.l #8,%0\n"        \
599       "   add.b   (%3,%2.w),%0\n" \
600       "0:\n"                      \
601       : "=&d" ((_output)), "=&d" ((dumby)) \
602       : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \
603       : "cc" ) ; \
604  }
605#else
606#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
607  { \
608    register int dumby; \
609    \
610    asm volatile ( "   move.w  %2,%1\n"        \
611       "   lsr.w   #8,%1\n"        \
612       "   beq.s   1f\n"           \
613       "   move.b  (%3,%1.w),%0\n" \
614       "   and.l   #0x000000ff,%0\n"\
615       "   bra.s   0f\n"           \
616       "1: moveq.l #8,%0\n"        \
617       "   add.b   (%3,%2.w),%0\n" \
618       "0:\n"                      \
619       : "=&d" ((_output)), "=&d" ((dumby)) \
620       : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \
621       : "cc" ) ; \
622  }
623#endif
624
625#endif
626
627/* end of Bitfield handler macros */
628
629/*
630 *  Priority handler macros
631 *
632 *  These macros perform the following functions:
633 *    + return a mask with the bit for this major/minor portion of
634 *      of thread priority set.
635 *    + translate the bit number returned by "Bitfield_find_first_bit"
636 *      into an index into the thread ready chain bit maps
637 */
638
639#define _CPU_Priority_Mask( _bit_number ) \
640  ( 0x8000 >> (_bit_number) )
641
642#define _CPU_Priority_bits_index( _priority ) \
643  (_priority)
644
645/* end of Priority handler macros */
646
647/* functions */
648
649/*
650 *  _CPU_Initialize
651 *
652 *  This routine performs CPU dependent initialization.
653 */
654
655void _CPU_Initialize(void);
656
657/*
658 *  _CPU_ISR_install_raw_handler
659 *
660 *  This routine installs a "raw" interrupt handler directly into the
661 *  processor's vector table.
662 */
663 
664void _CPU_ISR_install_raw_handler(
665  uint32_t    vector,
666  proc_ptr    new_handler,
667  proc_ptr   *old_handler
668);
669
670/*
671 *  _CPU_ISR_install_vector
672 *
673 *  This routine installs an interrupt vector.
674 */
675
676void _CPU_ISR_install_vector(
677  uint32_t         vector,
678  proc_ptr         new_handler,
679  proc_ptr        *old_handler
680);
681
682/*
683 *  _CPU_Install_interrupt_stack
684 *
685 *  This routine installs the hardware interrupt stack pointer.
686 */
687
688void _CPU_Install_interrupt_stack( void );
689
690/*
691 *  _CPU_Context_switch
692 *
693 *  This routine switches from the run context to the heir context.
694 */
695
696void _CPU_Context_switch(
697  Context_Control  *run,
698  Context_Control  *heir
699);
700
701/*
702 *  _CPU_Context_save_fp
703 *
704 *  This routine saves the floating point context passed to it.
705 */
706
707void _CPU_Context_save_fp(
708  Context_Control_fp **fp_context_ptr
709);
710
711/*
712 *  _CPU_Context_restore_fp
713 *
714 *  This routine restores the floating point context passed to it.
715 */
716
717void _CPU_Context_restore_fp(
718  Context_Control_fp **fp_context_ptr
719);
720
721#if (M68K_HAS_FPSP_PACKAGE == 1)
722/*
723 *  Hooks for the Floating Point Support Package (FPSP) provided by Motorola
724 *
725 *  NOTES: 
726 *
727 *  Motorola 68k family CPU's before the 68040 used a coprocessor
728 *  (68881 or 68882) to handle floating point.  The 68040 has internal
729 *  floating point support -- but *not* the complete support provided by
730 *  the 68881 or 68882.  The leftover functions are taken care of by the
731 *  M68040 Floating Point Support Package.  Quoting from the MC68040
732 *  Microprocessors User's Manual, Section 9, Floating-Point Unit (MC68040):
733 *
734 *    "When used with the M68040FPSP, the MC68040 FPU is fully
735 *    compliant with IEEE floating-point standards."
736 *
737 *  M68KFPSPInstallExceptionHandlers is in libcpu/m68k/MODEL/fpsp and
738 *  is invoked early in the application code to ensure that proper FP
739 *  behavior is installed.  This is not left to the BSP to call, since
740 *  this would force all applications using that BSP to use FPSP which
741 *  is not necessarily desirable.
742 *
743 *  There is a similar package for the 68060 but RTEMS does not yet
744 *  support the 68060.
745 */
746
747void M68KFPSPInstallExceptionHandlers (void);
748
749SCORE_EXTERN int (*_FPSP_install_raw_handler)(
750  uint32_t   vector,
751  proc_ptr new_handler,
752  proc_ptr *old_handler
753);
754
755#endif
756
757
758#endif
759
760#ifdef __cplusplus
761}
762#endif
763
764#endif
Note: See TracBrowser for help on using the repository browser.