source: rtems/cpukit/score/cpu/m68k/rtems/score/cpu.h @ 18a5db2

5
Last change on this file since 18a5db2 was 18a5db2, checked in by Sebastian Huber <sebastian.huber@…>, on Feb 3, 2016 at 10:48:31 AM

m68k: Avoid SCORE_EXTERN

Update #2559.

  • Property mode set to 100644
File size: 19.4 KB
Line 
1/**
2 * @file
3 *
4 * @brief Motorola M68K CPU Dependent Source
5 *
6 * This include file contains information pertaining to the Motorola
7 * m68xxx processor family.
8 */
9
10/*
11 *  COPYRIGHT (c) 1989-2011.
12 *  On-Line Applications Research Corporation (OAR).
13 *
14 *  The license and distribution terms for this file may be
15 *  found in the file LICENSE in this distribution or at
16 *  http://www.rtems.org/license/LICENSE.
17 */
18
19#ifndef _RTEMS_SCORE_CPU_H
20#define _RTEMS_SCORE_CPU_H
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26#include <rtems/score/types.h>
27#include <rtems/score/m68k.h>
28
29/* conditional compilation parameters */
30
31#define CPU_INLINE_ENABLE_DISPATCH       TRUE
32
33/*
34 *  Does the CPU follow the simple vectored interrupt model?
35 *
36 *  If TRUE, then RTEMS allocates the vector table it internally manages.
37 *  If FALSE, then the BSP is assumed to allocate and manage the vector
38 *  table
39 *
40 *  M68K Specific Information:
41 *
42 *  XXX document implementation including references if appropriate
43 */
44#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
45
46/*
47 *  Use the m68k's hardware interrupt stack support and have the
48 *  interrupt manager allocate the memory for it.
49 */
50
51#if ( M68K_HAS_SEPARATE_STACKS == 1)
52#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 0
53#define CPU_HAS_HARDWARE_INTERRUPT_STACK 1
54#else
55#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 1
56#define CPU_HAS_HARDWARE_INTERRUPT_STACK 0
57#endif
58#define CPU_ALLOCATE_INTERRUPT_STACK     1
59
60/*
61 *  Does the RTEMS invoke the user's ISR with the vector number and
62 *  a pointer to the saved interrupt frame (1) or just the vector
63 *  number (0)?
64 */
65
66#define CPU_ISR_PASSES_FRAME_POINTER 0
67
68/*
69 *  Some family members have no FP, some have an FPU such as the
70 *  MC68881/MC68882 for the MC68020, others have it built in (MC68030, 040).
71 *
72 *  NOTE:  If on a CPU without hardware FP, then one can use software
73 *         emulation.  The gcc software FP emulation code has data which
74 *         must be contexted switched on a per task basis.
75 */
76
77#if ( M68K_HAS_FPU == 1 ) || ( M68K_HAS_EMAC == 1 )
78  #define CPU_HARDWARE_FP TRUE
79  #define CPU_SOFTWARE_FP FALSE
80#else
81  #define CPU_HARDWARE_FP FALSE
82  #if defined( __GNUC__ )
83    #define CPU_SOFTWARE_FP TRUE
84  #else
85    #define CPU_SOFTWARE_FP FALSE
86  #endif
87#endif
88
89/*
90 *  All tasks are not by default floating point tasks on this CPU.
91 *  The IDLE task does not have a floating point context on this CPU.
92 *  It is safe to use the deferred floating point context switch
93 *  algorithm on this CPU.
94 */
95
96#define CPU_ALL_TASKS_ARE_FP             FALSE
97#define CPU_IDLE_TASK_IS_FP              FALSE
98#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
99
100#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
101#define CPU_STACK_GROWS_UP               FALSE
102
103/* FIXME: Is this the right value? */
104#define CPU_CACHE_LINE_BYTES 16
105
106#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
107
108/*
109 *  Define what is required to specify how the network to host conversion
110 *  routines are handled.
111 */
112
113#define CPU_BIG_ENDIAN                           TRUE
114#define CPU_LITTLE_ENDIAN                        FALSE
115
116#define CPU_PER_CPU_CONTROL_SIZE 0
117
118#if ( CPU_HARDWARE_FP == TRUE ) && !defined( __mcoldfire__ )
119  #if defined( __mc68060__ )
120    #define M68K_FP_STATE_SIZE 16
121  #else
122    #define M68K_FP_STATE_SIZE 216
123  #endif
124#endif
125
126#ifndef ASM
127
128/* structures */
129
130typedef struct {
131  /* There is no CPU specific per-CPU state */
132} CPU_Per_CPU_control;
133
134/*
135 *  Basic integer context for the m68k family.
136 */
137
138typedef struct {
139  uint32_t    sr;                /* (sr) status register */
140  uint32_t    d2;                /* (d2) data register 2 */
141  uint32_t    d3;                /* (d3) data register 3 */
142  uint32_t    d4;                /* (d4) data register 4 */
143  uint32_t    d5;                /* (d5) data register 5 */
144  uint32_t    d6;                /* (d6) data register 6 */
145  uint32_t    d7;                /* (d7) data register 7 */
146  void       *a2;                /* (a2) address register 2 */
147  void       *a3;                /* (a3) address register 3 */
148  void       *a4;                /* (a4) address register 4 */
149  void       *a5;                /* (a5) address register 5 */
150  void       *a6;                /* (a6) address register 6 */
151  void       *a7_msp;            /* (a7) master stack pointer */
152  #if defined( __mcoldfire__ ) && ( M68K_HAS_FPU == 1 )
153    uint8_t   fpu_dis;
154  #endif
155} Context_Control;
156
157#define _CPU_Context_Get_SP( _context ) \
158  (_context)->a7_msp
159
160/*
161 *  Floating point context areas and support routines
162 */
163
164#if ( CPU_SOFTWARE_FP == TRUE )
165  /*
166   *  This is the same as gcc's view of the software FP condition code
167   *  register _fpCCR.  The implementation of the emulation code is
168   *  in the gcc-VERSION/config/m68k directory.  This structure is
169   *  correct as of gcc 2.7.2.2.
170   */
171  typedef struct {
172    uint16_t _exception_bits;
173    uint16_t _trap_enable_bits;
174    uint16_t _sticky_bits;
175    uint16_t _rounding_mode;
176    uint16_t _format;
177    uint16_t _last_operation;
178    union {
179      float sf;
180      double df;
181    } _operand1;
182    union {
183      float sf;
184      double df;
185    } _operand2;
186  } Context_Control_fp;
187
188  /*
189   *  This software FP implementation is only for GCC.
190   */
191  #define _CPU_Context_Fp_start( _base, _offset ) \
192     ((void *) _Addresses_Add_offset( (_base), (_offset) ) )
193
194  #define _CPU_Context_Initialize_fp( _fp_area ) \
195     { \
196       Context_Control_fp *_fp; \
197       _fp = *(Context_Control_fp **)_fp_area; \
198       _fp->_exception_bits = 0; \
199       _fp->_trap_enable_bits = 0; \
200       _fp->_sticky_bits = 0; \
201       _fp->_rounding_mode = 0;  /* ROUND_TO_NEAREST */ \
202       _fp->_format = 0;         /* NIL */ \
203       _fp->_last_operation = 0; /* NOOP */ \
204       _fp->_operand1.df = 0; \
205       _fp->_operand2.df = 0; \
206     }
207#endif
208
209#if ( CPU_HARDWARE_FP == TRUE )
210  #if defined( __mcoldfire__ )
211    /* We need memset() to initialize the FP context */
212    #include <string.h>
213
214    #if ( M68K_HAS_FPU == 1 )
215      /*
216       * The Cache Control Register (CACR) has write-only access.  It is also
217       * used to enable and disable the FPU.  We need to maintain a copy of
218       * this register to allow per thread values.
219       */
220      extern uint32_t _CPU_cacr_shadow;
221    #endif
222
223    /* We assume that each ColdFire core with a FPU has also an EMAC unit */
224    typedef struct {
225      uint32_t emac_macsr;
226      uint32_t emac_acc0;
227      uint32_t emac_acc1;
228      uint32_t emac_acc2;
229      uint32_t emac_acc3;
230      uint32_t emac_accext01;
231      uint32_t emac_accext23;
232      uint32_t emac_mask;
233      #if ( M68K_HAS_FPU == 1 )
234        uint16_t fp_state_format;
235        uint16_t fp_state_fpcr;
236        double fp_state_op;
237        uint32_t fp_state_fpsr;
238
239        /*
240         * We need to save the FP Instruction Address Register (FPIAR), because
241         * a context switch can occur within a FP exception before the handler
242         * was able to save this register.
243         */
244        uint32_t fp_fpiar;
245
246        double fp_data [8];
247      #endif
248    } Context_Control_fp;
249
250    #define _CPU_Context_Fp_start( _base, _offset ) \
251      ((void *) _Addresses_Add_offset( (_base), (_offset) ))
252
253    /*
254     * The reset value for all context relevant registers except the FP data
255     * registers is zero.  The reset value of the FP data register is NAN.  The
256     * restore of the reset FP state will reset the FP data registers, so the
257     * initial value of them can be arbitrary here.
258     */
259    #define _CPU_Context_Initialize_fp( _fp_area ) \
260      memset( *(_fp_area), 0, sizeof( Context_Control_fp ) )
261  #else
262    /*
263     *  FP context save area for the M68881/M68882 and 68060 numeric
264     *  coprocessors.
265     */
266    typedef struct {
267      /*
268       * M68K_FP_STATE_SIZE bytes for FSAVE/FRESTORE
269       * 96 bytes for FMOVEM FP0-7
270       * 12 bytes for FMOVEM CREGS
271       * 4 bytes for non-null flag
272       */
273      uint8_t fp_save_area [M68K_FP_STATE_SIZE + 112];
274    } Context_Control_fp;
275
276    #define _CPU_Context_Fp_start( _base, _offset ) \
277       ( \
278         (void *) _Addresses_Add_offset( \
279            (_base), \
280            (_offset) + CPU_CONTEXT_FP_SIZE - 4 \
281         ) \
282       )
283
284    #define _CPU_Context_Initialize_fp( _fp_area ) \
285       { \
286         uint32_t   *_fp_context = (uint32_t *)*(_fp_area); \
287         *(--(_fp_context)) = 0; \
288         *(_fp_area) = (void *)(_fp_context); \
289       }
290  #endif
291#endif
292
293/*
294 *  The following structures define the set of information saved
295 *  on the current stack by RTEMS upon receipt of each exc/interrupt.
296 *  These are not used by m68k handlers.
297 *  The exception frame is for rdbg.
298 */
299
300typedef struct {
301  uint32_t   vecnum; /* vector number */
302} CPU_Interrupt_frame;
303
304typedef struct {
305  uint32_t   vecnum; /* vector number */
306  uint32_t   sr; /* status register */
307  uint32_t   pc; /* program counter */
308  uint32_t   d0, d1, d2, d3, d4, d5, d6, d7;
309  uint32_t   a0, a1, a2, a3, a4, a5, a6, a7;
310} CPU_Exception_frame;
311
312/* variables */
313
314extern void*                     _VBR;
315
316#endif /* ASM */
317
318/* constants */
319
320/*
321 *  This defines the number of levels and the mask used to pick those
322 *  bits out of a thread mode.
323 */
324
325#define CPU_MODES_INTERRUPT_LEVEL  0x00000007 /* interrupt level in mode */
326#define CPU_MODES_INTERRUPT_MASK   0x00000007 /* interrupt level in mode */
327
328/*
329 *  context size area for floating point
330 */
331
332#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
333
334/*
335 *  extra stack required by the MPCI receive server thread
336 */
337
338#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
339
340/*
341 *  m68k family supports 256 distinct vectors.
342 */
343
344#define CPU_INTERRUPT_NUMBER_OF_VECTORS      256
345#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
346
347/*
348 *  This is defined if the port has a special way to report the ISR nesting
349 *  level.  Most ports maintain the variable _ISR_Nest_level.
350 */
351
352#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
353
354/*
355 *  Minimum size of a thread's stack.
356 */
357
358#define CPU_STACK_MINIMUM_SIZE           M68K_CPU_STACK_MINIMUM_SIZE
359
360/*
361 *  Maximum priority of a thread. Note based from 0 which is the idle task.
362 */
363#define CPU_PRIORITY_MAXIMUM             M68K_CPU_PRIORITY_MAXIMUM
364
365#define CPU_SIZEOF_POINTER 4
366
367/*
368 *  m68k is pretty tolerant of alignment.  Just put things on 4 byte boundaries.
369 */
370
371#define CPU_ALIGNMENT                    4
372#define CPU_HEAP_ALIGNMENT               CPU_ALIGNMENT
373#define CPU_PARTITION_ALIGNMENT          CPU_ALIGNMENT
374
375/*
376 *  On m68k thread stacks require no further alignment after allocation
377 *  from the Workspace.
378 */
379
380#define CPU_STACK_ALIGNMENT        0
381
382#ifndef ASM
383
384/* macros */
385
386/*
387 *  ISR handler macros
388 *
389 *  These macros perform the following functions:
390 *     + initialize the RTEMS vector table
391 *     + disable all maskable CPU interrupts
392 *     + restore previous interrupt level (enable)
393 *     + temporarily restore interrupts (flash)
394 *     + set a particular level
395 */
396
397#define _CPU_Initialize_vectors()
398
399#define _CPU_ISR_Disable( _level ) \
400  m68k_disable_interrupts( _level )
401
402#define _CPU_ISR_Enable( _level ) \
403  m68k_enable_interrupts( _level )
404
405#define _CPU_ISR_Flash( _level ) \
406  m68k_flash_interrupts( _level )
407
408#define _CPU_ISR_Set_level( _newlevel ) \
409   m68k_set_interrupt_level( _newlevel )
410
411uint32_t   _CPU_ISR_Get_level( void );
412
413/* end of ISR handler macros */
414
415/*
416 *  Context handler macros
417 *
418 *  These macros perform the following functions:
419 *     + initialize a context area
420 *     + restart the current thread
421 *     + calculate the initial pointer into a FP context area
422 *     + initialize an FP context area
423 */
424
425void _CPU_Context_Initialize(
426  Context_Control *the_context,
427  void *stack_area_begin,
428  size_t stack_area_size,
429  uint32_t new_level,
430  void (*entry_point)( void ),
431  bool is_fp,
432  void *tls_area
433);
434
435/* end of Context handler macros */
436
437/*
438 *  _CPU_Thread_Idle_body
439 *
440 *  This routine is the CPU dependent IDLE thread body.
441 *
442 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
443 *         is TRUE.
444 */
445
446void *_CPU_Thread_Idle_body( uintptr_t ignored );
447
448/*
449 *  Fatal Error manager macros
450 *
451 *  These macros perform the following functions:
452 *    + disable interrupts and halt the CPU
453 */
454
455#if ( defined(__mcoldfire__) )
456#define _CPU_Fatal_halt( _source, _error ) \
457  { __asm__ volatile( "move.w %%sr,%%d0\n\t" \
458                  "or.l %2,%%d0\n\t" \
459                  "move.w %%d0,%%sr\n\t" \
460                  "move.l %1,%%d0\n\t" \
461                  "move.l #0xDEADBEEF,%%d1\n\t" \
462                  "halt" \
463                  : "=g" (_error) \
464                  : "0" (_error), "d"(0x0700) \
465                  : "d0", "d1" ); \
466  }
467#else
468#define _CPU_Fatal_halt( _source, _error ) \
469  { __asm__ volatile( "movl  %0,%%d0; " \
470                  "orw   #0x0700,%%sr; " \
471                  "stop  #0x2700" : "=d" ((_error)) : "0" ((_error)) ); \
472  }
473#endif
474
475/* end of Fatal Error manager macros */
476
477/*
478 *  Bitfield handler macros
479 *
480 *  These macros perform the following functions:
481 *     + scan for the highest numbered (MSB) set in a 16 bit bitfield
482 *
483 *  NOTE:
484 *
485 *    It appears that on the M68020 bitfield are always 32 bits wide
486 *    when in a register.  This code forces the bitfield to be in
487 *    memory (it really always is anyway). This allows us to
488 *    have a real 16 bit wide bitfield which operates "correctly."
489 */
490
491#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
492#define CPU_USE_GENERIC_BITFIELD_DATA FALSE
493
494#if ( M68K_HAS_BFFFO != 1 )
495/*
496 *  Lookup table for BFFFO simulation
497 */
498extern const unsigned char _CPU_m68k_BFFFO_table[256];
499#endif
500
501#if ( M68K_HAS_BFFFO == 1 )
502
503#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
504  __asm__ volatile( "bfffo (%1),#0,#16,%0" : "=d" (_output) : "a" (&_value));
505
506#elif ( __mcfisaaplus__ )
507  /* This is simplified by the fact that RTEMS never calls it with _value=0 */
508#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
509    __asm__ volatile ( \
510       "   swap     %0\n"        \
511       "   ff1.l    %0\n"        \
512       : "=d" ((_output))        \
513       : "0" ((_value))          \
514       : "cc" ) ;
515
516#else
517/* duplicates BFFFO results for 16 bits (i.e., 15-(_priority) in
518   _CPU_Priority_bits_index is not needed), handles the 0 case, and
519   does not molest _value -- jsg */
520#if ( defined(__mcoldfire__) )
521
522#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
523  { \
524    register int dumby; \
525    \
526    __asm__ volatile ( \
527       "   clr.l   %1\n"         \
528       "   move.w  %2,%1\n"      \
529       "   lsr.l   #8,%1\n"      \
530       "   beq.s   1f\n"         \
531       "   move.b  (%3,%1),%0\n" \
532       "   bra.s   0f\n"         \
533       "1: move.w  %2,%1\n"      \
534       "   move.b  (%3,%1),%0\n" \
535       "   addq.l  #8,%0\n"      \
536       "0: and.l   #0xff,%0\n"   \
537       : "=&d" ((_output)), "=&d" ((dumby))    \
538       : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \
539       : "cc" ) ; \
540  }
541#elif ( M68K_HAS_EXTB_L == 1 )
542#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
543  { \
544    register int dumby; \
545    \
546    __asm__ volatile ( "   move.w  %2,%1\n"        \
547       "   lsr.w   #8,%1\n"        \
548       "   beq.s   1f\n"           \
549       "   move.b  (%3,%1.w),%0\n" \
550       "   extb.l  %0\n"           \
551       "   bra.s   0f\n"           \
552       "1: moveq.l #8,%0\n"        \
553       "   add.b   (%3,%2.w),%0\n" \
554       "0:\n"                      \
555       : "=&d" ((_output)), "=&d" ((dumby)) \
556       : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \
557       : "cc" ) ; \
558  }
559#else
560#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
561  { \
562    register int dumby; \
563    \
564    __asm__ volatile ( "   move.w  %2,%1\n"        \
565       "   lsr.w   #8,%1\n"        \
566       "   beq.s   1f\n"           \
567       "   move.b  (%3,%1.w),%0\n" \
568       "   and.l   #0x000000ff,%0\n"\
569       "   bra.s   0f\n"           \
570       "1: moveq.l #8,%0\n"        \
571       "   add.b   (%3,%2.w),%0\n" \
572       "0:\n"                      \
573       : "=&d" ((_output)), "=&d" ((dumby)) \
574       : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \
575       : "cc" ) ; \
576  }
577#endif
578
579#endif
580
581/* end of Bitfield handler macros */
582
583/*
584 *  Priority handler macros
585 *
586 *  These macros perform the following functions:
587 *    + return a mask with the bit for this major/minor portion of
588 *      of thread priority set.
589 *    + translate the bit number returned by "Bitfield_find_first_bit"
590 *      into an index into the thread ready chain bit maps
591 */
592
593#define _CPU_Priority_Mask( _bit_number ) \
594  ( 0x8000 >> (_bit_number) )
595
596#define _CPU_Priority_bits_index( _priority ) \
597  (_priority)
598
599/* end of Priority handler macros */
600
601/* functions */
602
603/*
604 *  _CPU_Initialize
605 *
606 *  This routine performs CPU dependent initialization.
607 */
608
609void _CPU_Initialize(void);
610
611/*
612 *  _CPU_ISR_install_raw_handler
613 *
614 *  This routine installs a "raw" interrupt handler directly into the
615 *  processor's vector table.
616 */
617
618void _CPU_ISR_install_raw_handler(
619  uint32_t    vector,
620  proc_ptr    new_handler,
621  proc_ptr   *old_handler
622);
623
624/*
625 *  _CPU_ISR_install_vector
626 *
627 *  This routine installs an interrupt vector.
628 */
629
630void _CPU_ISR_install_vector(
631  uint32_t         vector,
632  proc_ptr         new_handler,
633  proc_ptr        *old_handler
634);
635
636/*
637 *  _CPU_Install_interrupt_stack
638 *
639 *  This routine installs the hardware interrupt stack pointer.
640 */
641
642void _CPU_Install_interrupt_stack( void );
643
644/*
645 *  _CPU_Context_switch
646 *
647 *  This routine switches from the run context to the heir context.
648 */
649
650void _CPU_Context_switch(
651  Context_Control  *run,
652  Context_Control  *heir
653);
654
655void _CPU_Context_Restart_self(
656  Context_Control  *the_context
657) RTEMS_NO_RETURN;
658
659/*
660 *  _CPU_Context_save_fp
661 *
662 *  This routine saves the floating point context passed to it.
663 */
664
665void _CPU_Context_save_fp(
666  Context_Control_fp **fp_context_ptr
667);
668
669/*
670 *  _CPU_Context_restore_fp
671 *
672 *  This routine restores the floating point context passed to it.
673 */
674
675void _CPU_Context_restore_fp(
676  Context_Control_fp **fp_context_ptr
677);
678
679static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
680{
681  /* TODO */
682}
683
684static inline void _CPU_Context_validate( uintptr_t pattern )
685{
686  while (1) {
687    /* TODO */
688  }
689}
690
691/**
692 *  This method prints the CPU exception frame.
693 *
694 *  @param[in] frame points to the frame to be printed
695 */
696void _CPU_Exception_frame_print(
697  const CPU_Exception_frame *frame
698);
699
700typedef uint32_t CPU_Counter_ticks;
701
702CPU_Counter_ticks _CPU_Counter_read( void );
703
704static inline CPU_Counter_ticks _CPU_Counter_difference(
705  CPU_Counter_ticks second,
706  CPU_Counter_ticks first
707)
708{
709  return second - first;
710}
711
712#if (M68K_HAS_FPSP_PACKAGE == 1)
713/*
714 *  Hooks for the Floating Point Support Package (FPSP) provided by Motorola
715 *
716 *  NOTES:
717 *
718 *  Motorola 68k family CPU's before the 68040 used a coprocessor
719 *  (68881 or 68882) to handle floating point.  The 68040 has internal
720 *  floating point support -- but *not* the complete support provided by
721 *  the 68881 or 68882.  The leftover functions are taken care of by the
722 *  M68040 Floating Point Support Package.  Quoting from the MC68040
723 *  Microprocessors User's Manual, Section 9, Floating-Point Unit (MC68040):
724 *
725 *    "When used with the M68040FPSP, the MC68040 FPU is fully
726 *    compliant with IEEE floating-point standards."
727 *
728 *  M68KFPSPInstallExceptionHandlers is in libcpu/m68k/MODEL/fpsp and
729 *  is invoked early in the application code to ensure that proper FP
730 *  behavior is installed.  This is not left to the BSP to call, since
731 *  this would force all applications using that BSP to use FPSP which
732 *  is not necessarily desirable.
733 *
734 *  There is a similar package for the 68060 but RTEMS does not yet
735 *  support the 68060.
736 */
737
738void M68KFPSPInstallExceptionHandlers (void);
739
740extern int (*_FPSP_install_raw_handler)(
741  uint32_t   vector,
742  proc_ptr new_handler,
743  proc_ptr *old_handler
744);
745
746#endif
747
748
749#endif
750
751#ifdef __cplusplus
752}
753#endif
754
755#endif
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