[7908ba5b] | 1 | /* cpu.h |
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| 2 | * |
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| 3 | * This include file contains information pertaining to the Motorola |
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| 4 | * m68xxx processor family. |
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| 5 | * |
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[08311cc3] | 6 | * COPYRIGHT (c) 1989-1999. |
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[7908ba5b] | 7 | * On-Line Applications Research Corporation (OAR). |
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| 8 | * |
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| 9 | * The license and distribution terms for this file may be |
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| 10 | * found in the file LICENSE in this distribution or at |
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| 11 | * http://www.OARcorp.com/rtems/license.html. |
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| 12 | * |
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| 13 | * $Id$ |
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| 14 | */ |
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| 15 | |
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| 16 | #ifndef __CPU_h |
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| 17 | #define __CPU_h |
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| 18 | |
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| 19 | #ifdef __cplusplus |
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| 20 | extern "C" { |
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| 21 | #endif |
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| 22 | |
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| 23 | #include <rtems/score/m68k.h> /* pick up machine definitions */ |
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| 24 | #ifndef ASM |
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| 25 | #include <rtems/score/m68ktypes.h> |
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| 26 | #endif |
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| 27 | |
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| 28 | /* conditional compilation parameters */ |
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| 29 | |
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| 30 | #define CPU_INLINE_ENABLE_DISPATCH TRUE |
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| 31 | #define CPU_UNROLL_ENQUEUE_PRIORITY FALSE |
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| 32 | |
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| 33 | /* |
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| 34 | * Use the m68k's hardware interrupt stack support and have the |
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| 35 | * interrupt manager allocate the memory for it. |
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| 36 | */ |
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| 37 | |
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| 38 | #if ( M68K_HAS_SEPARATE_STACKS == 1) |
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| 39 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK 0 |
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| 40 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK 1 |
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| 41 | #else |
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| 42 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK 1 |
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| 43 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK 0 |
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| 44 | #endif |
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| 45 | #define CPU_ALLOCATE_INTERRUPT_STACK 1 |
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| 46 | |
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| 47 | /* |
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| 48 | * Does the RTEMS invoke the user's ISR with the vector number and |
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| 49 | * a pointer to the saved interrupt frame (1) or just the vector |
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| 50 | * number (0)? |
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| 51 | */ |
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| 52 | |
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| 53 | #define CPU_ISR_PASSES_FRAME_POINTER 0 |
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| 54 | |
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| 55 | /* |
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| 56 | * Some family members have no FP, some have an FPU such as the |
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| 57 | * MC68881/MC68882 for the MC68020, others have it built in (MC68030, 040). |
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| 58 | * |
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| 59 | * NOTE: If on a CPU without hardware FP, then one can use software |
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| 60 | * emulation. The gcc software FP emulation code has data which |
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| 61 | * must be contexted switched on a per task basis. |
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| 62 | */ |
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| 63 | |
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| 64 | #if ( M68K_HAS_FPU == 1 ) |
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| 65 | #define CPU_HARDWARE_FP TRUE |
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| 66 | #define CPU_SOFTWARE_FP FALSE |
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| 67 | #else |
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| 68 | #define CPU_HARDWARE_FP FALSE |
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[6b79a071] | 69 | #if defined(__GNUC__) |
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[7908ba5b] | 70 | #define CPU_SOFTWARE_FP TRUE |
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| 71 | #else |
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| 72 | #define CPU_SOFTWARE_FP FALSE |
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| 73 | #endif |
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| 74 | #endif |
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| 75 | |
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| 76 | /* |
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| 77 | * All tasks are not by default floating point tasks on this CPU. |
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| 78 | * The IDLE task does not have a floating point context on this CPU. |
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| 79 | * It is safe to use the deferred floating point context switch |
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| 80 | * algorithm on this CPU. |
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| 81 | */ |
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| 82 | |
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| 83 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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| 84 | #define CPU_IDLE_TASK_IS_FP FALSE |
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| 85 | #define CPU_USE_DEFERRED_FP_SWITCH TRUE |
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| 86 | |
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| 87 | #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE |
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| 88 | #define CPU_STACK_GROWS_UP FALSE |
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| 89 | #define CPU_STRUCTURE_ALIGNMENT |
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| 90 | |
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| 91 | /* |
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| 92 | * Define what is required to specify how the network to host conversion |
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| 93 | * routines are handled. |
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| 94 | */ |
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| 95 | |
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[6805640e] | 96 | #define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE |
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[7908ba5b] | 97 | #define CPU_BIG_ENDIAN TRUE |
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| 98 | #define CPU_LITTLE_ENDIAN FALSE |
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| 99 | |
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| 100 | #ifndef ASM |
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| 101 | /* structures */ |
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| 102 | |
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| 103 | /* |
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| 104 | * Basic integer context for the m68k family. |
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| 105 | */ |
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| 106 | |
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| 107 | typedef struct { |
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| 108 | unsigned32 sr; /* (sr) status register */ |
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| 109 | unsigned32 d2; /* (d2) data register 2 */ |
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| 110 | unsigned32 d3; /* (d3) data register 3 */ |
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| 111 | unsigned32 d4; /* (d4) data register 4 */ |
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| 112 | unsigned32 d5; /* (d5) data register 5 */ |
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| 113 | unsigned32 d6; /* (d6) data register 6 */ |
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| 114 | unsigned32 d7; /* (d7) data register 7 */ |
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| 115 | void *a2; /* (a2) address register 2 */ |
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| 116 | void *a3; /* (a3) address register 3 */ |
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| 117 | void *a4; /* (a4) address register 4 */ |
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| 118 | void *a5; /* (a5) address register 5 */ |
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| 119 | void *a6; /* (a6) address register 6 */ |
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| 120 | void *a7_msp; /* (a7) master stack pointer */ |
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| 121 | } Context_Control; |
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| 122 | |
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| 123 | /* |
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| 124 | * Floating point context ares |
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| 125 | */ |
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| 126 | |
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| 127 | #if (CPU_SOFTWARE_FP == TRUE) |
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| 128 | |
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| 129 | /* |
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| 130 | * This is the same as gcc's view of the software FP condition code |
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| 131 | * register _fpCCR. The implementation of the emulation code is |
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| 132 | * in the gcc-VERSION/config/m68k directory. This structure is |
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| 133 | * correct as of gcc 2.7.2.2. |
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| 134 | */ |
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| 135 | |
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| 136 | typedef struct { |
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| 137 | unsigned16 _exception_bits; |
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| 138 | unsigned16 _trap_enable_bits; |
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| 139 | unsigned16 _sticky_bits; |
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| 140 | unsigned16 _rounding_mode; |
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| 141 | unsigned16 _format; |
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| 142 | unsigned16 _last_operation; |
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| 143 | union { |
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| 144 | float sf; |
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| 145 | double df; |
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| 146 | } _operand1; |
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| 147 | union { |
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| 148 | float sf; |
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| 149 | double df; |
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| 150 | } _operand2; |
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| 151 | } Context_Control_fp; |
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| 152 | |
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| 153 | #else |
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| 154 | |
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| 155 | /* |
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| 156 | * FP context save area for the M68881/M68882 numeric coprocessors. |
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| 157 | */ |
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| 158 | |
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| 159 | typedef struct { |
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| 160 | unsigned8 fp_save_area[332]; /* 216 bytes for FSAVE/FRESTORE */ |
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| 161 | /* 96 bytes for FMOVEM FP0-7 */ |
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| 162 | /* 12 bytes for FMOVEM CREGS */ |
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| 163 | /* 4 bytes for non-null flag */ |
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| 164 | } Context_Control_fp; |
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| 165 | #endif |
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| 166 | |
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| 167 | /* |
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| 168 | * The following structure defines the set of information saved |
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| 169 | * on the current stack by RTEMS upon receipt of each interrupt. |
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| 170 | */ |
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| 171 | |
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| 172 | typedef struct { |
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| 173 | unsigned32 TBD; /* XXX Fix for this CPU */ |
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| 174 | } CPU_Interrupt_frame; |
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| 175 | |
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| 176 | /* |
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| 177 | * The following table contains the information required to configure |
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| 178 | * the m68k specific parameters. |
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| 179 | */ |
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| 180 | |
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| 181 | typedef struct { |
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| 182 | void (*pretasking_hook)( void ); |
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| 183 | void (*predriver_hook)( void ); |
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| 184 | void (*postdriver_hook)( void ); |
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| 185 | void (*idle_task)( void ); |
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| 186 | boolean do_zero_of_workspace; |
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| 187 | unsigned32 idle_task_stack_size; |
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| 188 | unsigned32 interrupt_stack_size; |
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| 189 | unsigned32 extra_mpci_receive_server_stack; |
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| 190 | void * (*stack_allocate_hook)( unsigned32 ); |
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| 191 | void (*stack_free_hook)( void* ); |
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| 192 | /* end of fields required on all CPUs */ |
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| 193 | |
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| 194 | m68k_isr *interrupt_vector_table; |
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| 195 | } rtems_cpu_table; |
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| 196 | |
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[458bd34] | 197 | /* |
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| 198 | * Macros to access required entires in the CPU Table are in |
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| 199 | * the file rtems/system.h. |
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| 200 | */ |
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| 201 | |
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| 202 | /* |
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| 203 | * Macros to access M68K specific additions to the CPU Table |
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| 204 | */ |
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| 205 | |
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| 206 | #define rtems_cpu_configuration_get_interrupt_vector_table() \ |
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| 207 | (_CPU_Table.interrupt_vector_table) |
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| 208 | |
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[7908ba5b] | 209 | /* variables */ |
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| 210 | |
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| 211 | SCORE_EXTERN void *_CPU_Interrupt_stack_low; |
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| 212 | SCORE_EXTERN void *_CPU_Interrupt_stack_high; |
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| 213 | |
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| 214 | extern char _VBR[]; |
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| 215 | |
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| 216 | #if ( M68K_HAS_VBR == 0 ) |
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| 217 | |
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| 218 | /* |
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| 219 | * Table of ISR handler entries that resides in RAM. The FORMAT/ID is |
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| 220 | * pushed onto the stack. This is not is the same order as VBR processors. |
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| 221 | * The ISR handler takes the format and uses it for dispatching the user |
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| 222 | * handler. |
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| 223 | * |
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| 224 | * FIXME : should be moved to below CPU_INTERRUPT_NUMBER_OF_VECTORS |
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| 225 | * |
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| 226 | */ |
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| 227 | |
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| 228 | typedef struct { |
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| 229 | unsigned16 move_a7; /* move #FORMAT_ID,%a7@- */ |
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| 230 | unsigned16 format_id; |
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| 231 | unsigned16 jmp; /* jmp _ISR_Handlers */ |
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| 232 | unsigned32 isr_handler; |
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| 233 | } _CPU_ISR_handler_entry; |
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| 234 | |
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| 235 | #define M68K_MOVE_A7 0x3F3C |
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| 236 | #define M68K_JMP 0x4EF9 |
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| 237 | |
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| 238 | /* points to jsr-exception-table in targets wo/ VBR register */ |
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| 239 | SCORE_EXTERN _CPU_ISR_handler_entry _CPU_ISR_jump_table[256]; |
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| 240 | |
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| 241 | #endif /* M68K_HAS_VBR */ |
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| 242 | #endif /* ASM */ |
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| 243 | |
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| 244 | /* constants */ |
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| 245 | |
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| 246 | /* |
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| 247 | * This defines the number of levels and the mask used to pick those |
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| 248 | * bits out of a thread mode. |
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| 249 | */ |
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| 250 | |
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| 251 | #define CPU_MODES_INTERRUPT_LEVEL 0x00000007 /* interrupt level in mode */ |
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| 252 | #define CPU_MODES_INTERRUPT_MASK 0x00000007 /* interrupt level in mode */ |
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| 253 | |
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| 254 | /* |
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| 255 | * context size area for floating point |
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| 256 | */ |
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| 257 | |
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| 258 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
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| 259 | |
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| 260 | /* |
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| 261 | * extra stack required by the MPCI receive server thread |
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| 262 | */ |
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| 263 | |
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| 264 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 |
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| 265 | |
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| 266 | /* |
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| 267 | * m68k family supports 256 distinct vectors. |
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| 268 | */ |
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| 269 | |
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| 270 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 |
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| 271 | #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) |
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| 272 | |
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| 273 | /* |
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| 274 | * Minimum size of a thread's stack. |
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| 275 | */ |
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| 276 | |
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[e065e8ae] | 277 | #define CPU_STACK_MINIMUM_SIZE 4096 |
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[7908ba5b] | 278 | |
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| 279 | /* |
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| 280 | * m68k is pretty tolerant of alignment. Just put things on 4 byte boundaries. |
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| 281 | */ |
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| 282 | |
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| 283 | #define CPU_ALIGNMENT 4 |
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| 284 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
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| 285 | #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT |
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| 286 | |
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| 287 | /* |
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| 288 | * On m68k thread stacks require no further alignment after allocation |
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| 289 | * from the Workspace. |
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| 290 | */ |
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| 291 | |
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| 292 | #define CPU_STACK_ALIGNMENT 0 |
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| 293 | |
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| 294 | #ifndef ASM |
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| 295 | |
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| 296 | /* macros */ |
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| 297 | |
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| 298 | /* |
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| 299 | * ISR handler macros |
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| 300 | * |
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| 301 | * These macros perform the following functions: |
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| 302 | * + disable all maskable CPU interrupts |
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| 303 | * + restore previous interrupt level (enable) |
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| 304 | * + temporarily restore interrupts (flash) |
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| 305 | * + set a particular level |
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| 306 | */ |
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| 307 | |
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| 308 | #define _CPU_ISR_Disable( _level ) \ |
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| 309 | m68k_disable_interrupts( _level ) |
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| 310 | |
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| 311 | #define _CPU_ISR_Enable( _level ) \ |
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| 312 | m68k_enable_interrupts( _level ) |
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| 313 | |
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| 314 | #define _CPU_ISR_Flash( _level ) \ |
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| 315 | m68k_flash_interrupts( _level ) |
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| 316 | |
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| 317 | #define _CPU_ISR_Set_level( _newlevel ) \ |
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| 318 | m68k_set_interrupt_level( _newlevel ) |
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| 319 | |
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| 320 | unsigned32 _CPU_ISR_Get_level( void ); |
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| 321 | |
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| 322 | /* end of ISR handler macros */ |
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| 323 | |
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| 324 | /* |
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| 325 | * Context handler macros |
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| 326 | * |
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| 327 | * These macros perform the following functions: |
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| 328 | * + initialize a context area |
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| 329 | * + restart the current thread |
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| 330 | * + calculate the initial pointer into a FP context area |
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| 331 | * + initialize an FP context area |
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| 332 | */ |
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| 333 | |
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| 334 | #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ |
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| 335 | _isr, _entry_point, _is_fp ) \ |
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| 336 | do { \ |
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| 337 | unsigned32 _stack; \ |
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| 338 | \ |
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| 339 | (_the_context)->sr = 0x3000 | ((_isr) << 8); \ |
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| 340 | _stack = (unsigned32)(_stack_base) + (_size) - 4; \ |
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| 341 | (_the_context)->a7_msp = (void *)_stack; \ |
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| 342 | *(void **)_stack = (void *)(_entry_point); \ |
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| 343 | } while ( 0 ) |
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| 344 | |
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| 345 | #define _CPU_Context_Restart_self( _the_context ) \ |
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| 346 | { asm volatile( "movew %0,%%sr ; " \ |
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| 347 | "moval %1,%%a7 ; " \ |
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| 348 | "rts" \ |
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| 349 | : "=d" ((_the_context)->sr), "=d" ((_the_context)->a7_msp) \ |
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| 350 | : "0" ((_the_context)->sr), "1" ((_the_context)->a7_msp) ); \ |
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| 351 | } |
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| 352 | |
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| 353 | /* |
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| 354 | * Floating Point Context Area Support routines |
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| 355 | */ |
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| 356 | |
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| 357 | #if (CPU_SOFTWARE_FP == TRUE) |
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| 358 | |
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| 359 | /* |
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| 360 | * This software FP implementation is only for GCC. |
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| 361 | */ |
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| 362 | |
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| 363 | #define _CPU_Context_Fp_start( _base, _offset ) \ |
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| 364 | ((void *) _Addresses_Add_offset( (_base), (_offset) ) ) |
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| 365 | |
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| 366 | |
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| 367 | #define _CPU_Context_Initialize_fp( _fp_area ) \ |
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| 368 | { \ |
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| 369 | Context_Control_fp *_fp; \ |
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| 370 | _fp = *(Context_Control_fp **)_fp_area; \ |
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| 371 | _fp->_exception_bits = 0; \ |
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| 372 | _fp->_trap_enable_bits = 0; \ |
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| 373 | _fp->_sticky_bits = 0; \ |
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| 374 | _fp->_rounding_mode = 0; /* ROUND_TO_NEAREST */ \ |
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| 375 | _fp->_format = 0; /* NIL */ \ |
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| 376 | _fp->_last_operation = 0; /* NOOP */ \ |
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| 377 | _fp->_operand1.df = 0; \ |
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| 378 | _fp->_operand2.df = 0; \ |
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| 379 | } |
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| 380 | #else |
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| 381 | #define _CPU_Context_Fp_start( _base, _offset ) \ |
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| 382 | ((void *) \ |
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| 383 | _Addresses_Add_offset( \ |
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| 384 | (_base), \ |
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| 385 | (_offset) + CPU_CONTEXT_FP_SIZE - 4 \ |
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| 386 | ) \ |
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| 387 | ) |
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| 388 | |
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| 389 | #define _CPU_Context_Initialize_fp( _fp_area ) \ |
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| 390 | { unsigned32 *_fp_context = (unsigned32 *)*(_fp_area); \ |
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| 391 | \ |
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| 392 | *(--(_fp_context)) = 0; \ |
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| 393 | *(_fp_area) = (unsigned8 *)(_fp_context); \ |
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| 394 | } |
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| 395 | #endif |
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| 396 | |
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| 397 | /* end of Context handler macros */ |
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| 398 | |
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| 399 | /* |
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| 400 | * Fatal Error manager macros |
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| 401 | * |
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| 402 | * These macros perform the following functions: |
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| 403 | * + disable interrupts and halt the CPU |
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| 404 | */ |
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| 405 | |
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| 406 | #if ( M68K_COLDFIRE_ARCH == 1 ) |
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| 407 | #define _CPU_Fatal_halt( _error ) \ |
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| 408 | { asm volatile( "move.w %%sr,%%d0\n\t" \ |
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| 409 | "or.l %2,%%d0\n\t" \ |
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| 410 | "move.w %%d0,%%sr\n\t" \ |
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| 411 | "move.l %1,%%d0\n\t" \ |
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| 412 | "move.l #0xDEADBEEF,%%d1\n\t" \ |
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| 413 | "halt" \ |
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| 414 | : "=g" (_error) \ |
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| 415 | : "0" (_error), "d"(0x0700) \ |
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| 416 | : "d0", "d1" ); \ |
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| 417 | } |
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| 418 | #else |
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| 419 | #define _CPU_Fatal_halt( _error ) \ |
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| 420 | { asm volatile( "movl %0,%%d0; " \ |
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| 421 | "orw #0x0700,%%sr; " \ |
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| 422 | "stop #0x2700" : "=d" ((_error)) : "0" ((_error)) ); \ |
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| 423 | } |
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| 424 | #endif |
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| 425 | |
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| 426 | /* end of Fatal Error manager macros */ |
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| 427 | |
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| 428 | /* |
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| 429 | * Bitfield handler macros |
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| 430 | * |
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| 431 | * These macros perform the following functions: |
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| 432 | * + scan for the highest numbered (MSB) set in a 16 bit bitfield |
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| 433 | * |
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| 434 | * NOTE: |
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| 435 | * |
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| 436 | * It appears that on the M68020 bitfield are always 32 bits wide |
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| 437 | * when in a register. This code forces the bitfield to be in |
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| 438 | * memory (it really always is anyway). This allows us to |
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| 439 | * have a real 16 bit wide bitfield which operates "correctly." |
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| 440 | */ |
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| 441 | |
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| 442 | #define CPU_USE_GENERIC_BITFIELD_CODE FALSE |
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| 443 | #define CPU_USE_GENERIC_BITFIELD_DATA FALSE |
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| 444 | |
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| 445 | #if ( M68K_HAS_BFFFO == 1 ) |
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| 446 | |
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| 447 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
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| 448 | asm volatile( "bfffo (%1),#0,#16,%0" : "=d" (_output) : "a" (&_value)); |
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| 449 | #else |
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| 450 | |
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| 451 | /* duplicates BFFFO results for 16 bits (i.e., 15-(_priority) in |
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| 452 | _CPU_Priority_bits_index is not needed), handles the 0 case, and |
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| 453 | does not molest _value -- jsg */ |
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| 454 | #if ( M68K_COLDFIRE_ARCH == 1 ) |
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| 455 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
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| 456 | { \ |
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| 457 | extern const unsigned char __BFFFOtable[256]; \ |
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| 458 | register int dumby; \ |
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| 459 | \ |
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| 460 | asm volatile ( \ |
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| 461 | " clr.l %1\n" \ |
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| 462 | " move.w %2,%1\n" \ |
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| 463 | " lsr.l #8,%1\n" \ |
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| 464 | " beq.s 1f\n" \ |
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| 465 | " move.b (%3,%1),%0\n" \ |
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| 466 | " bra.s 0f\n" \ |
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| 467 | "1: move.w %2,%1\n" \ |
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| 468 | " move.b (%3,%1),%0\n" \ |
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| 469 | " addq.l #8,%0\n" \ |
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| 470 | "0: and.l #0xff,%0\n" \ |
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| 471 | : "=&d" ((_output)), "=&d" ((dumby)) \ |
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| 472 | : "d" ((_value)), "ao" ((__BFFFOtable)) \ |
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| 473 | : "cc" ) ; \ |
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| 474 | } |
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| 475 | #elif ( M68K_HAS_EXTB_L == 1 ) |
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| 476 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
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| 477 | { \ |
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| 478 | extern const unsigned char __BFFFOtable[256]; \ |
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| 479 | register int dumby; \ |
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| 480 | \ |
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| 481 | asm volatile ( " move.w %2,%1\n" \ |
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| 482 | " lsr.w #8,%1\n" \ |
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| 483 | " beq.s 1f\n" \ |
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| 484 | " move.b (%3,%1.w),%0\n" \ |
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| 485 | " extb.l %0\n" \ |
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| 486 | " bra.s 0f\n" \ |
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| 487 | "1: moveq.l #8,%0\n" \ |
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| 488 | " add.b (%3,%2.w),%0\n" \ |
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| 489 | "0:\n" \ |
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| 490 | : "=&d" ((_output)), "=&d" ((dumby)) \ |
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| 491 | : "d" ((_value)), "ao" ((__BFFFOtable)) \ |
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| 492 | : "cc" ) ; \ |
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| 493 | } |
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| 494 | #else |
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| 495 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
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| 496 | { \ |
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| 497 | extern const unsigned char __BFFFOtable[256]; \ |
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| 498 | register int dumby; \ |
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| 499 | \ |
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| 500 | asm volatile ( " move.w %2,%1\n" \ |
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| 501 | " lsr.w #8,%1\n" \ |
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| 502 | " beq.s 1f\n" \ |
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| 503 | " move.b (%3,%1.w),%0\n" \ |
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| 504 | " and.l #0x000000ff,%0\n"\ |
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| 505 | " bra.s 0f\n" \ |
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| 506 | "1: moveq.l #8,%0\n" \ |
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| 507 | " add.b (%3,%2.w),%0\n" \ |
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| 508 | "0:\n" \ |
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| 509 | : "=&d" ((_output)), "=&d" ((dumby)) \ |
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| 510 | : "d" ((_value)), "ao" ((__BFFFOtable)) \ |
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| 511 | : "cc" ) ; \ |
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| 512 | } |
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| 513 | #endif |
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| 514 | |
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| 515 | #endif |
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| 516 | |
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| 517 | /* end of Bitfield handler macros */ |
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| 518 | |
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| 519 | /* |
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| 520 | * Priority handler macros |
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| 521 | * |
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| 522 | * These macros perform the following functions: |
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| 523 | * + return a mask with the bit for this major/minor portion of |
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| 524 | * of thread priority set. |
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| 525 | * + translate the bit number returned by "Bitfield_find_first_bit" |
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| 526 | * into an index into the thread ready chain bit maps |
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| 527 | */ |
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| 528 | |
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| 529 | #define _CPU_Priority_Mask( _bit_number ) \ |
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| 530 | ( 0x8000 >> (_bit_number) ) |
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| 531 | |
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| 532 | #define _CPU_Priority_bits_index( _priority ) \ |
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| 533 | (_priority) |
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| 534 | |
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| 535 | /* end of Priority handler macros */ |
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| 536 | |
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| 537 | /* functions */ |
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| 538 | |
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| 539 | /* |
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| 540 | * _CPU_Initialize |
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| 541 | * |
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| 542 | * This routine performs CPU dependent initialization. |
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| 543 | */ |
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| 544 | |
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| 545 | void _CPU_Initialize( |
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| 546 | rtems_cpu_table *cpu_table, |
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| 547 | void (*thread_dispatch) |
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| 548 | ); |
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| 549 | |
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| 550 | /* |
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| 551 | * _CPU_ISR_install_raw_handler |
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| 552 | * |
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| 553 | * This routine installs a "raw" interrupt handler directly into the |
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| 554 | * processor's vector table. |
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| 555 | */ |
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| 556 | |
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| 557 | void _CPU_ISR_install_raw_handler( |
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| 558 | unsigned32 vector, |
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| 559 | proc_ptr new_handler, |
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| 560 | proc_ptr *old_handler |
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| 561 | ); |
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| 562 | |
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| 563 | /* |
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| 564 | * _CPU_ISR_install_vector |
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| 565 | * |
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| 566 | * This routine installs an interrupt vector. |
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| 567 | */ |
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| 568 | |
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| 569 | void _CPU_ISR_install_vector( |
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| 570 | unsigned32 vector, |
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| 571 | proc_ptr new_handler, |
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| 572 | proc_ptr *old_handler |
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| 573 | ); |
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| 574 | |
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| 575 | /* |
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| 576 | * _CPU_Install_interrupt_stack |
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| 577 | * |
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| 578 | * This routine installs the hardware interrupt stack pointer. |
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| 579 | */ |
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| 580 | |
---|
| 581 | void _CPU_Install_interrupt_stack( void ); |
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| 582 | |
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| 583 | /* |
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| 584 | * _CPU_Context_switch |
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| 585 | * |
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| 586 | * This routine switches from the run context to the heir context. |
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| 587 | */ |
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| 588 | |
---|
| 589 | void _CPU_Context_switch( |
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| 590 | Context_Control *run, |
---|
| 591 | Context_Control *heir |
---|
| 592 | ); |
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| 593 | |
---|
| 594 | /* |
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| 595 | * _CPU_Context_save_fp |
---|
| 596 | * |
---|
| 597 | * This routine saves the floating point context passed to it. |
---|
| 598 | */ |
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| 599 | |
---|
| 600 | void _CPU_Context_save_fp( |
---|
| 601 | void **fp_context_ptr |
---|
| 602 | ); |
---|
| 603 | |
---|
| 604 | /* |
---|
| 605 | * _CPU_Context_restore_fp |
---|
| 606 | * |
---|
| 607 | * This routine restores the floating point context passed to it. |
---|
| 608 | */ |
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| 609 | |
---|
| 610 | void _CPU_Context_restore_fp( |
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| 611 | void **fp_context_ptr |
---|
| 612 | ); |
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| 613 | |
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| 614 | #if (M68K_HAS_FPSP_PACKAGE == 1) |
---|
| 615 | /* |
---|
| 616 | * Hooks for the Floating Point Support Package (FPSP) provided by Motorola |
---|
| 617 | * |
---|
| 618 | * NOTES: |
---|
| 619 | * |
---|
| 620 | * Motorola 68k family CPU's before the 68040 used a coprocessor |
---|
| 621 | * (68881 or 68882) to handle floating point. The 68040 has internal |
---|
| 622 | * floating point support -- but *not* the complete support provided by |
---|
| 623 | * the 68881 or 68882. The leftover functions are taken care of by the |
---|
| 624 | * M68040 Floating Point Support Package. Quoting from the MC68040 |
---|
| 625 | * Microprocessors User's Manual, Section 9, Floating-Point Unit (MC68040): |
---|
| 626 | * |
---|
| 627 | * "When used with the M68040FPSP, the MC68040 FPU is fully |
---|
| 628 | * compliant with IEEE floating-point standards." |
---|
| 629 | * |
---|
| 630 | * M68KFPSPInstallExceptionHandlers is in libcpu/m68k/MODEL/fpsp and |
---|
| 631 | * is invoked early in the application code to insure that proper FP |
---|
| 632 | * behavior is installed. This is not left to the BSP to call, since |
---|
| 633 | * this would force all applications using that BSP to use FPSP which |
---|
| 634 | * is not necessarily desirable. |
---|
| 635 | * |
---|
| 636 | * There is a similar package for the 68060 but RTEMS does not yet |
---|
| 637 | * support the 68060. |
---|
| 638 | */ |
---|
| 639 | |
---|
| 640 | void M68KFPSPInstallExceptionHandlers (void); |
---|
| 641 | |
---|
| 642 | SCORE_EXTERN int (*_FPSP_install_raw_handler)( |
---|
| 643 | unsigned32 vector, |
---|
| 644 | proc_ptr new_handler, |
---|
| 645 | proc_ptr *old_handler |
---|
| 646 | ); |
---|
| 647 | |
---|
| 648 | #endif |
---|
| 649 | |
---|
| 650 | |
---|
| 651 | #endif |
---|
| 652 | |
---|
| 653 | #ifdef __cplusplus |
---|
| 654 | } |
---|
| 655 | #endif |
---|
| 656 | |
---|
| 657 | #endif |
---|
| 658 | /* end of include file */ |
---|