[a911a77] | 1 | /** |
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[66fffc7] | 2 | * @file |
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| 3 | * |
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| 4 | * @brief Motorola M68K CPU Dependent Source |
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| 5 | * |
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| 6 | * This include file contains information pertaining to the Motorola |
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| 7 | * m68xxx processor family. |
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[a911a77] | 8 | */ |
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| 9 | |
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| 10 | /* |
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[186fee2] | 11 | * COPYRIGHT (c) 1989-2011. |
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[7908ba5b] | 12 | * On-Line Applications Research Corporation (OAR). |
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| 13 | * |
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| 14 | * The license and distribution terms for this file may be |
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| 15 | * found in the file LICENSE in this distribution or at |
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[05a98b7] | 16 | * http://www.rtems.com/license/LICENSE. |
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[7908ba5b] | 17 | */ |
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| 18 | |
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[7f70d1b7] | 19 | #ifndef _RTEMS_SCORE_CPU_H |
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| 20 | #define _RTEMS_SCORE_CPU_H |
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[7908ba5b] | 21 | |
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| 22 | #ifdef __cplusplus |
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| 23 | extern "C" { |
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| 24 | #endif |
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| 25 | |
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[89b85e51] | 26 | #include <rtems/score/types.h> |
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| 27 | #include <rtems/score/m68k.h> |
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[7908ba5b] | 28 | |
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| 29 | /* conditional compilation parameters */ |
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| 30 | |
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| 31 | #define CPU_INLINE_ENABLE_DISPATCH TRUE |
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| 32 | #define CPU_UNROLL_ENQUEUE_PRIORITY FALSE |
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| 33 | |
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[2fd427c] | 34 | /* |
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| 35 | * Does the CPU follow the simple vectored interrupt model? |
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| 36 | * |
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| 37 | * If TRUE, then RTEMS allocates the vector table it internally manages. |
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| 38 | * If FALSE, then the BSP is assumed to allocate and manage the vector |
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| 39 | * table |
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| 40 | * |
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| 41 | * M68K Specific Information: |
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| 42 | * |
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| 43 | * XXX document implementation including references if appropriate |
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| 44 | */ |
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| 45 | #define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE |
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| 46 | |
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[7908ba5b] | 47 | /* |
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| 48 | * Use the m68k's hardware interrupt stack support and have the |
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| 49 | * interrupt manager allocate the memory for it. |
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| 50 | */ |
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| 51 | |
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| 52 | #if ( M68K_HAS_SEPARATE_STACKS == 1) |
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| 53 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK 0 |
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| 54 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK 1 |
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| 55 | #else |
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| 56 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK 1 |
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| 57 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK 0 |
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| 58 | #endif |
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| 59 | #define CPU_ALLOCATE_INTERRUPT_STACK 1 |
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| 60 | |
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| 61 | /* |
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| 62 | * Does the RTEMS invoke the user's ISR with the vector number and |
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[5bb38e15] | 63 | * a pointer to the saved interrupt frame (1) or just the vector |
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[7908ba5b] | 64 | * number (0)? |
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| 65 | */ |
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| 66 | |
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| 67 | #define CPU_ISR_PASSES_FRAME_POINTER 0 |
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| 68 | |
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| 69 | /* |
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| 70 | * Some family members have no FP, some have an FPU such as the |
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| 71 | * MC68881/MC68882 for the MC68020, others have it built in (MC68030, 040). |
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| 72 | * |
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| 73 | * NOTE: If on a CPU without hardware FP, then one can use software |
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| 74 | * emulation. The gcc software FP emulation code has data which |
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| 75 | * must be contexted switched on a per task basis. |
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| 76 | */ |
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| 77 | |
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[3b7e9bc] | 78 | #if ( M68K_HAS_FPU == 1 ) || ( M68K_HAS_EMAC == 1 ) |
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| 79 | #define CPU_HARDWARE_FP TRUE |
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| 80 | #define CPU_SOFTWARE_FP FALSE |
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[7908ba5b] | 81 | #else |
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[3b7e9bc] | 82 | #define CPU_HARDWARE_FP FALSE |
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| 83 | #if defined( __GNUC__ ) |
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| 84 | #define CPU_SOFTWARE_FP TRUE |
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| 85 | #else |
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| 86 | #define CPU_SOFTWARE_FP FALSE |
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| 87 | #endif |
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[7908ba5b] | 88 | #endif |
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| 89 | |
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| 90 | /* |
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| 91 | * All tasks are not by default floating point tasks on this CPU. |
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| 92 | * The IDLE task does not have a floating point context on this CPU. |
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| 93 | * It is safe to use the deferred floating point context switch |
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| 94 | * algorithm on this CPU. |
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| 95 | */ |
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| 96 | |
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| 97 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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| 98 | #define CPU_IDLE_TASK_IS_FP FALSE |
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| 99 | #define CPU_USE_DEFERRED_FP_SWITCH TRUE |
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| 100 | |
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[8e0738e1] | 101 | #define CPU_PROVIDES_IDLE_THREAD_BODY TRUE |
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[7908ba5b] | 102 | #define CPU_STACK_GROWS_UP FALSE |
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[15fef93] | 103 | #define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (4))) |
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[7908ba5b] | 104 | |
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[9c121991] | 105 | #define CPU_TIMESTAMP_USE_INT64_INLINE TRUE |
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| 106 | |
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[7908ba5b] | 107 | /* |
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| 108 | * Define what is required to specify how the network to host conversion |
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| 109 | * routines are handled. |
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| 110 | */ |
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| 111 | |
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| 112 | #define CPU_BIG_ENDIAN TRUE |
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| 113 | #define CPU_LITTLE_ENDIAN FALSE |
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| 114 | |
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[da42259] | 115 | #if ( CPU_HARDWARE_FP == TRUE ) && !defined( __mcoldfire__ ) |
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| 116 | #if defined( __mc68060__ ) |
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| 117 | #define M68K_FP_STATE_SIZE 16 |
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| 118 | #else |
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| 119 | #define M68K_FP_STATE_SIZE 216 |
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| 120 | #endif |
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| 121 | #endif |
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| 122 | |
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[7908ba5b] | 123 | #ifndef ASM |
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[3b7e9bc] | 124 | |
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[7908ba5b] | 125 | /* structures */ |
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| 126 | |
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| 127 | /* |
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| 128 | * Basic integer context for the m68k family. |
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| 129 | */ |
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| 130 | |
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| 131 | typedef struct { |
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[d86bae8] | 132 | uint32_t sr; /* (sr) status register */ |
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| 133 | uint32_t d2; /* (d2) data register 2 */ |
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| 134 | uint32_t d3; /* (d3) data register 3 */ |
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| 135 | uint32_t d4; /* (d4) data register 4 */ |
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| 136 | uint32_t d5; /* (d5) data register 5 */ |
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| 137 | uint32_t d6; /* (d6) data register 6 */ |
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| 138 | uint32_t d7; /* (d7) data register 7 */ |
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[7908ba5b] | 139 | void *a2; /* (a2) address register 2 */ |
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| 140 | void *a3; /* (a3) address register 3 */ |
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| 141 | void *a4; /* (a4) address register 4 */ |
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| 142 | void *a5; /* (a5) address register 5 */ |
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| 143 | void *a6; /* (a6) address register 6 */ |
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| 144 | void *a7_msp; /* (a7) master stack pointer */ |
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[3b7e9bc] | 145 | #if defined( __mcoldfire__ ) && ( M68K_HAS_FPU == 1 ) |
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| 146 | uint8_t fpu_dis; |
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| 147 | #endif |
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| 148 | } Context_Control; |
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[7908ba5b] | 149 | |
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[0ca6d0d9] | 150 | #define _CPU_Context_Get_SP( _context ) \ |
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| 151 | (_context)->a7_msp |
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| 152 | |
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[7908ba5b] | 153 | /* |
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[3b7e9bc] | 154 | * Floating point context areas and support routines |
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[7908ba5b] | 155 | */ |
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| 156 | |
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[3b7e9bc] | 157 | #if ( CPU_SOFTWARE_FP == TRUE ) |
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| 158 | /* |
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| 159 | * This is the same as gcc's view of the software FP condition code |
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| 160 | * register _fpCCR. The implementation of the emulation code is |
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| 161 | * in the gcc-VERSION/config/m68k directory. This structure is |
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| 162 | * correct as of gcc 2.7.2.2. |
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| 163 | */ |
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| 164 | typedef struct { |
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| 165 | uint16_t _exception_bits; |
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| 166 | uint16_t _trap_enable_bits; |
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| 167 | uint16_t _sticky_bits; |
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| 168 | uint16_t _rounding_mode; |
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| 169 | uint16_t _format; |
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| 170 | uint16_t _last_operation; |
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| 171 | union { |
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| 172 | float sf; |
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| 173 | double df; |
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| 174 | } _operand1; |
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| 175 | union { |
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| 176 | float sf; |
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| 177 | double df; |
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| 178 | } _operand2; |
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| 179 | } Context_Control_fp; |
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| 180 | |
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| 181 | /* |
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| 182 | * This software FP implementation is only for GCC. |
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| 183 | */ |
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| 184 | #define _CPU_Context_Fp_start( _base, _offset ) \ |
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| 185 | ((void *) _Addresses_Add_offset( (_base), (_offset) ) ) |
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| 186 | |
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| 187 | #define _CPU_Context_Initialize_fp( _fp_area ) \ |
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| 188 | { \ |
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| 189 | Context_Control_fp *_fp; \ |
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| 190 | _fp = *(Context_Control_fp **)_fp_area; \ |
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| 191 | _fp->_exception_bits = 0; \ |
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| 192 | _fp->_trap_enable_bits = 0; \ |
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| 193 | _fp->_sticky_bits = 0; \ |
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| 194 | _fp->_rounding_mode = 0; /* ROUND_TO_NEAREST */ \ |
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| 195 | _fp->_format = 0; /* NIL */ \ |
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| 196 | _fp->_last_operation = 0; /* NOOP */ \ |
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| 197 | _fp->_operand1.df = 0; \ |
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| 198 | _fp->_operand2.df = 0; \ |
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| 199 | } |
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[e0b8176] | 200 | #endif |
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| 201 | |
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[3b7e9bc] | 202 | #if ( CPU_HARDWARE_FP == TRUE ) |
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| 203 | #if defined( __mcoldfire__ ) |
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| 204 | /* We need memset() to initialize the FP context */ |
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| 205 | #include <string.h> |
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| 206 | |
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| 207 | #if ( M68K_HAS_FPU == 1 ) |
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| 208 | /* |
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| 209 | * The Cache Control Register (CACR) has write-only access. It is also |
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| 210 | * used to enable and disable the FPU. We need to maintain a copy of |
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| 211 | * this register to allow per thread values. |
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| 212 | */ |
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| 213 | extern uint32_t _CPU_cacr_shadow; |
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| 214 | #endif |
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| 215 | |
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| 216 | /* We assume that each ColdFire core with a FPU has also an EMAC unit */ |
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| 217 | typedef struct { |
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| 218 | uint32_t emac_macsr; |
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| 219 | uint32_t emac_acc0; |
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| 220 | uint32_t emac_acc1; |
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| 221 | uint32_t emac_acc2; |
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| 222 | uint32_t emac_acc3; |
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| 223 | uint32_t emac_accext01; |
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| 224 | uint32_t emac_accext23; |
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| 225 | uint32_t emac_mask; |
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| 226 | #if ( M68K_HAS_FPU == 1 ) |
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| 227 | uint16_t fp_state_format; |
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| 228 | uint16_t fp_state_fpcr; |
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| 229 | double fp_state_op; |
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| 230 | uint32_t fp_state_fpsr; |
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| 231 | |
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| 232 | /* |
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| 233 | * We need to save the FP Instruction Address Register (FPIAR), because |
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| 234 | * a context switch can occur within a FP exception before the handler |
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| 235 | * was able to save this register. |
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| 236 | */ |
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| 237 | uint32_t fp_fpiar; |
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| 238 | |
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| 239 | double fp_data [8]; |
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| 240 | #endif |
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| 241 | } Context_Control_fp; |
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| 242 | |
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| 243 | #define _CPU_Context_Fp_start( _base, _offset ) \ |
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| 244 | ((void *) _Addresses_Add_offset( (_base), (_offset) )) |
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| 245 | |
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| 246 | /* |
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| 247 | * The reset value for all context relevant registers except the FP data |
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| 248 | * registers is zero. The reset value of the FP data register is NAN. The |
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| 249 | * restore of the reset FP state will reset the FP data registers, so the |
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| 250 | * initial value of them can be arbitrary here. |
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| 251 | */ |
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| 252 | #define _CPU_Context_Initialize_fp( _fp_area ) \ |
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| 253 | memset( *(_fp_area), 0, sizeof( Context_Control_fp ) ) |
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| 254 | #else |
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| 255 | /* |
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[4bcd8dc] | 256 | * FP context save area for the M68881/M68882 and 68060 numeric |
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| 257 | * coprocessors. |
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[3b7e9bc] | 258 | */ |
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| 259 | typedef struct { |
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| 260 | /* |
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| 261 | * M68K_FP_STATE_SIZE bytes for FSAVE/FRESTORE |
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| 262 | * 96 bytes for FMOVEM FP0-7 |
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| 263 | * 12 bytes for FMOVEM CREGS |
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| 264 | * 4 bytes for non-null flag |
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| 265 | */ |
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| 266 | uint8_t fp_save_area [M68K_FP_STATE_SIZE + 112]; |
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| 267 | } Context_Control_fp; |
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| 268 | |
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| 269 | #define _CPU_Context_Fp_start( _base, _offset ) \ |
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| 270 | ( \ |
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| 271 | (void *) _Addresses_Add_offset( \ |
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| 272 | (_base), \ |
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| 273 | (_offset) + CPU_CONTEXT_FP_SIZE - 4 \ |
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| 274 | ) \ |
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| 275 | ) |
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| 276 | |
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| 277 | #define _CPU_Context_Initialize_fp( _fp_area ) \ |
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| 278 | { \ |
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| 279 | uint32_t *_fp_context = (uint32_t *)*(_fp_area); \ |
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| 280 | *(--(_fp_context)) = 0; \ |
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| 281 | *(_fp_area) = (void *)(_fp_context); \ |
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| 282 | } |
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[da42259] | 283 | #endif |
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[7908ba5b] | 284 | #endif |
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| 285 | |
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| 286 | /* |
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[e090b7e] | 287 | * The following structures define the set of information saved |
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| 288 | * on the current stack by RTEMS upon receipt of each exc/interrupt. |
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| 289 | * These are not used by m68k handlers. |
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| 290 | * The exception frame is for rdbg. |
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[7908ba5b] | 291 | */ |
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| 292 | |
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| 293 | typedef struct { |
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[d86bae8] | 294 | uint32_t vecnum; /* vector number */ |
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[7908ba5b] | 295 | } CPU_Interrupt_frame; |
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| 296 | |
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[e090b7e] | 297 | typedef struct { |
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[d86bae8] | 298 | uint32_t vecnum; /* vector number */ |
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| 299 | uint32_t sr; /* status register */ |
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| 300 | uint32_t pc; /* program counter */ |
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| 301 | uint32_t d0, d1, d2, d3, d4, d5, d6, d7; |
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| 302 | uint32_t a0, a1, a2, a3, a4, a5, a6, a7; |
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[e090b7e] | 303 | } CPU_Exception_frame; |
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| 304 | |
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[7908ba5b] | 305 | /* variables */ |
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| 306 | |
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[5bb38e15] | 307 | extern void* _VBR; |
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[7908ba5b] | 308 | |
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| 309 | #if ( M68K_HAS_VBR == 0 ) |
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| 310 | |
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| 311 | /* |
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| 312 | * Table of ISR handler entries that resides in RAM. The FORMAT/ID is |
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| 313 | * pushed onto the stack. This is not is the same order as VBR processors. |
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| 314 | * The ISR handler takes the format and uses it for dispatching the user |
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| 315 | * handler. |
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| 316 | * |
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| 317 | * FIXME : should be moved to below CPU_INTERRUPT_NUMBER_OF_VECTORS |
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| 318 | * |
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| 319 | */ |
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| 320 | |
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| 321 | typedef struct { |
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[d86bae8] | 322 | uint16_t move_a7; /* move #FORMAT_ID,%a7@- */ |
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| 323 | uint16_t format_id; |
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| 324 | uint16_t jmp; /* jmp _ISR_Handlers */ |
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| 325 | uint32_t isr_handler; |
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[7908ba5b] | 326 | } _CPU_ISR_handler_entry; |
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| 327 | |
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| 328 | #define M68K_MOVE_A7 0x3F3C |
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| 329 | #define M68K_JMP 0x4EF9 |
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| 330 | |
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| 331 | /* points to jsr-exception-table in targets wo/ VBR register */ |
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[5bb38e15] | 332 | SCORE_EXTERN _CPU_ISR_handler_entry _CPU_ISR_jump_table[256]; |
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[7908ba5b] | 333 | |
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| 334 | #endif /* M68K_HAS_VBR */ |
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[3b7e9bc] | 335 | |
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[7908ba5b] | 336 | #endif /* ASM */ |
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| 337 | |
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| 338 | /* constants */ |
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| 339 | |
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| 340 | /* |
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| 341 | * This defines the number of levels and the mask used to pick those |
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| 342 | * bits out of a thread mode. |
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| 343 | */ |
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| 344 | |
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| 345 | #define CPU_MODES_INTERRUPT_LEVEL 0x00000007 /* interrupt level in mode */ |
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| 346 | #define CPU_MODES_INTERRUPT_MASK 0x00000007 /* interrupt level in mode */ |
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| 347 | |
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| 348 | /* |
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| 349 | * context size area for floating point |
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| 350 | */ |
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| 351 | |
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| 352 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
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| 353 | |
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| 354 | /* |
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| 355 | * extra stack required by the MPCI receive server thread |
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| 356 | */ |
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| 357 | |
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| 358 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 |
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| 359 | |
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| 360 | /* |
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| 361 | * m68k family supports 256 distinct vectors. |
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| 362 | */ |
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| 363 | |
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| 364 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 |
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| 365 | #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) |
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| 366 | |
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[4db30283] | 367 | /* |
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| 368 | * This is defined if the port has a special way to report the ISR nesting |
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| 369 | * level. Most ports maintain the variable _ISR_Nest_level. |
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| 370 | */ |
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| 371 | |
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| 372 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
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| 373 | |
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[7908ba5b] | 374 | /* |
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| 375 | * Minimum size of a thread's stack. |
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| 376 | */ |
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| 377 | |
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[e339d8b] | 378 | #define CPU_STACK_MINIMUM_SIZE M68K_CPU_STACK_MINIMUM_SIZE |
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| 379 | |
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| 380 | /* |
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| 381 | * Maximum priority of a thread. Note based from 0 which is the idle task. |
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| 382 | */ |
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| 383 | #define CPU_PRIORITY_MAXIMUM M68K_CPU_PRIORITY_MAXIMUM |
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[7908ba5b] | 384 | |
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[f1738ed] | 385 | #define CPU_SIZEOF_POINTER 4 |
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| 386 | |
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[7908ba5b] | 387 | /* |
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| 388 | * m68k is pretty tolerant of alignment. Just put things on 4 byte boundaries. |
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| 389 | */ |
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| 390 | |
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| 391 | #define CPU_ALIGNMENT 4 |
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| 392 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
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| 393 | #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT |
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| 394 | |
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| 395 | /* |
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| 396 | * On m68k thread stacks require no further alignment after allocation |
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| 397 | * from the Workspace. |
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| 398 | */ |
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| 399 | |
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| 400 | #define CPU_STACK_ALIGNMENT 0 |
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| 401 | |
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| 402 | #ifndef ASM |
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| 403 | |
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| 404 | /* macros */ |
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| 405 | |
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| 406 | /* |
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| 407 | * ISR handler macros |
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| 408 | * |
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| 409 | * These macros perform the following functions: |
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[fe7acdcf] | 410 | * + initialize the RTEMS vector table |
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[7908ba5b] | 411 | * + disable all maskable CPU interrupts |
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| 412 | * + restore previous interrupt level (enable) |
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| 413 | * + temporarily restore interrupts (flash) |
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| 414 | * + set a particular level |
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| 415 | */ |
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| 416 | |
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[fe7acdcf] | 417 | #define _CPU_Initialize_vectors() |
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| 418 | |
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[7908ba5b] | 419 | #define _CPU_ISR_Disable( _level ) \ |
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| 420 | m68k_disable_interrupts( _level ) |
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| 421 | |
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| 422 | #define _CPU_ISR_Enable( _level ) \ |
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| 423 | m68k_enable_interrupts( _level ) |
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| 424 | |
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| 425 | #define _CPU_ISR_Flash( _level ) \ |
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| 426 | m68k_flash_interrupts( _level ) |
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| 427 | |
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| 428 | #define _CPU_ISR_Set_level( _newlevel ) \ |
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| 429 | m68k_set_interrupt_level( _newlevel ) |
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| 430 | |
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[d86bae8] | 431 | uint32_t _CPU_ISR_Get_level( void ); |
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[7908ba5b] | 432 | |
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| 433 | /* end of ISR handler macros */ |
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| 434 | |
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| 435 | /* |
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| 436 | * Context handler macros |
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| 437 | * |
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| 438 | * These macros perform the following functions: |
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| 439 | * + initialize a context area |
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| 440 | * + restart the current thread |
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| 441 | * + calculate the initial pointer into a FP context area |
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| 442 | * + initialize an FP context area |
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| 443 | */ |
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| 444 | |
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[e0b8176] | 445 | #if (defined(__mcoldfire__) && ( M68K_HAS_FPU == 1 )) |
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[7908ba5b] | 446 | #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ |
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| 447 | _isr, _entry_point, _is_fp ) \ |
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| 448 | do { \ |
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[d86bae8] | 449 | uint32_t _stack; \ |
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[7908ba5b] | 450 | \ |
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| 451 | (_the_context)->sr = 0x3000 | ((_isr) << 8); \ |
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[edb1810e] | 452 | _stack = (uint32_t)(_stack_base) + (_size) - 4; \ |
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[7908ba5b] | 453 | (_the_context)->a7_msp = (void *)_stack; \ |
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| 454 | *(void **)_stack = (void *)(_entry_point); \ |
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[e0b8176] | 455 | (_the_context)->fpu_dis = (_is_fp == TRUE) ? 0x00 : 0x10; \ |
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[7908ba5b] | 456 | } while ( 0 ) |
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[e0b8176] | 457 | #else |
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| 458 | #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ |
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| 459 | _isr, _entry_point, _is_fp ) \ |
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| 460 | do { \ |
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| 461 | uint32_t _stack; \ |
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| 462 | \ |
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| 463 | (_the_context)->sr = 0x3000 | ((_isr) << 8); \ |
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[186fee2] | 464 | _stack = (uint32_t)(_stack_base) + (_size) - 4; \ |
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[e0b8176] | 465 | (_the_context)->a7_msp = (void *)_stack; \ |
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| 466 | *(void **)_stack = (void *)(_entry_point); \ |
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| 467 | } while ( 0 ) |
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| 468 | #endif |
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[7908ba5b] | 469 | |
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| 470 | /* end of Context handler macros */ |
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| 471 | |
---|
[8e0738e1] | 472 | /* |
---|
| 473 | * _CPU_Thread_Idle_body |
---|
| 474 | * |
---|
| 475 | * This routine is the CPU dependent IDLE thread body. |
---|
| 476 | * |
---|
| 477 | * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY |
---|
| 478 | * is TRUE. |
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| 479 | */ |
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| 480 | |
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[59b68bd] | 481 | void *_CPU_Thread_Idle_body( uintptr_t ignored ); |
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[8e0738e1] | 482 | |
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[7908ba5b] | 483 | /* |
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| 484 | * Fatal Error manager macros |
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| 485 | * |
---|
| 486 | * These macros perform the following functions: |
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| 487 | * + disable interrupts and halt the CPU |
---|
| 488 | */ |
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| 489 | |
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[97c73ed] | 490 | #if ( defined(__mcoldfire__) ) |
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[7908ba5b] | 491 | #define _CPU_Fatal_halt( _error ) \ |
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[0e900873] | 492 | { __asm__ volatile( "move.w %%sr,%%d0\n\t" \ |
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[7908ba5b] | 493 | "or.l %2,%%d0\n\t" \ |
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| 494 | "move.w %%d0,%%sr\n\t" \ |
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| 495 | "move.l %1,%%d0\n\t" \ |
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| 496 | "move.l #0xDEADBEEF,%%d1\n\t" \ |
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| 497 | "halt" \ |
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| 498 | : "=g" (_error) \ |
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| 499 | : "0" (_error), "d"(0x0700) \ |
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| 500 | : "d0", "d1" ); \ |
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| 501 | } |
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| 502 | #else |
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| 503 | #define _CPU_Fatal_halt( _error ) \ |
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[0e900873] | 504 | { __asm__ volatile( "movl %0,%%d0; " \ |
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[7908ba5b] | 505 | "orw #0x0700,%%sr; " \ |
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| 506 | "stop #0x2700" : "=d" ((_error)) : "0" ((_error)) ); \ |
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| 507 | } |
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| 508 | #endif |
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| 509 | |
---|
| 510 | /* end of Fatal Error manager macros */ |
---|
| 511 | |
---|
| 512 | /* |
---|
| 513 | * Bitfield handler macros |
---|
| 514 | * |
---|
| 515 | * These macros perform the following functions: |
---|
| 516 | * + scan for the highest numbered (MSB) set in a 16 bit bitfield |
---|
| 517 | * |
---|
| 518 | * NOTE: |
---|
| 519 | * |
---|
| 520 | * It appears that on the M68020 bitfield are always 32 bits wide |
---|
| 521 | * when in a register. This code forces the bitfield to be in |
---|
| 522 | * memory (it really always is anyway). This allows us to |
---|
| 523 | * have a real 16 bit wide bitfield which operates "correctly." |
---|
| 524 | */ |
---|
| 525 | |
---|
| 526 | #define CPU_USE_GENERIC_BITFIELD_CODE FALSE |
---|
| 527 | #define CPU_USE_GENERIC_BITFIELD_DATA FALSE |
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| 528 | |
---|
[60a3fa0c] | 529 | #if ( M68K_HAS_BFFFO != 1 ) |
---|
| 530 | /* |
---|
| 531 | * Lookup table for BFFFO simulation |
---|
| 532 | */ |
---|
| 533 | extern const unsigned char _CPU_m68k_BFFFO_table[256]; |
---|
| 534 | #endif |
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| 535 | |
---|
[7908ba5b] | 536 | #if ( M68K_HAS_BFFFO == 1 ) |
---|
| 537 | |
---|
| 538 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
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[0e900873] | 539 | __asm__ volatile( "bfffo (%1),#0,#16,%0" : "=d" (_output) : "a" (&_value)); |
---|
[7908ba5b] | 540 | |
---|
[e339d8b] | 541 | #elif ( __mcfisaaplus__ ) |
---|
[fa9fa1e4] | 542 | /* This is simplified by the fact that RTEMS never calls it with _value=0 */ |
---|
| 543 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
---|
[0e900873] | 544 | __asm__ volatile ( \ |
---|
[fa9fa1e4] | 545 | " swap %0\n" \ |
---|
| 546 | " ff1.l %0\n" \ |
---|
| 547 | : "=d" ((_output)) \ |
---|
| 548 | : "0" ((_value)) \ |
---|
| 549 | : "cc" ) ; |
---|
| 550 | |
---|
| 551 | #else |
---|
[7908ba5b] | 552 | /* duplicates BFFFO results for 16 bits (i.e., 15-(_priority) in |
---|
| 553 | _CPU_Priority_bits_index is not needed), handles the 0 case, and |
---|
| 554 | does not molest _value -- jsg */ |
---|
[97c73ed] | 555 | #if ( defined(__mcoldfire__) ) |
---|
[60a3fa0c] | 556 | |
---|
[7908ba5b] | 557 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
---|
| 558 | { \ |
---|
| 559 | register int dumby; \ |
---|
| 560 | \ |
---|
[0e900873] | 561 | __asm__ volatile ( \ |
---|
[7908ba5b] | 562 | " clr.l %1\n" \ |
---|
| 563 | " move.w %2,%1\n" \ |
---|
| 564 | " lsr.l #8,%1\n" \ |
---|
| 565 | " beq.s 1f\n" \ |
---|
| 566 | " move.b (%3,%1),%0\n" \ |
---|
| 567 | " bra.s 0f\n" \ |
---|
| 568 | "1: move.w %2,%1\n" \ |
---|
| 569 | " move.b (%3,%1),%0\n" \ |
---|
| 570 | " addq.l #8,%0\n" \ |
---|
| 571 | "0: and.l #0xff,%0\n" \ |
---|
| 572 | : "=&d" ((_output)), "=&d" ((dumby)) \ |
---|
[60a3fa0c] | 573 | : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \ |
---|
[7908ba5b] | 574 | : "cc" ) ; \ |
---|
| 575 | } |
---|
| 576 | #elif ( M68K_HAS_EXTB_L == 1 ) |
---|
| 577 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
---|
| 578 | { \ |
---|
| 579 | register int dumby; \ |
---|
| 580 | \ |
---|
[0e900873] | 581 | __asm__ volatile ( " move.w %2,%1\n" \ |
---|
[7908ba5b] | 582 | " lsr.w #8,%1\n" \ |
---|
| 583 | " beq.s 1f\n" \ |
---|
| 584 | " move.b (%3,%1.w),%0\n" \ |
---|
| 585 | " extb.l %0\n" \ |
---|
| 586 | " bra.s 0f\n" \ |
---|
| 587 | "1: moveq.l #8,%0\n" \ |
---|
| 588 | " add.b (%3,%2.w),%0\n" \ |
---|
| 589 | "0:\n" \ |
---|
| 590 | : "=&d" ((_output)), "=&d" ((dumby)) \ |
---|
[60a3fa0c] | 591 | : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \ |
---|
[7908ba5b] | 592 | : "cc" ) ; \ |
---|
| 593 | } |
---|
| 594 | #else |
---|
| 595 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
---|
| 596 | { \ |
---|
| 597 | register int dumby; \ |
---|
| 598 | \ |
---|
[0e900873] | 599 | __asm__ volatile ( " move.w %2,%1\n" \ |
---|
[7908ba5b] | 600 | " lsr.w #8,%1\n" \ |
---|
| 601 | " beq.s 1f\n" \ |
---|
| 602 | " move.b (%3,%1.w),%0\n" \ |
---|
| 603 | " and.l #0x000000ff,%0\n"\ |
---|
| 604 | " bra.s 0f\n" \ |
---|
| 605 | "1: moveq.l #8,%0\n" \ |
---|
| 606 | " add.b (%3,%2.w),%0\n" \ |
---|
| 607 | "0:\n" \ |
---|
| 608 | : "=&d" ((_output)), "=&d" ((dumby)) \ |
---|
[60a3fa0c] | 609 | : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \ |
---|
[7908ba5b] | 610 | : "cc" ) ; \ |
---|
| 611 | } |
---|
| 612 | #endif |
---|
| 613 | |
---|
| 614 | #endif |
---|
| 615 | |
---|
| 616 | /* end of Bitfield handler macros */ |
---|
| 617 | |
---|
| 618 | /* |
---|
| 619 | * Priority handler macros |
---|
| 620 | * |
---|
| 621 | * These macros perform the following functions: |
---|
| 622 | * + return a mask with the bit for this major/minor portion of |
---|
| 623 | * of thread priority set. |
---|
| 624 | * + translate the bit number returned by "Bitfield_find_first_bit" |
---|
| 625 | * into an index into the thread ready chain bit maps |
---|
| 626 | */ |
---|
| 627 | |
---|
| 628 | #define _CPU_Priority_Mask( _bit_number ) \ |
---|
| 629 | ( 0x8000 >> (_bit_number) ) |
---|
| 630 | |
---|
| 631 | #define _CPU_Priority_bits_index( _priority ) \ |
---|
| 632 | (_priority) |
---|
| 633 | |
---|
| 634 | /* end of Priority handler macros */ |
---|
| 635 | |
---|
| 636 | /* functions */ |
---|
| 637 | |
---|
| 638 | /* |
---|
| 639 | * _CPU_Initialize |
---|
| 640 | * |
---|
| 641 | * This routine performs CPU dependent initialization. |
---|
| 642 | */ |
---|
| 643 | |
---|
[c03e2bc] | 644 | void _CPU_Initialize(void); |
---|
[7908ba5b] | 645 | |
---|
| 646 | /* |
---|
| 647 | * _CPU_ISR_install_raw_handler |
---|
| 648 | * |
---|
[5bb38e15] | 649 | * This routine installs a "raw" interrupt handler directly into the |
---|
[7908ba5b] | 650 | * processor's vector table. |
---|
| 651 | */ |
---|
[5bb38e15] | 652 | |
---|
[7908ba5b] | 653 | void _CPU_ISR_install_raw_handler( |
---|
[d86bae8] | 654 | uint32_t vector, |
---|
[7908ba5b] | 655 | proc_ptr new_handler, |
---|
| 656 | proc_ptr *old_handler |
---|
| 657 | ); |
---|
| 658 | |
---|
| 659 | /* |
---|
| 660 | * _CPU_ISR_install_vector |
---|
| 661 | * |
---|
| 662 | * This routine installs an interrupt vector. |
---|
| 663 | */ |
---|
| 664 | |
---|
| 665 | void _CPU_ISR_install_vector( |
---|
[d86bae8] | 666 | uint32_t vector, |
---|
[7908ba5b] | 667 | proc_ptr new_handler, |
---|
| 668 | proc_ptr *old_handler |
---|
| 669 | ); |
---|
| 670 | |
---|
| 671 | /* |
---|
| 672 | * _CPU_Install_interrupt_stack |
---|
| 673 | * |
---|
| 674 | * This routine installs the hardware interrupt stack pointer. |
---|
| 675 | */ |
---|
| 676 | |
---|
| 677 | void _CPU_Install_interrupt_stack( void ); |
---|
| 678 | |
---|
| 679 | /* |
---|
| 680 | * _CPU_Context_switch |
---|
| 681 | * |
---|
| 682 | * This routine switches from the run context to the heir context. |
---|
| 683 | */ |
---|
| 684 | |
---|
| 685 | void _CPU_Context_switch( |
---|
| 686 | Context_Control *run, |
---|
| 687 | Context_Control *heir |
---|
| 688 | ); |
---|
| 689 | |
---|
[4ad55267] | 690 | void _CPU_Context_Restart_self( |
---|
| 691 | Context_Control *the_context |
---|
| 692 | ); |
---|
| 693 | |
---|
[7908ba5b] | 694 | /* |
---|
| 695 | * _CPU_Context_save_fp |
---|
| 696 | * |
---|
| 697 | * This routine saves the floating point context passed to it. |
---|
| 698 | */ |
---|
| 699 | |
---|
| 700 | void _CPU_Context_save_fp( |
---|
[14865ec7] | 701 | Context_Control_fp **fp_context_ptr |
---|
[7908ba5b] | 702 | ); |
---|
| 703 | |
---|
| 704 | /* |
---|
| 705 | * _CPU_Context_restore_fp |
---|
| 706 | * |
---|
| 707 | * This routine restores the floating point context passed to it. |
---|
| 708 | */ |
---|
| 709 | |
---|
| 710 | void _CPU_Context_restore_fp( |
---|
[14865ec7] | 711 | Context_Control_fp **fp_context_ptr |
---|
[7908ba5b] | 712 | ); |
---|
| 713 | |
---|
[4bcd8dc] | 714 | /** |
---|
| 715 | * This method prints the CPU exception frame. |
---|
| 716 | * |
---|
| 717 | * @param[in] frame points to the frame to be printed |
---|
| 718 | */ |
---|
| 719 | void _CPU_Exception_frame_print( |
---|
| 720 | const CPU_Exception_frame *frame |
---|
| 721 | ); |
---|
[815994f] | 722 | |
---|
[7908ba5b] | 723 | #if (M68K_HAS_FPSP_PACKAGE == 1) |
---|
| 724 | /* |
---|
| 725 | * Hooks for the Floating Point Support Package (FPSP) provided by Motorola |
---|
| 726 | * |
---|
[5bb38e15] | 727 | * NOTES: |
---|
[7908ba5b] | 728 | * |
---|
| 729 | * Motorola 68k family CPU's before the 68040 used a coprocessor |
---|
| 730 | * (68881 or 68882) to handle floating point. The 68040 has internal |
---|
| 731 | * floating point support -- but *not* the complete support provided by |
---|
| 732 | * the 68881 or 68882. The leftover functions are taken care of by the |
---|
| 733 | * M68040 Floating Point Support Package. Quoting from the MC68040 |
---|
| 734 | * Microprocessors User's Manual, Section 9, Floating-Point Unit (MC68040): |
---|
| 735 | * |
---|
| 736 | * "When used with the M68040FPSP, the MC68040 FPU is fully |
---|
| 737 | * compliant with IEEE floating-point standards." |
---|
| 738 | * |
---|
| 739 | * M68KFPSPInstallExceptionHandlers is in libcpu/m68k/MODEL/fpsp and |
---|
[ece004d] | 740 | * is invoked early in the application code to ensure that proper FP |
---|
[7908ba5b] | 741 | * behavior is installed. This is not left to the BSP to call, since |
---|
| 742 | * this would force all applications using that BSP to use FPSP which |
---|
| 743 | * is not necessarily desirable. |
---|
| 744 | * |
---|
| 745 | * There is a similar package for the 68060 but RTEMS does not yet |
---|
| 746 | * support the 68060. |
---|
| 747 | */ |
---|
| 748 | |
---|
| 749 | void M68KFPSPInstallExceptionHandlers (void); |
---|
| 750 | |
---|
| 751 | SCORE_EXTERN int (*_FPSP_install_raw_handler)( |
---|
[d86bae8] | 752 | uint32_t vector, |
---|
[7908ba5b] | 753 | proc_ptr new_handler, |
---|
| 754 | proc_ptr *old_handler |
---|
| 755 | ); |
---|
| 756 | |
---|
| 757 | #endif |
---|
| 758 | |
---|
| 759 | |
---|
| 760 | #endif |
---|
| 761 | |
---|
| 762 | #ifdef __cplusplus |
---|
| 763 | } |
---|
| 764 | #endif |
---|
| 765 | |
---|
| 766 | #endif |
---|