source: rtems/cpukit/score/cpu/m68k/rtems/m68k/sim.h @ fa6b0f5

4.104.114.84.95
Last change on this file since fa6b0f5 was fa6b0f5, checked in by Ralf Corsepius <ralf.corsepius@…>, on Feb 4, 2005 at 5:36:20 AM

2005-02-04 Ralf Corsepius <ralf.corsepius@…>

  • rtems/m68k/m68302.h, rtems/m68k/m68360.h, rtems/m68k/qsm.h, rtems/m68k/sim.h, rtems/score/m68k.h: Header guards cleanup.
  • Property mode set to 100644
File size: 11.7 KB
Line 
1/*
2 *-------------------------------------------------------------------
3 *
4 *   SIM -- System Integration Module
5 *
6 * The system integration module (SIM) is used on many Motorola 16-
7 * and 32-bit MCUs for the following functions:
8 *
9 *  () System configuration and protection. Bus and software watchdog
10 *  monitors are provided in addition to periodic interrupt generators.
11 *
12 *  () Clock signal generation for other intermodule bus (IMB) members
13 *  and external devices.
14 *
15 *  () The generation of chip-select signals that simplify external
16 *  circuitry interface.
17 *
18 *  () Data ports that are available for general purpose input and
19 *  output.
20 *
21 *  () A system test block that is intended only for factory tests.
22 *
23 * For more information, refer to Motorola's "Modular Microcontroller
24 * Family System Integration Module Reference Manual" (Motorola document
25 * SIMRM/AD).
26 *
27 * This file was created by John S. Gwynne to support Motorola's 68332 MCU.
28 *
29 * Redistribution and use in source and binary forms are permitted
30 * provided that the following conditions are met:
31 * 1. Redistribution of source code and documentation must retain
32 *    the above authorship, this list of conditions and the
33 *    following disclaimer.
34 * 2. The name of the author may not be used to endorse or promote
35 *    products derived from this software without specific prior
36 *    written permission.
37 *
38 * This software is provided "AS IS" without warranty of any kind,
39 * either expressed or implied, including, but not limited to, the
40 * implied warranties of merchantability, title and fitness for a
41 * particular purpose.
42 *
43 *------------------------------------------------------------------
44 *
45 *  $Id$
46 */
47
48#ifndef _RTEMS_M68K_SIM_H
49#define _RTEMS_M68K_SIM_H
50
51
52/* SAM-- shift and mask */
53#undef  SAM
54#define SAM(a,b,c) ((a << b) & c)
55
56/*
57 *  These macros make this file usable from assembly.
58 */
59
60#ifdef ASM
61#define SIM_VOLATILE_USHORT_POINTER
62#define SIM_VOLATILE_UCHAR_POINTER
63#else
64#define SIM_VOLATILE_USHORT_POINTER (volatile unsigned short int * const)
65#define SIM_VOLATILE_UCHAR_POINTER  (volatile unsigned char * const)
66#endif
67
68/* SIM_CRB (SIM Control Register Block) base address of the SIM
69   control registers */
70#ifndef SIM_CRB
71#if SIM_MM == 0
72#define SIM_CRB 0x7ffa00
73#else /* SIM_MM */
74#undef SIM_MM
75#define SIM_MM 1
76#define SIM_CRB 0xfffa00
77#endif /* SIM_MM */
78#endif /* SIM_CRB */
79
80
81#define SIMCR SIM_VOLATILE_USHORT_POINTER(0x00 + SIM_CRB)
82                                /* Module Configuration Register */
83#define    EXOFF 0x8000         /*    External Clock Off */
84#define    FRZSW 0x4000         /*    Freeze Software Enable */
85#define    FRZBM 0x2000         /*    Freeze Bus Monitor Enable */
86#define    SLVEN 0x0800         /*    Factory Test Model Enabled (ro)*/
87#define    SHEN  0x0300         /*    Show Cycle Enable */
88#define    SUPV  0x0080         /*    Supervisor/Unrestricted Data Space */
89#define    MM    0x0040         /*    Module Mapping */
90#define    IARB  0x000f         /*    Interrupt Arbitration Field */
91
92
93
94#define SIMTR SIM_VOLATILE_USHORT_POINTER(0x02 + SIM_CRB)
95                                /* SIM Test Register */
96/* Used only for factor testing */
97
98
99
100#define SYNCR SIM_VOLATILE_USHORT_POINTER(0x04 + SIM_CRB)
101                                /* Clock Synthesizer Control Register */
102#define    VCO      0x8000      /*    Frequency Control (VCO) */
103#define    PRESCALE 0x4000      /*    Frequency Control Bit (Prescale) */
104#define    COUNTER  0x3f00      /*    Frequency Control Counter */
105#define    EDIV     0x0080      /*    ECLK Divide Rate */
106#define    SLIMP    0x0010      /*    Limp Mode Status */
107#define    SLOCK    0x0008      /*    Synthesizer Lock */
108#define    RSTEN    0x0004      /*    Reset Enable */
109#define    STSIM    0x0002      /*    Stop Mode SIM Clock */
110#define    STEXT    0x0001      /*    Stop Mode External Clock */
111
112
113
114#define RSR SIM_VOLATILE_UCHAR_POINTER(0x07 + SIM_CRB)
115                                /* Reset Status Register */
116#define    EXT   0x0080         /*    External Reset */
117#define    POW   0x0040         /*    Power-On Reset */
118#define    SW    0x0020         /*    Software Watchdog Reset */
119#define    DBF   0x0010         /*    Double Bus Fault Reset */
120#define    LOC   0x0004         /*    Loss of Clock Reset */
121#define    SYS   0x0002         /*    System Reset */
122#define    TST   0x0001         /*    Test Submodule Reset */
123
124
125
126#define SIMTRE SIM_VOLATILE_USHORT_POINTER(0x08 + SIM_CRB)
127                                /* System Integration Test Register */
128/* Used only for factor testing */
129
130
131
132#define PORTE0 SIM_VOLATILE_UCHAR_POINTER(0x11 + SIM_CRB)
133#define PORTE1 SIM_VOLATILE_UCHAR_POINTER(0x13 + SIM_CRB)
134                                /* Port E Data Register */
135#define DDRE SIM_VOLATILE_UCHAR_POINTER(0x15 + SIM_CRB)
136                                /* Port E Data Direction Register */
137#define PEPAR SIM_VOLATILE_UCHAR_POINTER(0x17 + SIM_CRB)
138                                /* Port E Pin Assignment Register */
139/* Any bit cleared (zero) defines the corresponding pin to be an I/O
140   pin. Any bit set defines the corresponding pin to be a bus control
141   signal. */
142
143
144
145#define PORTF0 SIM_VOLATILE_UCHAR_POINTER(0x19 + SIM_CRB)
146#define PORTF1 SIM_VOLATILE_UCHAR_POINTER(0x1b + SIM_CRB)
147                                /* Port F Data Register */
148#define DDRF SIM_VOLATILE_UCHAR_POINTER(0x1d + SIM_CRB)
149                                /* Port E Data Direction Register */
150#define PFPAR SIM_VOLATILE_UCHAR_POINTER(0x1f + SIM_CRB)
151/* Any bit cleared (zero) defines the corresponding pin to be an I/O
152   pin. Any bit set defines the corresponding pin to be a bus control
153   signal. */
154
155
156
157#define SYPCR SIM_VOLATILE_UCHAR_POINTER(0x21 + SIM_CRB)
158/* !!! can write to only once after reset !!! */
159                                /* System Protection Control Register */
160#define    SWE   0x80           /*    Software Watch Enable */
161#define    SWP   0x40           /*    Software Watchdog Prescale */
162#define    SWT   0x30           /*    Software Watchdog Timing */
163#define    HME   0x08           /*    Halt Monitor Enable */
164#define    BME   0x04           /*    Bus Monitor External Enable */
165#define    BMT   0x03           /*    Bus Monitor Timing */
166
167
168
169#define PICR SIM_VOLATILE_USHORT_POINTER(0x22 + SIM_CRB)
170                                /* Periodic Interrupt Control Reg. */
171#define    PIRQL 0x0700         /*    Periodic Interrupt Request Level */
172#define    PIV   0x00ff         /*    Periodic Interrupt Level */
173
174
175
176#define PITR SIM_VOLATILE_USHORT_POINTER(0x24 + SIM_CRB)
177                                /* Periodic Interrupt Timer Register */
178#define    PTP   0x0100         /*    Periodic Timer Prescaler Control */
179#define    PITM  0x00ff         /*    Periodic Interrupt Timing Modulus */
180
181
182
183#define SWSR SIM_VOLATILE_UCHAR_POINTER(0x27 + SIM_CRB)
184                                /* Software Service Register */
185/* write 0x55 then 0xaa to service the software watchdog */
186
187
188
189#define TSTMSRA SIM_VOLATILE_USHORT_POINTER(0x30 + SIM_CRB)
190                                /* Test Module Master Shift A */
191#define TSTMSRB SIM_VOLATILE_USHORT_POINTER(0x32 + SIM_CRB)
192                                /* Test Module Master Shift A */
193#define TSTSC SIM_VOLATILE_USHORT_POINTER(0x34 + SIM_CRB)
194                                /* Test Module Shift Count */
195#define TSTRC SIM_VOLATILE_USHORT_POINTER(0x36 + SIM_CRB)
196                                /* Test Module Repetition Counter */
197#define CREG SIM_VOLATILE_USHORT_POINTER(0x38 + SIM_CRB)
198                                /* Test Module Control */
199#define DREG SIM_VOLATILE_USHORT_POINTER(0x3a + SIM_CRB)
200                                /* Test Module Distributed */
201/* Used only for factor testing */
202
203
204
205#define PORTC SIM_VOLATILE_UCHAR_POINTER(0x41 + SIM_CRB)
206                                /* Port C Data */
207
208
209
210#define CSPAR0 SIM_VOLATILE_USHORT_POINTER(0x44 + SIM_CRB)
211                                /* Chip Select Pin Assignment
212                                   Resgister 0 */
213/* CSPAR0 contains seven two-bit fields that determine the functions
214   of corresponding chip-select pins. CSPAR0[15:14] are not
215   used. These bits always read zero; write have no effect. CSPAR0 bit
216   1 always reads one; writes to CSPAR0 bit 1 have no effect. */
217#define CSPAR1 SIM_VOLATILE_USHORT_POINTER(0x46 + SIM_CRB)
218                                /* Chip Select Pin Assignment
219                                   Register 1 */
220/* CSPAR1 contains five two-bit fields that determine the finctions of
221   corresponding chip-select pins. CSPAR1[15:10] are not used. These
222   bits always read zero; writes have no effect. */
223/*
224 *
225 *                      Bit Field  |  Description
226 *                     ------------+---------------
227 *                         00      | Discrete Output
228 *                         01      | Alternate Function
229 *                         10      | Chip Select (8-bit port)
230 *                         11      | Chip Select (16-bit port)
231 */
232#define DisOut 0x0
233#define AltFun 0x1
234#define CS8bit 0x2
235#define CS16bit 0x3
236/*
237 *
238 * CSPARx Field    |Chip Select Signal  |  Alternate Signal  |  Discrete Output
239 *-----------------+--------------------+--------------------+---------------*/
240#define CS_5    12 /*     !CS5          |         FC2        |       PC2     */
241#define CS_4    10 /*     !CS4          |         FC1        |       PC1     */
242#define CS_3     8 /*     !CS3          |         FC0        |       PC0     */
243#define CS_2     6 /*     !CS2          |       !BGACK       |               */
244#define CS_1     4 /*     !CS1          |         !BG        |               */
245#define CS_0     2 /*     !CS0          |         !BR        |               */
246#define CSBOOT   0 /*     !CSBOOT       |                    |               */
247/*                 |                    |                    |               */
248#define CS_10    8 /*     !CS10         |       ADDR23       |      ECLK     */
249#define CS_9     6 /*     !CS9          |       ADDR22       |       PC6     */
250#define CS_8     4 /*     !CS8          |       ADDR21       |       PC5     */
251#define CS_7     2 /*     !CS7          |       ADDR20       |       PC4     */
252#define CS_6     0 /*     !CS6          |       ADDR19       |       PC3     */
253
254#define BS_2K 0x0
255#define BS_8K 0x1
256#define BS_16K 0x2
257#define BS_64K 0x3
258#define BS_128K 0x4
259#define BS_256K 0x5
260#define BS_512K 0x6
261#define BS_1M 0x7
262
263#define CSBARBT SIM_VOLATILE_USHORT_POINTER(0x48 + SIM_CRB)
264#define CSBAR0 SIM_VOLATILE_USHORT_POINTER(0x4c + SIM_CRB)
265#define CSBAR1 SIM_VOLATILE_USHORT_POINTER(0x50 + SIM_CRB)
266#define CSBAR2 SIM_VOLATILE_USHORT_POINTER(0x54 + SIM_CRB)
267#define CSBAR3 SIM_VOLATILE_USHORT_POINTER(0x58 + SIM_CRB)
268#define CSBAR4 SIM_VOLATILE_USHORT_POINTER(0x5c + SIM_CRB)
269#define CSBAR5 SIM_VOLATILE_USHORT_POINTER(0x60 + SIM_CRB)
270#define CSBAR6 SIM_VOLATILE_USHORT_POINTER(0x64 + SIM_CRB)
271#define CSBAR7 SIM_VOLATILE_USHORT_POINTER(0x68 + SIM_CRB)
272#define CSBAR8 SIM_VOLATILE_USHORT_POINTER(0x6c + SIM_CRB)
273#define CSBAR9 SIM_VOLATILE_USHORT_POINTER(0x70 + SIM_CRB)
274#define CSBAR10 SIM_VOLATILE_USHORT_POINTER(0x74 + SIM_CRB)
275
276#define MODE 0x8000
277#define Disable 0
278#define LowerByte 0x2000
279#define UpperByte 0x4000
280#define BothBytes 0x6000
281#define ReadOnly 0x0800
282#define WriteOnly 0x1000
283#define ReadWrite 0x1800
284#define SyncAS 0x0
285#define SyncDS 0x0400
286
287#define WaitStates_0 (0x0 << 6)
288#define WaitStates_1 (0x1 << 6)
289#define WaitStates_2 (0x2 << 6)
290#define WaitStates_3 (0x3 << 6)
291#define WaitStates_4 (0x4 << 6)
292#define WaitStates_5 (0x5 << 6)
293#define WaitStates_6 (0x6 << 6)
294#define WaitStates_7 (0x7 << 6)
295#define WaitStates_8 (0x8 << 6)
296#define WaitStates_9 (0x9 << 6)
297#define WaitStates_10 (0xa << 6)
298#define WaitStates_11 (0xb << 6)
299#define WaitStates_12 (0xc << 6)
300#define WaitStates_13 (0xd << 6)
301#define FastTerm (0xe << 6)
302#define External (0xf << 6)
303
304#define CPUSpace (0x0 << 4)
305#define UserSpace (0x1 << 4)
306#define SupSpace (0x2 << 4)
307#define UserSupSpace (0x3 << 4)
308
309#define IPLevel_any 0x0
310#define IPLevel_1 0x2
311#define IPLevel_2 0x4
312#define IPLevel_3 0x6
313#define IPLevel_4 0x8
314#define IPLevel_5 0xa
315#define IPLevel_6 0xc
316#define IPLevel_7 0xe
317
318#define AVEC 1
319
320#define CSORBT SIM_VOLATILE_USHORT_POINTER(0x4a + SIM_CRB)
321#define CSOR0 SIM_VOLATILE_USHORT_POINTER(0x4e + SIM_CRB)
322#define CSOR1 SIM_VOLATILE_USHORT_POINTER(0x52 + SIM_CRB)
323#define CSOR2 SIM_VOLATILE_USHORT_POINTER(0x56 + SIM_CRB)
324#define CSOR3 SIM_VOLATILE_USHORT_POINTER(0x5a + SIM_CRB)
325#define CSOR4 SIM_VOLATILE_USHORT_POINTER(0x5e + SIM_CRB)
326#define CSOR5 SIM_VOLATILE_USHORT_POINTER(0x62 + SIM_CRB)
327#define CSOR6 SIM_VOLATILE_USHORT_POINTER(0x66 + SIM_CRB)
328#define CSOR7 SIM_VOLATILE_USHORT_POINTER(0x6a + SIM_CRB)
329#define CSOR8 SIM_VOLATILE_USHORT_POINTER(0x6e + SIM_CRB)
330#define CSOR9 SIM_VOLATILE_USHORT_POINTER(0x72 + SIM_CRB)
331#define CSOR10 SIM_VOLATILE_USHORT_POINTER(0x76 + SIM_CRB)
332
333#endif /* _RTEMS_M68K_SIM_H */
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