| 1 | /* |
|---|
| 2 | *------------------------------------------------------------------- |
|---|
| 3 | * |
|---|
| 4 | * SIM -- System Integration Module |
|---|
| 5 | * |
|---|
| 6 | * The system integration module (SIM) is used on many Motorola 16- |
|---|
| 7 | * and 32-bit MCUs for the following functions: |
|---|
| 8 | * |
|---|
| 9 | * () System configuration and protection. Bus and software watchdog |
|---|
| 10 | * monitors are provided in addition to periodic interrupt generators. |
|---|
| 11 | * |
|---|
| 12 | * () Clock signal generation for other intermodule bus (IMB) members |
|---|
| 13 | * and external devices. |
|---|
| 14 | * |
|---|
| 15 | * () The generation of chip-select signals that simplify external |
|---|
| 16 | * circuitry interface. |
|---|
| 17 | * |
|---|
| 18 | * () Data ports that are available for general purpose input and |
|---|
| 19 | * output. |
|---|
| 20 | * |
|---|
| 21 | * () A system test block that is intended only for factory tests. |
|---|
| 22 | * |
|---|
| 23 | * For more information, refer to Motorola's "Modular Microcontroller |
|---|
| 24 | * Family System Integration Module Reference Manual" (Motorola document |
|---|
| 25 | * SIMRM/AD). |
|---|
| 26 | * |
|---|
| 27 | * This file was created by John S. Gwynne to support Motorola's 68332 MCU. |
|---|
| 28 | * |
|---|
| 29 | * Redistribution and use in source and binary forms are permitted |
|---|
| 30 | * provided that the following conditions are met: |
|---|
| 31 | * 1. Redistribution of source code and documentation must retain |
|---|
| 32 | * the above authorship, this list of conditions and the |
|---|
| 33 | * following disclaimer. |
|---|
| 34 | * 2. The name of the author may not be used to endorse or promote |
|---|
| 35 | * products derived from this software without specific prior |
|---|
| 36 | * written permission. |
|---|
| 37 | * |
|---|
| 38 | * This software is provided "AS IS" without warranty of any kind, |
|---|
| 39 | * either expressed or implied, including, but not limited to, the |
|---|
| 40 | * implied warranties of merchantability, title and fitness for a |
|---|
| 41 | * particular purpose. |
|---|
| 42 | * |
|---|
| 43 | *------------------------------------------------------------------ |
|---|
| 44 | */ |
|---|
| 45 | |
|---|
| 46 | #ifndef _RTEMS_M68K_SIM_H |
|---|
| 47 | #define _RTEMS_M68K_SIM_H |
|---|
| 48 | |
|---|
| 49 | |
|---|
| 50 | /* SAM-- shift and mask */ |
|---|
| 51 | #undef SAM |
|---|
| 52 | #define SAM(a,b,c) ((a << b) & c) |
|---|
| 53 | |
|---|
| 54 | /* |
|---|
| 55 | * These macros make this file usable from assembly. |
|---|
| 56 | */ |
|---|
| 57 | |
|---|
| 58 | #ifdef ASM |
|---|
| 59 | #define SIM_VOLATILE_USHORT_POINTER |
|---|
| 60 | #define SIM_VOLATILE_UCHAR_POINTER |
|---|
| 61 | #else |
|---|
| 62 | #define SIM_VOLATILE_USHORT_POINTER (volatile unsigned short int * const) |
|---|
| 63 | #define SIM_VOLATILE_UCHAR_POINTER (volatile unsigned char * const) |
|---|
| 64 | #endif |
|---|
| 65 | |
|---|
| 66 | /* SIM_CRB (SIM Control Register Block) base address of the SIM |
|---|
| 67 | control registers */ |
|---|
| 68 | #ifndef SIM_CRB |
|---|
| 69 | #if SIM_MM == 0 |
|---|
| 70 | #define SIM_CRB 0x7ffa00 |
|---|
| 71 | #else /* SIM_MM */ |
|---|
| 72 | #undef SIM_MM |
|---|
| 73 | #define SIM_MM 1 |
|---|
| 74 | #define SIM_CRB 0xfffa00 |
|---|
| 75 | #endif /* SIM_MM */ |
|---|
| 76 | #endif /* SIM_CRB */ |
|---|
| 77 | |
|---|
| 78 | |
|---|
| 79 | #define SIMCR SIM_VOLATILE_USHORT_POINTER(0x00 + SIM_CRB) |
|---|
| 80 | /* Module Configuration Register */ |
|---|
| 81 | #define EXOFF 0x8000 /* External Clock Off */ |
|---|
| 82 | #define FRZSW 0x4000 /* Freeze Software Enable */ |
|---|
| 83 | #define FRZBM 0x2000 /* Freeze Bus Monitor Enable */ |
|---|
| 84 | #define SLVEN 0x0800 /* Factory Test Model Enabled (ro)*/ |
|---|
| 85 | #define SHEN 0x0300 /* Show Cycle Enable */ |
|---|
| 86 | #define SUPV 0x0080 /* Supervisor/Unrestricted Data Space */ |
|---|
| 87 | #define MM 0x0040 /* Module Mapping */ |
|---|
| 88 | #define IARB 0x000f /* Interrupt Arbitration Field */ |
|---|
| 89 | |
|---|
| 90 | |
|---|
| 91 | |
|---|
| 92 | #define SIMTR SIM_VOLATILE_USHORT_POINTER(0x02 + SIM_CRB) |
|---|
| 93 | /* SIM Test Register */ |
|---|
| 94 | /* Used only for factor testing */ |
|---|
| 95 | |
|---|
| 96 | |
|---|
| 97 | |
|---|
| 98 | #define SYNCR SIM_VOLATILE_USHORT_POINTER(0x04 + SIM_CRB) |
|---|
| 99 | /* Clock Synthesizer Control Register */ |
|---|
| 100 | #define VCO 0x8000 /* Frequency Control (VCO) */ |
|---|
| 101 | #define PRESCALE 0x4000 /* Frequency Control Bit (Prescale) */ |
|---|
| 102 | #define COUNTER 0x3f00 /* Frequency Control Counter */ |
|---|
| 103 | #define EDIV 0x0080 /* ECLK Divide Rate */ |
|---|
| 104 | #define SLIMP 0x0010 /* Limp Mode Status */ |
|---|
| 105 | #define SLOCK 0x0008 /* Synthesizer Lock */ |
|---|
| 106 | #define RSTEN 0x0004 /* Reset Enable */ |
|---|
| 107 | #define STSIM 0x0002 /* Stop Mode SIM Clock */ |
|---|
| 108 | #define STEXT 0x0001 /* Stop Mode External Clock */ |
|---|
| 109 | |
|---|
| 110 | |
|---|
| 111 | |
|---|
| 112 | #define RSR SIM_VOLATILE_UCHAR_POINTER(0x07 + SIM_CRB) |
|---|
| 113 | /* Reset Status Register */ |
|---|
| 114 | #define EXT 0x0080 /* External Reset */ |
|---|
| 115 | #define POW 0x0040 /* Power-On Reset */ |
|---|
| 116 | #define SW 0x0020 /* Software Watchdog Reset */ |
|---|
| 117 | #define DBF 0x0010 /* Double Bus Fault Reset */ |
|---|
| 118 | #define LOC 0x0004 /* Loss of Clock Reset */ |
|---|
| 119 | #define SYS 0x0002 /* System Reset */ |
|---|
| 120 | #define TST 0x0001 /* Test Submodule Reset */ |
|---|
| 121 | |
|---|
| 122 | |
|---|
| 123 | |
|---|
| 124 | #define SIMTRE SIM_VOLATILE_USHORT_POINTER(0x08 + SIM_CRB) |
|---|
| 125 | /* System Integration Test Register */ |
|---|
| 126 | /* Used only for factor testing */ |
|---|
| 127 | |
|---|
| 128 | |
|---|
| 129 | |
|---|
| 130 | #define PORTE0 SIM_VOLATILE_UCHAR_POINTER(0x11 + SIM_CRB) |
|---|
| 131 | #define PORTE1 SIM_VOLATILE_UCHAR_POINTER(0x13 + SIM_CRB) |
|---|
| 132 | /* Port E Data Register */ |
|---|
| 133 | #define DDRE SIM_VOLATILE_UCHAR_POINTER(0x15 + SIM_CRB) |
|---|
| 134 | /* Port E Data Direction Register */ |
|---|
| 135 | #define PEPAR SIM_VOLATILE_UCHAR_POINTER(0x17 + SIM_CRB) |
|---|
| 136 | /* Port E Pin Assignment Register */ |
|---|
| 137 | /* Any bit cleared (zero) defines the corresponding pin to be an I/O |
|---|
| 138 | pin. Any bit set defines the corresponding pin to be a bus control |
|---|
| 139 | signal. */ |
|---|
| 140 | |
|---|
| 141 | |
|---|
| 142 | |
|---|
| 143 | #define PORTF0 SIM_VOLATILE_UCHAR_POINTER(0x19 + SIM_CRB) |
|---|
| 144 | #define PORTF1 SIM_VOLATILE_UCHAR_POINTER(0x1b + SIM_CRB) |
|---|
| 145 | /* Port F Data Register */ |
|---|
| 146 | #define DDRF SIM_VOLATILE_UCHAR_POINTER(0x1d + SIM_CRB) |
|---|
| 147 | /* Port E Data Direction Register */ |
|---|
| 148 | #define PFPAR SIM_VOLATILE_UCHAR_POINTER(0x1f + SIM_CRB) |
|---|
| 149 | /* Any bit cleared (zero) defines the corresponding pin to be an I/O |
|---|
| 150 | pin. Any bit set defines the corresponding pin to be a bus control |
|---|
| 151 | signal. */ |
|---|
| 152 | |
|---|
| 153 | |
|---|
| 154 | |
|---|
| 155 | #define SYPCR SIM_VOLATILE_UCHAR_POINTER(0x21 + SIM_CRB) |
|---|
| 156 | /* !!! can write to only once after reset !!! */ |
|---|
| 157 | /* System Protection Control Register */ |
|---|
| 158 | #define SWE 0x80 /* Software Watch Enable */ |
|---|
| 159 | #define SWP 0x40 /* Software Watchdog Prescale */ |
|---|
| 160 | #define SWT 0x30 /* Software Watchdog Timing */ |
|---|
| 161 | #define HME 0x08 /* Halt Monitor Enable */ |
|---|
| 162 | #define BME 0x04 /* Bus Monitor External Enable */ |
|---|
| 163 | #define BMT 0x03 /* Bus Monitor Timing */ |
|---|
| 164 | |
|---|
| 165 | |
|---|
| 166 | |
|---|
| 167 | #define PICR SIM_VOLATILE_USHORT_POINTER(0x22 + SIM_CRB) |
|---|
| 168 | /* Periodic Interrupt Control Reg. */ |
|---|
| 169 | #define PIRQL 0x0700 /* Periodic Interrupt Request Level */ |
|---|
| 170 | #define PIV 0x00ff /* Periodic Interrupt Level */ |
|---|
| 171 | |
|---|
| 172 | |
|---|
| 173 | |
|---|
| 174 | #define PITR SIM_VOLATILE_USHORT_POINTER(0x24 + SIM_CRB) |
|---|
| 175 | /* Periodic Interrupt Timer Register */ |
|---|
| 176 | #define PTP 0x0100 /* Periodic Timer Prescaler Control */ |
|---|
| 177 | #define PITM 0x00ff /* Periodic Interrupt Timing Modulus */ |
|---|
| 178 | |
|---|
| 179 | |
|---|
| 180 | |
|---|
| 181 | #define SWSR SIM_VOLATILE_UCHAR_POINTER(0x27 + SIM_CRB) |
|---|
| 182 | /* Software Service Register */ |
|---|
| 183 | /* write 0x55 then 0xaa to service the software watchdog */ |
|---|
| 184 | |
|---|
| 185 | |
|---|
| 186 | |
|---|
| 187 | #define TSTMSRA SIM_VOLATILE_USHORT_POINTER(0x30 + SIM_CRB) |
|---|
| 188 | /* Test Module Master Shift A */ |
|---|
| 189 | #define TSTMSRB SIM_VOLATILE_USHORT_POINTER(0x32 + SIM_CRB) |
|---|
| 190 | /* Test Module Master Shift A */ |
|---|
| 191 | #define TSTSC SIM_VOLATILE_USHORT_POINTER(0x34 + SIM_CRB) |
|---|
| 192 | /* Test Module Shift Count */ |
|---|
| 193 | #define TSTRC SIM_VOLATILE_USHORT_POINTER(0x36 + SIM_CRB) |
|---|
| 194 | /* Test Module Repetition Counter */ |
|---|
| 195 | #define CREG SIM_VOLATILE_USHORT_POINTER(0x38 + SIM_CRB) |
|---|
| 196 | /* Test Module Control */ |
|---|
| 197 | #define DREG SIM_VOLATILE_USHORT_POINTER(0x3a + SIM_CRB) |
|---|
| 198 | /* Test Module Distributed */ |
|---|
| 199 | /* Used only for factor testing */ |
|---|
| 200 | |
|---|
| 201 | |
|---|
| 202 | |
|---|
| 203 | #define PORTC SIM_VOLATILE_UCHAR_POINTER(0x41 + SIM_CRB) |
|---|
| 204 | /* Port C Data */ |
|---|
| 205 | |
|---|
| 206 | |
|---|
| 207 | |
|---|
| 208 | #define CSPAR0 SIM_VOLATILE_USHORT_POINTER(0x44 + SIM_CRB) |
|---|
| 209 | /* Chip Select Pin Assignment |
|---|
| 210 | Resgister 0 */ |
|---|
| 211 | /* CSPAR0 contains seven two-bit fields that determine the functions |
|---|
| 212 | of corresponding chip-select pins. CSPAR0[15:14] are not |
|---|
| 213 | used. These bits always read zero; write have no effect. CSPAR0 bit |
|---|
| 214 | 1 always reads one; writes to CSPAR0 bit 1 have no effect. */ |
|---|
| 215 | #define CSPAR1 SIM_VOLATILE_USHORT_POINTER(0x46 + SIM_CRB) |
|---|
| 216 | /* Chip Select Pin Assignment |
|---|
| 217 | Register 1 */ |
|---|
| 218 | /* CSPAR1 contains five two-bit fields that determine the finctions of |
|---|
| 219 | corresponding chip-select pins. CSPAR1[15:10] are not used. These |
|---|
| 220 | bits always read zero; writes have no effect. */ |
|---|
| 221 | /* |
|---|
| 222 | * |
|---|
| 223 | * Bit Field | Description |
|---|
| 224 | * ------------+--------------- |
|---|
| 225 | * 00 | Discrete Output |
|---|
| 226 | * 01 | Alternate Function |
|---|
| 227 | * 10 | Chip Select (8-bit port) |
|---|
| 228 | * 11 | Chip Select (16-bit port) |
|---|
| 229 | */ |
|---|
| 230 | #define DisOut 0x0 |
|---|
| 231 | #define AltFun 0x1 |
|---|
| 232 | #define CS8bit 0x2 |
|---|
| 233 | #define CS16bit 0x3 |
|---|
| 234 | /* |
|---|
| 235 | * |
|---|
| 236 | * CSPARx Field |Chip Select Signal | Alternate Signal | Discrete Output |
|---|
| 237 | *-----------------+--------------------+--------------------+---------------*/ |
|---|
| 238 | #define CS_5 12 /* !CS5 | FC2 | PC2 */ |
|---|
| 239 | #define CS_4 10 /* !CS4 | FC1 | PC1 */ |
|---|
| 240 | #define CS_3 8 /* !CS3 | FC0 | PC0 */ |
|---|
| 241 | #define CS_2 6 /* !CS2 | !BGACK | */ |
|---|
| 242 | #define CS_1 4 /* !CS1 | !BG | */ |
|---|
| 243 | #define CS_0 2 /* !CS0 | !BR | */ |
|---|
| 244 | #define CSBOOT 0 /* !CSBOOT | | */ |
|---|
| 245 | /* | | | */ |
|---|
| 246 | #define CS_10 8 /* !CS10 | ADDR23 | ECLK */ |
|---|
| 247 | #define CS_9 6 /* !CS9 | ADDR22 | PC6 */ |
|---|
| 248 | #define CS_8 4 /* !CS8 | ADDR21 | PC5 */ |
|---|
| 249 | #define CS_7 2 /* !CS7 | ADDR20 | PC4 */ |
|---|
| 250 | #define CS_6 0 /* !CS6 | ADDR19 | PC3 */ |
|---|
| 251 | |
|---|
| 252 | #define BS_2K 0x0 |
|---|
| 253 | #define BS_8K 0x1 |
|---|
| 254 | #define BS_16K 0x2 |
|---|
| 255 | #define BS_64K 0x3 |
|---|
| 256 | #define BS_128K 0x4 |
|---|
| 257 | #define BS_256K 0x5 |
|---|
| 258 | #define BS_512K 0x6 |
|---|
| 259 | #define BS_1M 0x7 |
|---|
| 260 | |
|---|
| 261 | #define CSBARBT SIM_VOLATILE_USHORT_POINTER(0x48 + SIM_CRB) |
|---|
| 262 | #define CSBAR0 SIM_VOLATILE_USHORT_POINTER(0x4c + SIM_CRB) |
|---|
| 263 | #define CSBAR1 SIM_VOLATILE_USHORT_POINTER(0x50 + SIM_CRB) |
|---|
| 264 | #define CSBAR2 SIM_VOLATILE_USHORT_POINTER(0x54 + SIM_CRB) |
|---|
| 265 | #define CSBAR3 SIM_VOLATILE_USHORT_POINTER(0x58 + SIM_CRB) |
|---|
| 266 | #define CSBAR4 SIM_VOLATILE_USHORT_POINTER(0x5c + SIM_CRB) |
|---|
| 267 | #define CSBAR5 SIM_VOLATILE_USHORT_POINTER(0x60 + SIM_CRB) |
|---|
| 268 | #define CSBAR6 SIM_VOLATILE_USHORT_POINTER(0x64 + SIM_CRB) |
|---|
| 269 | #define CSBAR7 SIM_VOLATILE_USHORT_POINTER(0x68 + SIM_CRB) |
|---|
| 270 | #define CSBAR8 SIM_VOLATILE_USHORT_POINTER(0x6c + SIM_CRB) |
|---|
| 271 | #define CSBAR9 SIM_VOLATILE_USHORT_POINTER(0x70 + SIM_CRB) |
|---|
| 272 | #define CSBAR10 SIM_VOLATILE_USHORT_POINTER(0x74 + SIM_CRB) |
|---|
| 273 | |
|---|
| 274 | #define MODE 0x8000 |
|---|
| 275 | #define Disable 0 |
|---|
| 276 | #define LowerByte 0x2000 |
|---|
| 277 | #define UpperByte 0x4000 |
|---|
| 278 | #define BothBytes 0x6000 |
|---|
| 279 | #define ReadOnly 0x0800 |
|---|
| 280 | #define WriteOnly 0x1000 |
|---|
| 281 | #define ReadWrite 0x1800 |
|---|
| 282 | #define SyncAS 0x0 |
|---|
| 283 | #define SyncDS 0x0400 |
|---|
| 284 | |
|---|
| 285 | #define WaitStates_0 (0x0 << 6) |
|---|
| 286 | #define WaitStates_1 (0x1 << 6) |
|---|
| 287 | #define WaitStates_2 (0x2 << 6) |
|---|
| 288 | #define WaitStates_3 (0x3 << 6) |
|---|
| 289 | #define WaitStates_4 (0x4 << 6) |
|---|
| 290 | #define WaitStates_5 (0x5 << 6) |
|---|
| 291 | #define WaitStates_6 (0x6 << 6) |
|---|
| 292 | #define WaitStates_7 (0x7 << 6) |
|---|
| 293 | #define WaitStates_8 (0x8 << 6) |
|---|
| 294 | #define WaitStates_9 (0x9 << 6) |
|---|
| 295 | #define WaitStates_10 (0xa << 6) |
|---|
| 296 | #define WaitStates_11 (0xb << 6) |
|---|
| 297 | #define WaitStates_12 (0xc << 6) |
|---|
| 298 | #define WaitStates_13 (0xd << 6) |
|---|
| 299 | #define FastTerm (0xe << 6) |
|---|
| 300 | #define External (0xf << 6) |
|---|
| 301 | |
|---|
| 302 | #define CPUSpace (0x0 << 4) |
|---|
| 303 | #define UserSpace (0x1 << 4) |
|---|
| 304 | #define SupSpace (0x2 << 4) |
|---|
| 305 | #define UserSupSpace (0x3 << 4) |
|---|
| 306 | |
|---|
| 307 | #define IPLevel_any 0x0 |
|---|
| 308 | #define IPLevel_1 0x2 |
|---|
| 309 | #define IPLevel_2 0x4 |
|---|
| 310 | #define IPLevel_3 0x6 |
|---|
| 311 | #define IPLevel_4 0x8 |
|---|
| 312 | #define IPLevel_5 0xa |
|---|
| 313 | #define IPLevel_6 0xc |
|---|
| 314 | #define IPLevel_7 0xe |
|---|
| 315 | |
|---|
| 316 | #define AVEC 1 |
|---|
| 317 | |
|---|
| 318 | #define CSORBT SIM_VOLATILE_USHORT_POINTER(0x4a + SIM_CRB) |
|---|
| 319 | #define CSOR0 SIM_VOLATILE_USHORT_POINTER(0x4e + SIM_CRB) |
|---|
| 320 | #define CSOR1 SIM_VOLATILE_USHORT_POINTER(0x52 + SIM_CRB) |
|---|
| 321 | #define CSOR2 SIM_VOLATILE_USHORT_POINTER(0x56 + SIM_CRB) |
|---|
| 322 | #define CSOR3 SIM_VOLATILE_USHORT_POINTER(0x5a + SIM_CRB) |
|---|
| 323 | #define CSOR4 SIM_VOLATILE_USHORT_POINTER(0x5e + SIM_CRB) |
|---|
| 324 | #define CSOR5 SIM_VOLATILE_USHORT_POINTER(0x62 + SIM_CRB) |
|---|
| 325 | #define CSOR6 SIM_VOLATILE_USHORT_POINTER(0x66 + SIM_CRB) |
|---|
| 326 | #define CSOR7 SIM_VOLATILE_USHORT_POINTER(0x6a + SIM_CRB) |
|---|
| 327 | #define CSOR8 SIM_VOLATILE_USHORT_POINTER(0x6e + SIM_CRB) |
|---|
| 328 | #define CSOR9 SIM_VOLATILE_USHORT_POINTER(0x72 + SIM_CRB) |
|---|
| 329 | #define CSOR10 SIM_VOLATILE_USHORT_POINTER(0x76 + SIM_CRB) |
|---|
| 330 | |
|---|
| 331 | #endif /* _RTEMS_M68K_SIM_H */ |
|---|
![[RTEMS Logo]](/images/logo.png){kind=logo}
