source: rtems/cpukit/score/cpu/m68k/rtems/m68k/sim.h @ b7912a89

4.104.114.84.95
Last change on this file since b7912a89 was b7912a89, checked in by Joel Sherrill <joel.sherrill@…>, on 11/22/99 at 14:25:01

Changed name of W, X, and Y macros for fields in the Clock
Synthesizer Control Register to remove use of single letter names.

  • Property mode set to 100644
File size: 11.9 KB
Line 
1/*
2 *-------------------------------------------------------------------
3 *
4 *   SIM -- System Integration Module
5 *
6 * The system integration module (SIM) is used on many Motorola 16-
7 * and 32-bit MCUs for the following functions:
8 *
9 *  () System configuration and protection. Bus and software watchdog
10 *  monitors are provided in addition to periodic interrupt generators.
11 *
12 *  () Clock signal generation for other intermodule bus (IMB) members
13 *  and external devices.
14 *
15 *  () The generation of chip-select signals that simplify external
16 *  circuitry interface.
17 *
18 *  () Data ports that are available for general purpose input and
19 *  output.
20 *
21 *  () A system test block that is intended only for factory tests.
22 *
23 * For more information, refer to Motorola's "Modular Microcontroller
24 * Family System Integration Module Reference Manual" (Motorola document
25 * SIMRM/AD).
26 *
27 * This file has been created by John S. Gwynne for support of
28 * Motorola's 68332 MCU in the efi332 project.
29 *
30 * Redistribution and use in source and binary forms are permitted
31 * provided that the following conditions are met:
32 * 1. Redistribution of source code and documentation must retain
33 *    the above authorship, this list of conditions and the
34 *    following disclaimer.
35 * 2. The name of the author may not be used to endorse or promote
36 *    products derived from this software without specific prior
37 *    written permission.
38 *
39 * This software is provided "AS IS" without warranty of any kind,
40 * either expressed or implied, including, but not limited to, the
41 * implied warranties of merchantability, title and fitness for a
42 * particular purpose.
43 *
44 *------------------------------------------------------------------
45 *
46 *  $Id$
47 */
48
49#ifndef _SIM_H_
50#define _SIM_H_
51
52
53/*
54 *  XXX Why is a generic file like this including a bsp specific file?
55
56#include <efi332.h>
57 */
58
59
60/* SAM-- shift and mask */
61#undef  SAM
62#define SAM(a,b,c) ((a << b) & c)
63
64/*
65 *  These macros make this file usable from assembly.
66 */
67
68#ifdef ASM
69#define SIM_VOLATILE_USHORT_POINTER
70#define SIM_VOLATILE_UCHAR_POINTER
71#else
72#define SIM_VOLATILE_USHORT_POINTER (volatile unsigned short int * const)
73#define SIM_VOLATILE_UCHAR_POINTER  (volatile unsigned char * const)
74#endif
75
76/* SIM_CRB (SIM Control Register Block) base address of the SIM
77   control registers */
78/* not included in ram_init.h */
79#if SIM_MM == 0
80#define SIM_CRB 0x7ffa00
81#else
82#undef SIM_MM
83#define SIM_MM 1
84#define SIM_CRB 0xfffa00
85#endif
86/* end not included in ram_init.h */
87
88
89
90#define SIMCR SIM_VOLATILE_USHORT_POINTER(0x00 + SIM_CRB)
91                                /* Module Configuration Register */
92#define    EXOFF 0x8000         /*    External Clock Off */
93#define    FRZSW 0x4000         /*    Freeze Software Enable */
94#define    FRZBM 0x2000         /*    Freeze Bus Monitor Enable */
95#define    SLVEN 0x0800         /*    Factory Test Model Enabled (ro)*/
96#define    SHEN  0x0300         /*    Show Cycle Enable */
97#define    SUPV  0x0080         /*    Supervisor/Unrestricted Data Space */
98#define    MM    0x0040         /*    Module Mapping */
99#define    IARB  0x000f         /*    Interrupt Arbitration Field */
100
101
102
103#define SIMTR SIM_VOLATILE_USHORT_POINTER(0x02 + SIM_CRB)
104                                /* SIM Test Register */
105/* Used only for factor testing */
106
107
108
109#define SYNCR SIM_VOLATILE_USHORT_POINTER(0x04 + SIM_CRB)
110                                /* Clock Synthesizer Control Register */
111#define    VCO      0x8000      /*    Frequency Control (VCO) */
112#define    PRESCALE 0x4000      /*    Frequency Control Bit (Prescale) */
113#define    COUNTER  0x3f00      /*    Frequency Control Counter */
114#define    EDIV     0x0080      /*    ECLK Divide Rate */
115#define    SLIMP    0x0010      /*    Limp Mode Status */
116#define    SLOCK    0x0008      /*    Synthesizer Lock */
117#define    RSTEN    0x0004      /*    Reset Enable */
118#define    STSIM    0x0002      /*    Stop Mode SIM Clock */
119#define    STEXT    0x0001      /*    Stop Mode External Clock */
120
121
122
123#define RSR SIM_VOLATILE_UCHAR_POINTER(0x07 + SIM_CRB)
124                                /* Reset Status Register */
125#define    EXT   0x0080         /*    External Reset */
126#define    POW   0x0040         /*    Power-On Reset */
127#define    SW    0x0020         /*    Software Watchdog Reset */
128#define    DBF   0x0010         /*    Double Bus Fault Reset */
129#define    LOC   0x0004         /*    Loss of Clock Reset */
130#define    SYS   0x0002         /*    System Reset */
131#define    TST   0x0001         /*    Test Submodule Reset */
132
133
134
135#define SIMTRE SIM_VOLATILE_USHORT_POINTER(0x08 + SIM_CRB)
136                                /* System Integration Test Register */
137/* Used only for factor testing */
138
139
140
141#define PORTE0 SIM_VOLATILE_UCHAR_POINTER(0x11 + SIM_CRB)
142#define PORTE1 SIM_VOLATILE_UCHAR_POINTER(0x13 + SIM_CRB)
143                                /* Port E Data Register */
144#define DDRE SIM_VOLATILE_UCHAR_POINTER(0x15 + SIM_CRB)
145                                /* Port E Data Direction Register */
146#define PEPAR SIM_VOLATILE_UCHAR_POINTER(0x17 + SIM_CRB)
147                                /* Port E Pin Assignment Register */
148/* Any bit cleared (zero) defines the corresponding pin to be an I/O
149   pin. Any bit set defines the corresponding pin to be a bus control
150   signal. */
151
152
153
154#define PORTF0 SIM_VOLATILE_UCHAR_POINTER(0x19 + SIM_CRB)
155#define PORTF1 SIM_VOLATILE_UCHAR_POINTER(0x1b + SIM_CRB)
156                                /* Port F Data Register */
157#define DDRF SIM_VOLATILE_UCHAR_POINTER(0x1d + SIM_CRB)
158                                /* Port E Data Direction Register */
159#define PFPAR SIM_VOLATILE_UCHAR_POINTER(0x1f + SIM_CRB)
160/* Any bit cleared (zero) defines the corresponding pin to be an I/O
161   pin. Any bit set defines the corresponding pin to be a bus control
162   signal. */
163
164
165
166#define SYPCR SIM_VOLATILE_UCHAR_POINTER(0x21 + SIM_CRB)
167/* !!! can write to only once after reset !!! */
168                                /* System Protection Control Register */
169#define    SWE   0x80           /*    Software Watch Enable */
170#define    SWP   0x40           /*    Software Watchdog Prescale */
171#define    SWT   0x30           /*    Software Watchdog Timing */
172#define    HME   0x08           /*    Halt Monitor Enable */
173#define    BME   0x04           /*    Bus Monitor External Enable */
174#define    BMT   0x03           /*    Bus Monitor Timing */
175
176
177
178#define PICR SIM_VOLATILE_USHORT_POINTER(0x22 + SIM_CRB)
179                                /* Periodic Interrupt Control Reg. */
180#define    PIRQL 0x0700         /*    Periodic Interrupt Request Level */
181#define    PIV   0x00ff         /*    Periodic Interrupt Level */
182
183
184
185#define PITR SIM_VOLATILE_USHORT_POINTER(0x24 + SIM_CRB)
186                                /* Periodic Interrupt Timer Register */
187#define    PTP   0x0100         /*    Periodic Timer Prescaler Control */
188#define    PITM  0x00ff         /*    Periodic Interrupt Timing Modulus */
189
190
191
192#define SWSR SIM_VOLATILE_UCHAR_POINTER(0x27 + SIM_CRB)
193                                /* Software Service Register */
194/* write 0x55 then 0xaa to service the software watchdog */
195
196
197
198#define TSTMSRA SIM_VOLATILE_USHORT_POINTER(0x30 + SIM_CRB)
199                                /* Test Module Master Shift A */
200#define TSTMSRB SIM_VOLATILE_USHORT_POINTER(0x32 + SIM_CRB)
201                                /* Test Module Master Shift A */
202#define TSTSC SIM_VOLATILE_USHORT_POINTER(0x34 + SIM_CRB)
203                                /* Test Module Shift Count */
204#define TSTRC SIM_VOLATILE_USHORT_POINTER(0x36 + SIM_CRB)
205                                /* Test Module Repetition Counter */
206#define CREG SIM_VOLATILE_USHORT_POINTER(0x38 + SIM_CRB)
207                                /* Test Module Control */
208#define DREG SIM_VOLATILE_USHORT_POINTER(0x3a + SIM_CRB)
209                                /* Test Module Distributed */
210/* Used only for factor testing */
211
212
213
214#define PORTC SIM_VOLATILE_UCHAR_POINTER(0x41 + SIM_CRB)
215                                /* Port C Data */
216
217
218
219#define CSPAR0 SIM_VOLATILE_USHORT_POINTER(0x44 + SIM_CRB)
220                                /* Chip Select Pin Assignment
221                                   Resgister 0 */
222/* CSPAR0 contains seven two-bit fields that determine the functions
223   of corresponding chip-select pins. CSPAR0[15:14] are not
224   used. These bits always read zero; write have no effect. CSPAR0 bit
225   1 always reads one; writes to CSPAR0 bit 1 have no effect. */
226#define CSPAR1 SIM_VOLATILE_USHORT_POINTER(0x46 + SIM_CRB)
227                                /* Chip Select Pin Assignment
228                                   Register 1 */
229/* CSPAR1 contains five two-bit fields that determine the finctions of
230   corresponding chip-select pins. CSPAR1[15:10] are not used. These
231   bits always read zero; writes have no effect. */
232/*
233 *
234 *                      Bit Field  |  Description
235 *                     ------------+---------------
236 *                         00      | Discrete Output
237 *                         01      | Alternate Function
238 *                         10      | Chip Select (8-bit port)
239 *                         11      | Chip Select (16-bit port)
240 */
241#define DisOut 0x0
242#define AltFun 0x1
243#define CS8bit 0x2
244#define CS16bit 0x3
245/*
246 *
247 * CSPARx Field    |Chip Select Signal  |  Alternate Signal  |  Discrete Output
248 *-----------------+--------------------+--------------------+---------------*/
249#define CS_5    12 /*     !CS5          |         FC2        |       PC2     */
250#define CS_4    10 /*     !CS4          |         FC1        |       PC1     */
251#define CS_3     8 /*     !CS3          |         FC0        |       PC0     */
252#define CS_2     6 /*     !CS2          |       !BGACK       |               */
253#define CS_1     4 /*     !CS1          |         !BG        |               */
254#define CS_0     2 /*     !CS0          |         !BR        |               */
255#define CSBOOT   0 /*     !CSBOOT       |                    |               */
256/*                 |                    |                    |               */
257#define CS_10    8 /*     !CS10         |       ADDR23       |      ECLK     */
258#define CS_9     6 /*     !CS9          |       ADDR22       |       PC6     */
259#define CS_8     4 /*     !CS8          |       ADDR21       |       PC5     */
260#define CS_7     2 /*     !CS7          |       ADDR20       |       PC4     */
261#define CS_6     0 /*     !CS6          |       ADDR19       |       PC3     */
262
263#define BS_2K 0x0
264#define BS_8K 0x1
265#define BS_16K 0x2
266#define BS_64K 0x3
267#define BS_128K 0x4
268#define BS_256K 0x5
269#define BS_512K 0x6
270#define BS_1M 0x7
271
272#define CSBARBT SIM_VOLATILE_USHORT_POINTER(0x48 + SIM_CRB)
273#define CSBAR0 SIM_VOLATILE_USHORT_POINTER(0x4c + SIM_CRB)
274#define CSBAR1 SIM_VOLATILE_USHORT_POINTER(0x50 + SIM_CRB)
275#define CSBAR2 SIM_VOLATILE_USHORT_POINTER(0x54 + SIM_CRB)
276#define CSBAR3 SIM_VOLATILE_USHORT_POINTER(0x58 + SIM_CRB)
277#define CSBAR4 SIM_VOLATILE_USHORT_POINTER(0x5c + SIM_CRB)
278#define CSBAR5 SIM_VOLATILE_USHORT_POINTER(0x60 + SIM_CRB)
279#define CSBAR6 SIM_VOLATILE_USHORT_POINTER(0x64 + SIM_CRB)
280#define CSBAR7 SIM_VOLATILE_USHORT_POINTER(0x68 + SIM_CRB)
281#define CSBAR8 SIM_VOLATILE_USHORT_POINTER(0x6c + SIM_CRB)
282#define CSBAR9 SIM_VOLATILE_USHORT_POINTER(0x70 + SIM_CRB)
283#define CSBAR10 SIM_VOLATILE_USHORT_POINTER(0x74 + SIM_CRB)
284
285#define MODE 0x8000
286#define Disable 0
287#define LowerByte 0x2000
288#define UpperByte 0x4000
289#define BothBytes 0x6000
290#define ReadOnly 0x0800
291#define WriteOnly 0x1000
292#define ReadWrite 0x1800
293#define SyncAS 0x0
294#define SyncDS 0x0400
295
296#define WaitStates_0 (0x0 << 6)
297#define WaitStates_1 (0x1 << 6)
298#define WaitStates_2 (0x2 << 6)
299#define WaitStates_3 (0x3 << 6)
300#define WaitStates_4 (0x4 << 6)
301#define WaitStates_5 (0x5 << 6)
302#define WaitStates_6 (0x6 << 6)
303#define WaitStates_7 (0x7 << 6)
304#define WaitStates_8 (0x8 << 6)
305#define WaitStates_9 (0x9 << 6)
306#define WaitStates_10 (0xa << 6)
307#define WaitStates_11 (0xb << 6)
308#define WaitStates_12 (0xc << 6)
309#define WaitStates_13 (0xd << 6)
310#define FastTerm (0xe << 6)
311#define External (0xf << 6)
312
313#define CPUSpace (0x0 << 4)
314#define UserSpace (0x1 << 4)
315#define SupSpace (0x2 << 4)
316#define UserSupSpace (0x3 << 4)
317
318#define IPLevel_any 0x0
319#define IPLevel_1 0x2
320#define IPLevel_2 0x4
321#define IPLevel_3 0x6
322#define IPLevel_4 0x8
323#define IPLevel_5 0xa
324#define IPLevel_6 0xc
325#define IPLevel_7 0xe
326
327#define AVEC 1
328
329#define CSORBT SIM_VOLATILE_USHORT_POINTER(0x4a + SIM_CRB)
330#define CSOR0 SIM_VOLATILE_USHORT_POINTER(0x4e + SIM_CRB)
331#define CSOR1 SIM_VOLATILE_USHORT_POINTER(0x52 + SIM_CRB)
332#define CSOR2 SIM_VOLATILE_USHORT_POINTER(0x56 + SIM_CRB)
333#define CSOR3 SIM_VOLATILE_USHORT_POINTER(0x5a + SIM_CRB)
334#define CSOR4 SIM_VOLATILE_USHORT_POINTER(0x5e + SIM_CRB)
335#define CSOR5 SIM_VOLATILE_USHORT_POINTER(0x62 + SIM_CRB)
336#define CSOR6 SIM_VOLATILE_USHORT_POINTER(0x66 + SIM_CRB)
337#define CSOR7 SIM_VOLATILE_USHORT_POINTER(0x6a + SIM_CRB)
338#define CSOR8 SIM_VOLATILE_USHORT_POINTER(0x6e + SIM_CRB)
339#define CSOR9 SIM_VOLATILE_USHORT_POINTER(0x72 + SIM_CRB)
340#define CSOR10 SIM_VOLATILE_USHORT_POINTER(0x76 + SIM_CRB)
341
342#endif /* _SIM_h_ */
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