[12710a56] | 1 | /* |
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| 2 | *------------------------------------------------------------------- |
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| 3 | * |
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| 4 | * QSM -- Queued Serial Module |
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| 5 | * |
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| 6 | * The QSM contains two serial interfaces: (a) the queued serial |
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| 7 | * peripheral interface (QSPI) and the serial communication interface |
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| 8 | * (SCI). The QSPI provides peripheral expansion and/or interprocessor |
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| 9 | * communication through a full-duplex, synchronous, three-wire bus. A |
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| 10 | * self contained RAM queue permits serial data transfers without CPU |
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| 11 | * intervention and automatic continuous sampling. The SCI provides a |
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| 12 | * standard non-return to zero mark/space format with wakeup functions |
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| 13 | * to allow the CPU to run uninterrupted until woken |
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| 14 | * |
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| 15 | * For more information, refer to Motorola's "Modular Microcontroller |
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| 16 | * Family Queued Serial Module Reference Manual" (Motorola document |
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| 17 | * QSMRM/AD). |
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| 18 | * |
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[a8f1432b] | 19 | * This file was created by John S. Gwynne to support Motorola's 68332 MCU. |
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[12710a56] | 20 | * |
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| 21 | * Redistribution and use in source and binary forms are permitted |
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| 22 | * provided that the following conditions are met: |
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| 23 | * 1. Redistribution of source code and documentation must retain |
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| 24 | * the above authorship, this list of conditions and the |
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| 25 | * following disclaimer. |
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| 26 | * 2. The name of the author may not be used to endorse or promote |
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| 27 | * products derived from this software without specific prior |
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| 28 | * written permission. |
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| 29 | * |
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| 30 | * This software is provided "AS IS" without warranty of any kind, |
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| 31 | * either expressed or implied, including, but not limited to, the |
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| 32 | * implied warranties of merchantability, title and fitness for a |
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| 33 | * particular purpose. |
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| 34 | * |
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| 35 | *------------------------------------------------------------------ |
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| 36 | * |
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| 37 | * $Id$ |
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| 38 | */ |
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| 39 | |
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[fa6b0f5] | 40 | #ifndef _RTEMS_M68K_QSM_H |
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| 41 | #define _RTEMS_M68K_QSM_H |
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[12710a56] | 42 | |
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| 43 | /* SAM-- shift and mask */ |
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| 44 | #undef SAM |
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| 45 | #define SAM(a,b,c) ((a << b) & c) |
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| 46 | |
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| 47 | |
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| 48 | /* QSM_CRB (QSM Control Register Block) base address of the QSM |
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| 49 | control registers */ |
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| 50 | #if SIM_MM == 0 |
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| 51 | #define QSM_CRB 0x7ffc00 |
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| 52 | #else |
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| 53 | #undef SIM_MM |
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| 54 | #define SIM_MM 1 |
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| 55 | #define QSM_CRB 0xfffc00 |
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| 56 | #endif |
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| 57 | |
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| 58 | |
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| 59 | #define QSMCR (volatile unsigned short int * const)(0x00 + QSM_CRB) |
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| 60 | /* QSM Configuration Register */ |
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| 61 | #define STOP 0x8000 /* Stop Enable */ |
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| 62 | #define FRZ 0x6000 /* Freeze Control */ |
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| 63 | #define SUPV 0x0080 /* Supervisor/Unrestricted */ |
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| 64 | #define IARB 0x000f /* Inerrupt Arbitration */ |
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| 65 | |
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| 66 | |
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| 67 | #define QTEST (volatile unsigned short int * const)(0x02 + QSM_CRB) |
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| 68 | /* QSM Test Register */ |
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| 69 | /* Used only for factor testing */ |
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| 70 | |
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| 71 | |
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| 72 | #define QILR (volatile unsigned char * const)(0x04 + QSM_CRB) |
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| 73 | /* QSM Interrupt Level Register */ |
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| 74 | #define ILQSPI 0x38 /* Interrupt Level for QSPI */ |
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| 75 | #define ILSCI 0x07 /* Interrupt Level for SCI */ |
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| 76 | |
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| 77 | |
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| 78 | #define QIVR (volatile unsigned char * const)(0x05 + QSM_CRB) |
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| 79 | /* QSM Interrupt Vector Register */ |
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| 80 | #define INTV 0xff /* Interrupt Vector Number */ |
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| 81 | |
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| 82 | |
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| 83 | #define SCCR0 (volatile unsigned short int * const)(0x08 + QSM_CRB) |
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| 84 | /* SCI Control Register 0 */ |
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| 85 | #define SCBR 0x1fff /* SCI Baud Rate */ |
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| 86 | |
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| 87 | |
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| 88 | #define SCCR1 (volatile unsigned short int * const)(0x0a + QSM_CRB) |
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| 89 | /* SCI Control Register 1 */ |
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| 90 | #define LOOPS 0x4000 /* Loop Mode */ |
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| 91 | #define WOMS 0x2000 /* Wired-OR Mode for SCI Pins */ |
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| 92 | #define ILT 0x1000 /* Idle-Line Detect Type */ |
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| 93 | #define PT 0x0800 /* Parity Type */ |
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| 94 | #define PE 0x0400 /* Parity Enable */ |
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| 95 | #define M 0x0200 /* Mode Select */ |
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| 96 | #define WAKE 0x0100 /* Wakeup by Address Mark */ |
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| 97 | #define TIE 0x0080 /* Transmit Complete Interrupt Enable */ |
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| 98 | #define TCIE 0x0040 /* Transmit Complete Interrupt Enable */ |
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| 99 | #define RIE 0x0020 /* Receiver Interrupt Enable */ |
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| 100 | #define ILIE 0x0010 /* Idle-Line Interrupt Enable */ |
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| 101 | #define TE 0x0008 /* Transmitter Enable */ |
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| 102 | #define RE 0x0004 /* Receiver Enable */ |
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| 103 | #define RWU 0x0002 /* Receiver Wakeup */ |
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| 104 | #define SBK 0x0001 /* Send Break */ |
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| 105 | |
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| 106 | |
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| 107 | #define SCSR (volatile unsigned short int * const)(0x0c + QSM_CRB) |
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| 108 | /* SCI Status Register */ |
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| 109 | #define TDRE 0x0100 /* Transmit Data Register Empty */ |
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| 110 | #define TC 0x0080 /* Transmit Complete */ |
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| 111 | #define RDRF 0x0040 /* Receive Data Register Full */ |
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| 112 | #define RAF 0x0020 /* Receiver Active */ |
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| 113 | #define IDLE 0x0010 /* Idle-Line Detected */ |
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| 114 | #define OR 0x0008 /* Overrun Error */ |
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| 115 | #define NF 0x0004 /* Noise Error Flag */ |
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| 116 | #define FE 0x0002 /* Framing Error */ |
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| 117 | #define PF 0x0001 /* Parity Error */ |
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| 118 | |
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| 119 | |
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| 120 | #define SCDR (volatile unsigned short int * const)(0x0e + QSM_CRB) |
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| 121 | /* SCI Data Register */ |
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| 122 | |
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| 123 | |
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| 124 | #define PORTQS (volatile unsigned char * const)(0x15 + QSM_CRB) |
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| 125 | /* Port QS Data Register */ |
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| 126 | |
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| 127 | #define PQSPAR (volatile unsigned char * const)(0x16 + QSM_CRB) |
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| 128 | /* PORT QS Pin Assignment Rgister */ |
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| 129 | /* Any bit cleared (zero) defines the corresponding pin to be an I/O |
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| 130 | pin. Any bit set defines the corresponding pin to be a QSPI |
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| 131 | signal. */ |
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| 132 | /* note: PQS2 is a digital I/O pin unless the SPI is enabled in which |
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| 133 | case it becomes the SPI serial clock SCK. */ |
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| 134 | /* note: PQS7 is a digital I/O pin unless the SCI transmitter is |
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| 135 | enabled in which case it becomes the SCI serial output TxD. */ |
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| 136 | #define QSMFun 0x0 |
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| 137 | #define QSMDis 0x1 |
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| 138 | /* |
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| 139 | * PQSPAR Field | QSM Function | Discrete I/O pin |
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| 140 | *------------------+--------------+------------------ */ |
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| 141 | #define PQSPA0 0 /* MISO | PQS0 */ |
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| 142 | #define PQSPA1 1 /* MOSI | PQS1 */ |
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| 143 | #define PQSPA2 2 /* SCK | PQS2 (see note)*/ |
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| 144 | #define PQSPA3 3 /* PCSO/!SS | PQS3 */ |
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| 145 | #define PQSPA4 4 /* PCS1 | PQS4 */ |
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| 146 | #define PQSPA5 5 /* PCS2 | PQS5 */ |
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| 147 | #define PQSPA6 6 /* PCS3 | PQS6 */ |
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| 148 | #define PQSPA7 7 /* TxD | PQS7 (see note)*/ |
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| 149 | |
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| 150 | |
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| 151 | #define DDRQS (volatile unsigned char * const)(0x17 + QSM_CRB) |
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| 152 | /* PORT QS Data Direction Register */ |
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| 153 | /* Clearing a bit makes the corresponding pin an input; setting a bit |
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| 154 | makes the pin an output. */ |
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| 155 | |
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| 156 | |
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| 157 | #define SPCR0 (volatile unsigned short int * const)(0x18 + QSM_CRB) |
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| 158 | /* QSPI Control Register 0 */ |
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| 159 | #define MSTR 0x8000 /* Master/Slave Mode Select */ |
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| 160 | #define WOMQ 0x4000 /* Wired-OR Mode for QSPI Pins */ |
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| 161 | #define BITS 0x3c00 /* Bits Per Transfer */ |
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| 162 | #define CPOL 0x0200 /* Clock Polarity */ |
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| 163 | #define CPHA 0x0100 /* Clock Phase */ |
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| 164 | #define SPBR 0x00ff /* Serial Clock Baud Rate */ |
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| 165 | |
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| 166 | |
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| 167 | #define SPCR1 (volatile unsigned short int * const)(0x1a + QSM_CRB) |
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| 168 | /* QSPI Control Register 1 */ |
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| 169 | #define SPE 0x8000 /* QSPI Enable */ |
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| 170 | #define DSCKL 0x7f00 /* Delay before SCK */ |
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| 171 | #define DTL 0x00ff /* Length of Delay after Transfer */ |
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| 172 | |
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| 173 | |
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| 174 | #define SPCR2 (volatile unsigned short int * const)(0x1c + QSM_CRB) |
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| 175 | /* QSPI Control Register 2 */ |
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| 176 | #define SPIFIE 0x8000 /* SPI Finished Interrupt Enable */ |
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| 177 | #define WREN 0x4000 /* Wrap Enable */ |
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| 178 | #define WRTO 0x2000 /* Wrap To */ |
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| 179 | #define ENDQP 0x0f00 /* Ending Queue Pointer */ |
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| 180 | #define NEWQP 0x000f /* New Queue Pointer Value */ |
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| 181 | |
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| 182 | |
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| 183 | #define SPCR3 (volatile unsigned char * const)(0x1e + QSM_CRB) |
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| 184 | /* QSPI Control Register 3 */ |
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| 185 | #define LOOPQ 0x0400 /* QSPI Loop Mode */ |
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| 186 | #define HMIE 0x0200 /* HALTA and MODF Interrupt Enable */ |
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| 187 | #define HALT 0x0100 /* Halt */ |
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| 188 | |
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| 189 | |
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| 190 | #define SPSR (volatile unsigned char * const)(0x1f + QSM_CRB) |
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| 191 | /* QSPI Status Register */ |
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| 192 | #define SPIF 0x0080 /* QSPI Finished Flag */ |
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| 193 | #define MODF 0x0040 /* Mode Fault Flag */ |
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| 194 | #define HALTA 0x0020 /* Halt Acknowlwdge Flag */ |
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| 195 | #define CPTQP x0000f /* Completed Queue Pointer */ |
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| 196 | |
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| 197 | #define QSPIRR (volatile unsigned char * const)(0x100 + QSM_CRB) |
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| 198 | /* QSPI Receive Data RAM */ |
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| 199 | #define QSPITR (volatile unsigned char * const)(0x120 + QSM_CRB) |
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| 200 | /* QSPI Transmit Data RAM */ |
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| 201 | #define QSPIcR (volatile unsigned char * const)(0x140 + QSM_CRB) |
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| 202 | /* QSPI Command RAM */ |
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| 203 | |
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[fa6b0f5] | 204 | #endif /* _RTEMS_M68K_QSM_H */ |
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