Context Navigation

m68360.h @ e354eb4f

4.115

Last change on this file since e354eb4f was 65c6425, checked in by Joel Sherrill <joel.sherrill@…>, on 05/03/12 at 17:24:46

Remove CVS Id Strings (manual edits after script)

These modifications were required by hand after running the script.
In some cases, the file names did not match patterns. In others,
the format of the file did not match any common patterns.

Property mode set to 100644

File size: 27.5 KB

Line
1	/*
2	**************************************************************************
3	**************************************************************************
4
5	MOTOROLA MC68360 QUAD INTEGRATED COMMUNICATIONS CONTROLLER (QUICC)
6
7	HARDWARE DECLARATIONS
8
9
10	Submitted By:
11
12	W. Eric Norum
13	Saskatchewan Accelerator Laboratory
14	University of Saskatchewan
15	107 North Road
16	Saskatoon, Saskatchewan, CANADA
17	S7N 5C6
18
19	eric@skatter.usask.ca
20
21	**************************************************************************
22	**************************************************************************
23	*/
24
25	#ifndef _RTEMS_M68K_M68360_H
26	#define _RTEMS_M68K_M68360_H
27
28	/*
29	*************************************************************************
30	* REGISTER SUBBLOCKS *
31	*************************************************************************
32	*/
33
34	/*
35	* Memory controller registers
36	*/
37	typedef struct m360MEMCRegisters_ {
38	unsigned long br;
39	unsigned long or;
40	unsigned long _pad[2];
41	} m360MEMCRegisters_t;
42
43	/*
44	* Serial Communications Controller registers
45	*/
46	typedef struct m360SCCRegisters_ {
47	unsigned long gsmr_l;
48	unsigned long gsmr_h;
49	unsigned short psmr;
50	unsigned short _pad0;
51	unsigned short todr;
52	unsigned short dsr;
53	unsigned short scce;
54	unsigned short _pad1;
55	unsigned short sccm;
56	unsigned char _pad2;
57	unsigned char sccs;
58	unsigned long _pad3[2];
59	} m360SCCRegisters_t;
60
61	/*
62	* Serial Management Controller registers
63	*/
64	typedef struct m360SMCRegisters_ {
65	unsigned short _pad0;
66	unsigned short smcmr;
67	unsigned short _pad1;
68	unsigned char smce;
69	unsigned char _pad2;
70	unsigned short _pad3;
71	unsigned char smcm;
72	unsigned char _pad4;
73	unsigned long _pad5;
74	} m360SMCRegisters_t;
75
76
77	/*
78	*************************************************************************
79	* Miscellaneous Parameters *
80	*************************************************************************
81	*/
82	typedef struct m360MiscParms_ {
83	unsigned short rev_num;
84	unsigned short _res1;
85	unsigned long _res2;
86	unsigned long _res3;
87	} m360MiscParms_t;
88
89	/*
90	*************************************************************************
91	* RISC Timers *
92	*************************************************************************
93	*/
94	typedef struct m360TimerParms_ {
95	unsigned short tm_base;
96	unsigned short _tm_ptr;
97	unsigned short _r_tmr;
98	unsigned short _r_tmv;
99	unsigned long tm_cmd;
100	unsigned long tm_cnt;
101	} m360TimerParms_t;
102
103	/*
104	* RISC Controller Configuration Register (RCCR)
105	* All other bits in this register are either reserved or
106	* used only with a Motorola-supplied RAM microcode packge.
107	*/
108	#define M360_RCCR_TIME (1<<15) /* Enable timer */
109	#define M360_RCCR_TIMEP(x) ((x)<<8) /* Timer period */
110
111	/*
112	* Command register
113	* Set up this register before issuing a M360_CR_OP_SET_TIMER command.
114	*/
115	#define M360_TM_CMD_V (1<<31) /* Set to enable timer */
116	#define M360_TM_CMD_R (1<<30) /* Set for automatic restart */
117	#define M360_TM_CMD_TIMER(x) ((x)<<16) /* Select timer */
118	#define M360_TM_CMD_PERIOD(x) (x) /* Timer period (16 bits) */
119
120	/*
121	*************************************************************************
122	* DMA Controllers *
123	*************************************************************************
124	*/
125	typedef struct m360IDMAparms_ {
126	unsigned short ibase;
127	unsigned short ibptr;
128	unsigned long _istate;
129	unsigned long _itemp;
130	} m360IDMAparms_t;
131
132	/*
133	*************************************************************************
134	* Serial Communication Controllers *
135	*************************************************************************
136	*/
137	typedef struct m360SCCparms_ {
138	unsigned short rbase;
139	unsigned short tbase;
140	unsigned char rfcr;
141	unsigned char tfcr;
142	unsigned short mrblr;
143	unsigned long _rstate;
144	unsigned long _pad0;
145	unsigned short _rbptr;
146	unsigned short _pad1;
147	unsigned long _pad2;
148	unsigned long _tstate;
149	unsigned long _pad3;
150	unsigned short _tbptr;
151	unsigned short _pad4;
152	unsigned long _pad5;
153	unsigned long _rcrc;
154	unsigned long _tcrc;
155	union {
156	struct {
157	unsigned long _res0;
158	unsigned long _res1;
159	unsigned short max_idl;
160	unsigned short _idlc;
161	unsigned short brkcr;
162	unsigned short parec;
163	unsigned short frmec;
164	unsigned short nosec;
165	unsigned short brkec;
166	unsigned short brklen;
167	unsigned short uaddr[2];
168	unsigned short _rtemp;
169	unsigned short toseq;
170	unsigned short character[8];
171	unsigned short rccm;
172	unsigned short rccr;
173	unsigned short rlbc;
174	} uart;
175	struct {
176	unsigned long crc_p;
177	unsigned long crc_c;
178	} transparent;
179
180	} un;
181	} m360SCCparms_t;
182
183	typedef struct m360SCCENparms_ {
184	unsigned short rbase;
185	unsigned short tbase;
186	unsigned char rfcr;
187	unsigned char tfcr;
188	unsigned short mrblr;
189	unsigned long _rstate;
190	unsigned long _pad0;
191	unsigned short _rbptr;
192	unsigned short _pad1;
193	unsigned long _pad2;
194	unsigned long _tstate;
195	unsigned long _pad3;
196	unsigned short _tbptr;
197	unsigned short _pad4;
198	unsigned long _pad5;
199	unsigned long _rcrc;
200	unsigned long _tcrc;
201	union {
202	struct {
203	unsigned long _res0;
204	unsigned long _res1;
205	unsigned short max_idl;
206	unsigned short _idlc;
207	unsigned short brkcr;
208	unsigned short parec;
209	unsigned short frmec;
210	unsigned short nosec;
211	unsigned short brkec;
212	unsigned short brklen;
213	unsigned short uaddr[2];
214	unsigned short _rtemp;
215	unsigned short toseq;
216	unsigned short character[8];
217	unsigned short rccm;
218	unsigned short rccr;
219	unsigned short rlbc;
220	} uart;
221	struct {
222	unsigned long c_pres;
223	unsigned long c_mask;
224	unsigned long crcec;
225	unsigned long alec;
226	unsigned long disfc;
227	unsigned short pads;
228	unsigned short ret_lim;
229	unsigned short _ret_cnt;
230	unsigned short mflr;
231	unsigned short minflr;
232	unsigned short maxd1;
233	unsigned short maxd2;
234	unsigned short _maxd;
235	unsigned short dma_cnt;
236	unsigned short _max_b;
237	unsigned short gaddr1;
238	unsigned short gaddr2;
239	unsigned short gaddr3;
240	unsigned short gaddr4;
241	unsigned long _tbuf0data0;
242	unsigned long _tbuf0data1;
243	unsigned long _tbuf0rba0;
244	unsigned long _tbuf0crc;
245	unsigned short _tbuf0bcnt;
246	unsigned short paddr_h;
247	unsigned short paddr_m;
248	unsigned short paddr_l;
249	unsigned short p_per;
250	unsigned short _rfbd_ptr;
251	unsigned short _tfbd_ptr;
252	unsigned short _tlbd_ptr;
253	unsigned long _tbuf1data0;
254	unsigned long _tbuf1data1;
255	unsigned long _tbuf1rba0;
256	unsigned long _tbuf1crc;
257	unsigned short _tbuf1bcnt;
258	unsigned short _tx_len;
259	unsigned short iaddr1;
260	unsigned short iaddr2;
261	unsigned short iaddr3;
262	unsigned short iaddr4;
263	unsigned short _boff_cnt;
264	unsigned short taddr_h;
265	unsigned short taddr_m;
266	unsigned short taddr_l;
267	} ethernet;
268	struct {
269	unsigned long crc_p;
270	unsigned long crc_c;
271	} transparent;
272	} un;
273	} m360SCCENparms_t;
274
275	/*
276	* Receive and transmit function code register bits
277	* These apply to the function code registers of all devices, not just SCC.
278	*/
279	#define M360_RFCR_MOT (1<<4)
280	#define M360_RFCR_DMA_SPACE 0x8
281	#define M360_TFCR_MOT (1<<4)
282	#define M360_TFCR_DMA_SPACE 0x8
283
284	/*
285	*************************************************************************
286	* Serial Management Controllers *
287	*************************************************************************
288	*/
289	typedef struct m360SMCparms_ {
290	unsigned short rbase;
291	unsigned short tbase;
292	unsigned char rfcr;
293	unsigned char tfcr;
294	unsigned short mrblr;
295	unsigned long _rstate;
296	unsigned long _pad0;
297	unsigned short _rbptr;
298	unsigned short _pad1;
299	unsigned long _pad2;
300	unsigned long _tstate;
301	unsigned long _pad3;
302	unsigned short _tbptr;
303	unsigned short _pad4;
304	unsigned long _pad5;
305	union {
306	struct {
307	unsigned short max_idl;
308	unsigned short _pad0;
309	unsigned short brklen;
310	unsigned short brkec;
311	unsigned short brkcr;
312	unsigned short _r_mask;
313	} uart;
314	struct {
315	unsigned short _pad0[5];
316	} transparent;
317	} un;
318	} m360SMCparms_t;
319
320	/*
321	* Mode register
322	*/
323	#define M360_SMCMR_CLEN(x) ((x)<<11) /* Character length */
324	#define M360_SMCMR_2STOP (1<<10) /* 2 stop bits */
325	#define M360_SMCMR_PARITY (1<<9) /* Enable parity */
326	#define M360_SMCMR_EVEN (1<<8) /* Even parity */
327	#define M360_SMCMR_SM_GCI (0<<4) /* GCI Mode */
328	#define M360_SMCMR_SM_UART (2<<4) /* UART Mode */
329	#define M360_SMCMR_SM_TRANSPARENT (3<<4) /* Transparent Mode */
330	#define M360_SMCMR_DM_LOOPBACK (1<<2) /* Local loopback mode */
331	#define M360_SMCMR_DM_ECHO (2<<2) /* Echo mode */
332	#define M360_SMCMR_TEN (1<<1) /* Enable transmitter */
333	#define M360_SMCMR_REN (1<<0) /* Enable receiver */
334
335	/*
336	* Event and mask registers (SMCE, SMCM)
337	*/
338	#define M360_SMCE_BRK (1<<4)
339	#define M360_SMCE_BSY (1<<2)
340	#define M360_SMCE_TX (1<<1)
341	#define M360_SMCE_RX (1<<0)
342
343	/*
344	*************************************************************************
345	* Serial Peripheral Interface *
346	*************************************************************************
347	*/
348	typedef struct m360SPIparms_ {
349	unsigned short rbase;
350	unsigned short tbase;
351	unsigned char rfcr;
352	unsigned char tfcr;
353	unsigned short mrblr;
354	unsigned long _rstate;
355	unsigned long _pad0;
356	unsigned short _rbptr;
357	unsigned short _pad1;
358	unsigned long _pad2;
359	unsigned long _tstate;
360	unsigned long _pad3;
361	unsigned short _tbptr;
362	unsigned short _pad4;
363	unsigned long _pad5;
364	} m360SPIparms_t;
365
366	/*
367	* Mode register (SPMODE)
368	*/
369	#define M360_SPMODE_LOOP (1<<14) /* Local loopback mode */
370	#define M360_SPMODE_CI (1<<13) /* Clock invert */
371	#define M360_SPMODE_CP (1<<12) /* Clock phase */
372	#define M360_SPMODE_DIV16 (1<<11) /* Divide BRGCLK by 16 */
373	#define M360_SPMODE_REV (1<<10) /* Reverse data */
374	#define M360_SPMODE_MASTER (1<<9) /* SPI is master */
375	#define M360_SPMODE_EN (1<<8) /* Enable SPI */
376	#define M360_SPMODE_CLEN(x) ((x)<<4) /* Character length */
377	#define M360_SPMODE_PM(x) (x) /* Prescaler modulus */
378
379	/*
380	* Mode register (SPCOM)
381	*/
382	#define M360_SPCOM_STR (1<<7) /* Start transmit */
383
384	/*
385	* Event and mask registers (SPIE, SPIM)
386	*/
387	#define M360_SPIE_MME (1<<5) /* Multi-master error */
388	#define M360_SPIE_TXE (1<<4) /* Tx error */
389	#define M360_SPIE_BSY (1<<2) /* Busy condition*/
390	#define M360_SPIE_TXB (1<<1) /* Tx buffer */
391	#define M360_SPIE_RXB (1<<0) /* Rx buffer */
392
393	/*
394	*************************************************************************
395	* SDMA (SCC, SMC, SPI) Buffer Descriptors *
396	*************************************************************************
397	*/
398	typedef struct m360BufferDescriptor_ {
399	unsigned short status;
400	unsigned short length;
401	volatile void *buffer;
402	} m360BufferDescriptor_t;
403
404	/*
405	* Bits in receive buffer descriptor status word
406	*/
407	#define M360_BD_EMPTY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
408	#define M360_BD_WRAP (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */
409	#define M360_BD_INTERRUPT (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */
410	#define M360_BD_LAST (1<<11) /* Ethernet, SPI */
411	#define M360_BD_CONTROL_CHAR (1<<11) /* SCC UART */
412	#define M360_BD_FIRST_IN_FRAME (1<<10) /* Ethernet */
413	#define M360_BD_ADDRESS (1<<10) /* SCC UART */
414	#define M360_BD_CONTINUOUS (1<<9) /* SCC UART, SMC UART, SPI */
415	#define M360_BD_MISS (1<<8) /* Ethernet */
416	#define M360_BD_IDLE (1<<8) /* SCC UART, SMC UART */
417	#define M360_BD_ADDRSS_MATCH (1<<7) /* SCC UART */
418	#define M360_BD_LONG (1<<5) /* Ethernet */
419	#define M360_BD_BREAK (1<<5) /* SCC UART, SMC UART */
420	#define M360_BD_NONALIGNED (1<<4) /* Ethernet */
421	#define M360_BD_FRAMING_ERROR (1<<4) /* SCC UART, SMC UART */
422	#define M360_BD_SHORT (1<<3) /* Ethernet */
423	#define M360_BD_PARITY_ERROR (1<<3) /* SCC UART, SMC UART */
424	#define M360_BD_CRC_ERROR (1<<2) /* Ethernet */
425	#define M360_BD_OVERRUN (1<<1) /* Ethernet, SCC UART, SMC UART, SPI */
426	#define M360_BD_COLLISION (1<<0) /* Ethernet */
427	#define M360_BD_CARRIER_LOST (1<<0) /* SCC UART */
428	#define M360_BD_MASTER_ERROR (1<<0) /* SPI */
429
430	/*
431	* Bits in transmit buffer descriptor status word
432	* Many bits have the same meaning as those in receiver buffer descriptors.
433	*/
434	#define M360_BD_READY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
435	#define M360_BD_PAD (1<<14) /* Ethernet */
436	#define M360_BD_CTS_REPORT (1<<11) /* SCC UART */
437	#define M360_BD_TX_CRC (1<<10) /* Ethernet */
438	#define M360_BD_DEFER (1<<9) /* Ethernet */
439	#define M360_BD_HEARTBEAT (1<<8) /* Ethernet */
440	#define M360_BD_PREAMBLE (1<<8) /* SCC UART, SMC UART */
441	#define M360_BD_LATE_COLLISION (1<<7) /* Ethernet */
442	#define M360_BD_NO_STOP_BIT (1<<7) /* SCC UART */
443	#define M360_BD_RETRY_LIMIT (1<<6) /* Ethernet */
444	#define M360_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) /* Ethernet */
445	#define M360_BD_UNDERRUN (1<<1) /* Ethernet, SPI */
446	#define M360_BD_CARRIER_LOST (1<<0) /* Ethernet */
447	#define M360_BD_CTS_LOST (1<<0) /* SCC UART */
448
449	/*
450	*************************************************************************
451	* IDMA Buffer Descriptors *
452	*************************************************************************
453	*/
454	typedef struct m360IDMABufferDescriptor_ {
455	unsigned short status;
456	unsigned short _pad;
457	unsigned long length;
458	void *source;
459	void *destination;
460	} m360IDMABufferDescriptor_t;
461
462	/*
463	*************************************************************************
464	* RISC Communication Processor Module Command Register (CR) *
465	*************************************************************************
466	*/
467	#define M360_CR_RST (1<<15) /* Reset communication processor */
468	#define M360_CR_OP_INIT_RX_TX (0<<8) /* SCC, SMC UART, SMC GCI, SPI */
469	#define M360_CR_OP_INIT_RX (1<<8) /* SCC, SMC UART, SPI */
470	#define M360_CR_OP_INIT_TX (2<<8) /* SCC, SMC UART, SPI */
471	#define M360_CR_OP_INIT_HUNT (3<<8) /* SCC, SMC UART */
472	#define M360_CR_OP_STOP_TX (4<<8) /* SCC, SMC UART */
473	#define M360_CR_OP_GR_STOP_TX (5<<8) /* SCC */
474	#define M360_CR_OP_INIT_IDMA (5<<8) /* IDMA */
475	#define M360_CR_OP_RESTART_TX (6<<8) /* SCC, SMC UART */
476	#define M360_CR_OP_CLOSE_RX_BD (7<<8) /* SCC, SMC UART, SPI */
477	#define M360_CR_OP_SET_GRP_ADDR (8<<8) /* SCC */
478	#define M360_CR_OP_SET_TIMER (8<<8) /* Timer */
479	#define M360_CR_OP_GCI_TIMEOUT (9<<8) /* SMC GCI */
480	#define M360_CR_OP_RESERT_BCS (10<<8) /* SCC */
481	#define M360_CR_OP_GCI_ABORT (10<<8) /* SMC GCI */
482	#define M360_CR_CHAN_SCC1 (0<<4) /* Channel selection */
483	#define M360_CR_CHAN_SCC2 (4<<4)
484	#define M360_CR_CHAN_SPI (5<<4)
485	#define M360_CR_CHAN_TIMER (5<<4)
486	#define M360_CR_CHAN_SCC3 (8<<4)
487	#define M360_CR_CHAN_SMC1 (9<<4)
488	#define M360_CR_CHAN_IDMA1 (9<<4)
489	#define M360_CR_CHAN_SCC4 (12<<4)
490	#define M360_CR_CHAN_SMC2 (13<<4)
491	#define M360_CR_CHAN_IDMA2 (13<<4)
492	#define M360_CR_FLG (1<<0) /* Command flag */
493
494	/*
495	*************************************************************************
496	* System Protection Control Register (SYPCR) *
497	*************************************************************************
498	*/
499	#define M360_SYPCR_SWE (1<<7) /* Software watchdog enable */
500	#define M360_SYPCR_SWRI (1<<6) /* Software watchdog reset select */
501	#define M360_SYPCR_SWT1 (1<<5) /* Software watchdog timing bit 1 */
502	#define M360_SYPCR_SWT0 (1<<4) /* Software watchdog timing bit 0 */
503	#define M360_SYPCR_DBFE (1<<3) /* Double bus fault monitor enable */
504	#define M360_SYPCR_BME (1<<2) /* Bus monitor external enable */
505	#define M360_SYPCR_BMT1 (1<<1) /* Bus monitor timing bit 1 */
506	#define M360_SYPCR_BMT0 (1<<0) /* Bus monitor timing bit 0 */
507
508	/*
509	*************************************************************************
510	* Memory Control Registers *
511	*************************************************************************
512	*/
513	#define M360_GMR_RCNT(x) ((x)<<24) /* Refresh count */
514	#define M360_GMR_RFEN (1<<23) /* Refresh enable */
515	#define M360_GMR_RCYC(x) ((x)<<21) /* Refresh cycle length */
516	#define M360_GMR_PGS(x) ((x)<<18) /* Page size */
517	#define M360_GMR_DPS_32BIT (0<<16) /* DRAM port size */
518	#define M360_GMR_DPS_16BIT (1<<16)
519	#define M360_GMR_DPS_8BIT (2<<16)
520	#define M360_GMR_DPS_DSACK (3<<16)
521	#define M360_GMR_WBT40 (1<<15) /* Wait between 040 transfers */
522	#define M360_GMR_WBTQ (1<<14) /* Wait between 360 transfers */
523	#define M360_GMR_SYNC (1<<13) /* Synchronous external access */
524	#define M360_GMR_EMWS (1<<12) /* External master wait state */
525	#define M360_GMR_OPAR (1<<11) /* Odd parity */
526	#define M360_GMR_PBEE (1<<10) /* Parity bus error enable */
527	#define M360_GMR_TSS40 (1<<9) /* TS* sample for 040 */
528	#define M360_GMR_NCS (1<<8) /* No CPU space */
529	#define M360_GMR_DWQ (1<<7) /* Delay write for 360 */
530	#define M360_GMR_DW40 (1<<6) /* Delay write for 040 */
531	#define M360_GMR_GAMX (1<<5) /* Global address mux enable */
532
533	#define M360_MEMC_BR_FC(x) ((x)<<7) /* Function code limit */
534	#define M360_MEMC_BR_TRLXQ (1<<6) /* Relax timing requirements */
535	#define M360_MEMC_BR_BACK40 (1<<5) /* Burst acknowledge to 040 */
536	#define M360_MEMC_BR_CSNT40 (1<<4) /* CS* negate timing for 040 */
537	#define M360_MEMC_BR_CSNTQ (1<<3) /* CS* negate timing for 360 */
538	#define M360_MEMC_BR_PAREN (1<<2) /* Enable parity checking */
539	#define M360_MEMC_BR_WP (1<<1) /* Write Protect */
540	#define M360_MEMC_BR_V (1<<0) /* Base/Option register are valid */
541
542	#define M360_MEMC_OR_TCYC(x) ((x)<<28) /* Cycle length (clocks) */
543	#define M360_MEMC_OR_WAITS(x) M360_MEMC_OR_TCYC((x)+1)
544	#define M360_MEMC_OR_2KB 0x0FFFF800 /* Address range */
545	#define M360_MEMC_OR_4KB 0x0FFFF000
546	#define M360_MEMC_OR_8KB 0x0FFFE000
547	#define M360_MEMC_OR_16KB 0x0FFFC000
548	#define M360_MEMC_OR_32KB 0x0FFF8000
549	#define M360_MEMC_OR_64KB 0x0FFF0000
550	#define M360_MEMC_OR_128KB 0x0FFE0000
551	#define M360_MEMC_OR_256KB 0x0FFC0000
552	#define M360_MEMC_OR_512KB 0x0FF80000
553	#define M360_MEMC_OR_1MB 0x0FF00000
554	#define M360_MEMC_OR_2MB 0x0FE00000
555	#define M360_MEMC_OR_4MB 0x0FC00000
556	#define M360_MEMC_OR_8MB 0x0F800000
557	#define M360_MEMC_OR_16MB 0x0F000000
558	#define M360_MEMC_OR_32MB 0x0E000000
559	#define M360_MEMC_OR_64MB 0x0C000000
560	#define M360_MEMC_OR_128MB 0x08000000
561	#define M360_MEMC_OR_256MB 0x00000000
562	#define M360_MEMC_OR_FCMC(x) ((x)<<7) /* Function code mask */
563	#define M360_MEMC_OR_BCYC(x) ((x)<<5) /* Burst cycle length (clocks) */
564	#define M360_MEMC_OR_PGME (1<<3) /* Page mode enable */
565	#define M360_MEMC_OR_32BIT (0<<1) /* Port size */
566	#define M360_MEMC_OR_16BIT (1<<1)
567	#define M360_MEMC_OR_8BIT (2<<1)
568	#define M360_MEMC_OR_DSACK (3<<1)
569	#define M360_MEMC_OR_DRAM (1<<0) /* Dynamic RAM select */
570
571	/*
572	*************************************************************************
573	* SI Mode Register (SIMODE) *
574	*************************************************************************
575	*/
576	#define M360_SI_SMC2_BITS 0xFFFF0000 /* All SMC2 bits */
577	#define M360_SI_SMC2_TDM (1<<31) /* Multiplexed SMC2 */
578	#define M360_SI_SMC2_BRG1 (0<<28) /* SMC2 clock souce */
579	#define M360_SI_SMC2_BRG2 (1<<28)
580	#define M360_SI_SMC2_BRG3 (2<<28)
581	#define M360_SI_SMC2_BRG4 (3<<28)
582	#define M360_SI_SMC2_CLK5 (0<<28)
583	#define M360_SI_SMC2_CLK6 (1<<28)
584	#define M360_SI_SMC2_CLK7 (2<<28)
585	#define M360_SI_SMC2_CLK8 (3<<28)
586	#define M360_SI_SMC1_BITS 0x0000FFFF /* All SMC1 bits */
587	#define M360_SI_SMC1_TDM (1<<15) /* Multiplexed SMC1 */
588	#define M360_SI_SMC1_BRG1 (0<<12) /* SMC1 clock souce */
589	#define M360_SI_SMC1_BRG2 (1<<12)
590	#define M360_SI_SMC1_BRG3 (2<<12)
591	#define M360_SI_SMC1_BRG4 (3<<12)
592	#define M360_SI_SMC1_CLK1 (0<<12)
593	#define M360_SI_SMC1_CLK2 (1<<12)
594	#define M360_SI_SMC1_CLK3 (2<<12)
595	#define M360_SI_SMC1_CLK4 (3<<12)
596
597	/*
598	*************************************************************************
599	* SDMA Configuration Register (SDMA) *
600	*************************************************************************
601	*/
602	#define M360_SDMA_FREEZE (2<<13) /* Freeze on next bus cycle */
603	#define M360_SDMA_SISM_7 (7<<8) /* Normal interrupt service mask */
604	#define M360_SDMA_SAID_4 (4<<4) /* Normal arbitration ID */
605	#define M360_SDMA_INTE (1<<1) /* SBER interrupt enable */
606	#define M360_SDMA_INTB (1<<0) /* SBKP interrupt enable */
607
608	/*
609	*************************************************************************
610	* Baud (sic) Rate Generators *
611	*************************************************************************
612	*/
613	#define M360_BRG_RST (1<<17) /* Reset generator */
614	#define M360_BRG_EN (1<<16) /* Enable generator */
615	#define M360_BRG_EXTC_BRGCLK (0<<14) /* Source is BRGCLK */
616	#define M360_BRG_EXTC_CLK2 (1<<14) /* Source is CLK2 pin */
617	#define M360_BRG_EXTC_CLK6 (2<<14) /* Source is CLK6 pin */
618	#define M360_BRG_ATB (1<<13) /* Autobaud */
619	#define M360_BRG_115200 (13<<1) /* Assume 25 MHz clock */
620	#define M360_BRG_57600 (26<<1)
621	#define M360_BRG_38400 (40<<1)
622	#define M360_BRG_19200 (80<<1)
623	#define M360_BRG_9600 (162<<1)
624	#define M360_BRG_4800 (324<<1)
625	#define M360_BRG_2400 (650<<1)
626	#define M360_BRG_1200 (1301<<1)
627	#define M360_BRG_600 (2603<<1)
628	#define M360_BRG_300 ((324<<1) \| 1)
629	#define M360_BRG_150 ((650<<1) \| 1)
630	#define M360_BRG_75 ((1301<<1) \| 1)
631
632	/*
633	*************************************************************************
634	* MC68360 DUAL-PORT RAM AND REGISTERS *
635	*************************************************************************
636	*/
637	typedef struct m360_ {
638	/*
639	* Dual-port RAM
640	*/
641	unsigned char dpram0[0x400]; /* Microcode program */
642	unsigned char dpram1[0x200];
643	unsigned char dpram2[0x100]; /* Microcode scratch */
644	unsigned char dpram3[0x100]; /* Not on REV A or B masks */
645	unsigned char _rsv0[0xC00-0x800];
646	m360SCCENparms_t scc1p;
647	unsigned char _rsv1[0xCB0-0xC00-sizeof(m360SCCENparms_t)];
648	m360MiscParms_t miscp;
649	unsigned char _rsv2[0xD00-0xCB0-sizeof(m360MiscParms_t)];
650	m360SCCparms_t scc2p;
651	unsigned char _rsv3[0xD80-0xD00-sizeof(m360SCCparms_t)];
652	m360SPIparms_t spip;
653	unsigned char _rsv4[0xDB0-0xD80-sizeof(m360SPIparms_t)];
654	m360TimerParms_t tmp;
655	unsigned char _rsv5[0xE00-0xDB0-sizeof(m360TimerParms_t)];
656	m360SCCparms_t scc3p;
657	unsigned char _rsv6[0xE70-0xE00-sizeof(m360SCCparms_t)];
658	m360IDMAparms_t idma1p;
659	unsigned char _rsv7[0xE80-0xE70-sizeof(m360IDMAparms_t)];
660	m360SMCparms_t smc1p;
661	unsigned char _rsv8[0xF00-0xE80-sizeof(m360SMCparms_t)];
662	m360SCCparms_t scc4p;
663	unsigned char _rsv9[0xF70-0xF00-sizeof(m360SCCparms_t)];
664	m360IDMAparms_t idma2p;
665	unsigned char _rsv10[0xF80-0xF70-sizeof(m360IDMAparms_t)];
666	m360SMCparms_t smc2p;
667	unsigned char _rsv11[0x1000-0xF80-sizeof(m360SMCparms_t)];
668
669	/*
670	* SIM Block
671	*/
672	unsigned long mcr;
673	unsigned long _pad00;
674	unsigned char avr;
675	unsigned char rsr;
676	unsigned short _pad01;
677	unsigned char clkocr;
678	unsigned char _pad02;
679	unsigned short _pad03;
680	unsigned short pllcr;
681	unsigned short _pad04;
682	unsigned short cdvcr;
683	unsigned short pepar;
684	unsigned long _pad05[2];
685	unsigned short _pad06;
686	unsigned char sypcr;
687	unsigned char swiv;
688	unsigned short _pad07;
689	unsigned short picr;
690	unsigned short _pad08;
691	unsigned short pitr;
692	unsigned short _pad09;
693	unsigned char _pad10;
694	unsigned char swsr;
695	unsigned long bkar;
696	unsigned long bcar;
697	unsigned long _pad11[2];
698
699	/*
700	* MEMC Block
701	*/
702	unsigned long gmr;
703	unsigned short mstat;
704	unsigned short _pad12;
705	unsigned long _pad13[2];
706	m360MEMCRegisters_t memc[8];
707	unsigned char _pad14[0xF0-0xD0];
708	unsigned char _pad15[0x100-0xF0];
709	unsigned char _pad16[0x500-0x100];
710
711	/*
712	* IDMA1 Block
713	*/
714	unsigned short iccr;
715	unsigned short _pad17;
716	unsigned short cmr1;
717	unsigned short _pad18;
718	unsigned long sapr1;
719	unsigned long dapr1;
720	unsigned long bcr1;
721	unsigned char fcr1;
722	unsigned char _pad19;
723	unsigned char cmar1;
724	unsigned char _pad20;
725	unsigned char csr1;
726	unsigned char _pad21;
727	unsigned short _pad22;
728
729	/*
730	* SDMA Block
731	*/
732	unsigned char sdsr;
733	unsigned char _pad23;
734	unsigned short sdcr;
735	unsigned long sdar;
736
737	/*
738	* IDMA2 Block
739	*/
740	unsigned short _pad24;
741	unsigned short cmr2;
742	unsigned long sapr2;
743	unsigned long dapr2;
744	unsigned long bcr2;
745	unsigned char fcr2;
746	unsigned char _pad26;
747	unsigned char cmar2;
748	unsigned char _pad27;
749	unsigned char csr2;
750	unsigned char _pad28;
751	unsigned short _pad29;
752	unsigned long _pad30;
753
754	/*
755	* CPIC Block
756	*/
757	unsigned long cicr;
758	unsigned long cipr;
759	unsigned long cimr;
760	unsigned long cisr;
761
762	/*
763	* Parallel I/O Block
764	*/
765	unsigned short padir;
766	unsigned short papar;
767	unsigned short paodr;
768	unsigned short padat;
769	unsigned long _pad31[2];
770	unsigned short pcdir;
771	unsigned short pcpar;
772	unsigned short pcso;
773	unsigned short pcdat;
774	unsigned short pcint;
775	unsigned short _pad32;
776	unsigned long _pad33[5];
777
778	/*
779	* TIMER Block
780	*/
781	unsigned short tgcr;
782	unsigned short _pad34;
783	unsigned long _pad35[3];
784	unsigned short tmr1;
785	unsigned short tmr2;
786	unsigned short trr1;
787	unsigned short trr2;
788	unsigned short tcr1;
789	unsigned short tcr2;
790	unsigned short tcn1;
791	unsigned short tcn2;
792	unsigned short tmr3;
793	unsigned short tmr4;
794	unsigned short trr3;
795	unsigned short trr4;
796	unsigned short tcr3;
797	unsigned short tcr4;
798	unsigned short tcn3;
799	unsigned short tcn4;
800	unsigned short ter1;
801	unsigned short ter2;
802	unsigned short ter3;
803	unsigned short ter4;
804	unsigned long _pad36[2];
805
806	/*
807	* CP Block
808	*/
809	unsigned short cr;
810	unsigned short _pad37;
811	unsigned short rccr;
812	unsigned short _pad38;
813	unsigned long _pad39[3];
814	unsigned short _pad40;
815	unsigned short rter;
816	unsigned short _pad41;
817	unsigned short rtmr;
818	unsigned long _pad42[5];
819
820	/*
821	* BRG Block
822	*/
823	unsigned long brgc1;
824	unsigned long brgc2;
825	unsigned long brgc3;
826	unsigned long brgc4;
827
828	/*
829	* SCC Block
830	*/
831	m360SCCRegisters_t scc1;
832	m360SCCRegisters_t scc2;
833	m360SCCRegisters_t scc3;
834	m360SCCRegisters_t scc4;
835
836	/*
837	* SMC Block
838	*/
839	m360SMCRegisters_t smc1;
840	m360SMCRegisters_t smc2;
841
842	/*
843	* SPI Block
844	*/
845	unsigned short spmode;
846	unsigned short _pad43[2];
847	unsigned char spie;
848	unsigned char _pad44;
849	unsigned short _pad45;
850	unsigned char spim;
851	unsigned char _pad46[2];
852	unsigned char spcom;
853	unsigned short _pad47[2];
854
855	/*
856	* PIP Block
857	*/
858	unsigned short pipc;
859	unsigned short _pad48;
860	unsigned short ptpr;
861	unsigned long pbdir;
862	unsigned long pbpar;
863	unsigned short _pad49;
864	unsigned short pbodr;
865	unsigned long pbdat;
866	unsigned long _pad50[6];
867
868	/*
869	* SI Block
870	*/
871	unsigned long simode;
872	unsigned char sigmr;
873	unsigned char _pad51;
874	unsigned char sistr;
875	unsigned char sicmr;
876	unsigned long _pad52;
877	unsigned long sicr;
878	unsigned short _pad53;
879	unsigned short sirp[2];
880	unsigned short _pad54;
881	unsigned long _pad55[2];
882	unsigned char siram[256];
883	} m360_t;
884
885	extern volatile m360_t m360;
886
887	/*
888	* definitions for the port b SPI pin bits
889	*/
890	#define M360_PB_SPI_MISO_MSK (1<< 3)
891	#define M360_PB_SPI_MOSI_MSK (1<< 2)
892	#define M360_PB_SPI_CLK_MSK (1<< 1)
893
894	#endif /* _RTEMS_M68K_M68360_H */

Note: See TracBrowser for help on using the repository browser.

Context Navigation

source: rtems/cpukit/score/cpu/m68k/rtems/m68k/m68360.h @ e354eb4f

Download in other formats: