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source: rtems/cpukit/score/cpu/m68k/rtems/m68k/m68360.h @ dce1c1a1

4.104.114.84.95

Last change on this file since dce1c1a1 was dce1c1a1, checked in by Joel Sherrill <joel.sherrill@…>, on 05/01/96 at 15:24:37
Updates from Eric Norum to use the mcpu32 flags and fix comments.
Property mode set to `100644`
File size: 27.8 KB

Line
1	/*
2	**************************************************************************
3	**************************************************************************
4
5	MOTOROLA MC68360 QUAD INTEGRATED COMMUNICATIONS CONTROLLER (QUICC)
6
7	HARDWARE DECLARATIONS
8
9
10	Submitted By:
11
12	W. Eric Norum
13	Saskatchewan Accelerator Laboratory
14	University of Saskatchewan
15	107 North Road
16	Saskatoon, Saskatchewan, CANADA
17	S7N 5C6
18
19	eric@skatter.usask.ca
20
21	$Id$
22
23	**************************************************************************
24	**************************************************************************
25	*/
26
27	#ifndef __MC68360_h
28	#define __MC68360_h
29
30	/*
31	*************************************************************************
32	* REGISTER SUBBLOCKS *
33	*************************************************************************
34	*/
35
36	/*
37	* Memory controller registers
38	*/
39	typedef struct m360MEMCRegisters_ {
40	rtems_unsigned32 br;
41	rtems_unsigned32 or;
42	rtems_unsigned32 _pad[2];
43	} m360MEMCRegisters_t;
44
45	/*
46	* Serial Communications Controller registers
47	*/
48	typedef struct m360SCCRegisters_ {
49	rtems_unsigned32 gsmr_l;
50	rtems_unsigned32 gsmr_h;
51	rtems_unsigned16 psmr;
52	rtems_unsigned16 _pad0;
53	rtems_unsigned16 todr;
54	rtems_unsigned16 dsr;
55	rtems_unsigned16 scce;
56	rtems_unsigned16 _pad1;
57	rtems_unsigned16 sccm;
58	rtems_unsigned8 _pad2;
59	rtems_unsigned8 sccs;
60	rtems_unsigned32 _pad3[2];
61	} m360SCCRegisters_t;
62
63	/*
64	* Serial Management Controller registers
65	*/
66	typedef struct m360SMCRegisters_ {
67	rtems_unsigned16 _pad0;
68	rtems_unsigned16 smcmr;
69	rtems_unsigned16 _pad1;
70	rtems_unsigned8 smce;
71	rtems_unsigned8 _pad2;
72	rtems_unsigned16 _pad3;
73	rtems_unsigned8 smcm;
74	rtems_unsigned8 _pad4;
75	rtems_unsigned32 _pad5;
76	} m360SMCRegisters_t;
77
78
79	/*
80	*************************************************************************
81	* Miscellaneous Parameters *
82	*************************************************************************
83	*/
84	typedef struct m360MiscParms_ {
85	rtems_unsigned16 rev_num;
86	rtems_unsigned16 _res1;
87	rtems_unsigned32 _res2;
88	rtems_unsigned32 _res3;
89	} m360MiscParms_t;
90
91	/*
92	*************************************************************************
93	* RISC Timers *
94	*************************************************************************
95	*/
96	typedef struct m360TimerParms_ {
97	rtems_unsigned16 tm_base;
98	rtems_unsigned16 _tm_ptr;
99	rtems_unsigned16 _r_tmr;
100	rtems_unsigned16 _r_tmv;
101	rtems_unsigned32 tm_cmd;
102	rtems_unsigned32 tm_cnt;
103	} m360TimerParms_t;
104
105	/*
106	* RISC Controller Configuration Register (RCCR)
107	* All other bits in this register are either reserved or
108	* used only with a Motorola-supplied RAM microcode packge.
109	*/
110	#define M360_RCCR_TIME (1<<15) /* Enable timer */
111	#define M360_RCCR_TIMEP(x) ((x)<<8) /* Timer period */
112
113	/*
114	* Command register
115	* Set up this register before issuing a M360_CR_OP_SET_TIMER command.
116	*/
117	#define M360_TM_CMD_V (1<<31) /* Set to enable timer */
118	#define M360_TM_CMD_R (1<<30) /* Set for automatic restart */
119	#define M360_TM_CMD_TIMER(x) ((x)<<16) /* Select timer */
120	#define M360_TM_CMD_PERIOD(x) (x) /* Timer period (16 bits) */
121
122	/*
123	*************************************************************************
124	* DMA Controllers *
125	*************************************************************************
126	*/
127	typedef struct m360IDMAparms_ {
128	rtems_unsigned16 ibase;
129	rtems_unsigned16 ibptr;
130	rtems_unsigned32 _istate;
131	rtems_unsigned32 _itemp;
132	} m360IDMAparms_t;
133
134	/*
135	*************************************************************************
136	* Serial Communication Controllers *
137	*************************************************************************
138	*/
139	typedef struct m360SCCparms_ {
140	rtems_unsigned16 rbase;
141	rtems_unsigned16 tbase;
142	rtems_unsigned8 rfcr;
143	rtems_unsigned8 tfcr;
144	rtems_unsigned16 mrblr;
145	rtems_unsigned32 _rstate;
146	rtems_unsigned32 _pad0;
147	rtems_unsigned16 _rbptr;
148	rtems_unsigned16 _pad1;
149	rtems_unsigned32 _pad2;
150	rtems_unsigned32 _tstate;
151	rtems_unsigned32 _pad3;
152	rtems_unsigned16 _tbptr;
153	rtems_unsigned16 _pad4;
154	rtems_unsigned32 _pad5;
155	rtems_unsigned32 _rcrc;
156	rtems_unsigned32 _tcrc;
157	union {
158	struct {
159	rtems_unsigned32 _res0;
160	rtems_unsigned32 _res1;
161	rtems_unsigned16 max_idl;
162	rtems_unsigned16 _idlc;
163	rtems_unsigned16 brkcr;
164	rtems_unsigned16 parec;
165	rtems_unsigned16 frmec;
166	rtems_unsigned16 nosec;
167	rtems_unsigned16 brkec;
168	rtems_unsigned16 brklen;
169	rtems_unsigned16 uaddr[2];
170	rtems_unsigned16 _rtemp;
171	rtems_unsigned16 toseq;
172	rtems_unsigned16 character[8];
173	rtems_unsigned16 rccm;
174	rtems_unsigned16 rccr;
175	rtems_unsigned16 rlbc;
176	} uart;
177	} un;
178	} m360SCCparms_t;
179
180	typedef struct m360SCCENparms_ {
181	rtems_unsigned16 rbase;
182	rtems_unsigned16 tbase;
183	rtems_unsigned8 rfcr;
184	rtems_unsigned8 tfcr;
185	rtems_unsigned16 mrblr;
186	rtems_unsigned32 _rstate;
187	rtems_unsigned32 _pad0;
188	rtems_unsigned16 _rbptr;
189	rtems_unsigned16 _pad1;
190	rtems_unsigned32 _pad2;
191	rtems_unsigned32 _tstate;
192	rtems_unsigned32 _pad3;
193	rtems_unsigned16 _tbptr;
194	rtems_unsigned16 _pad4;
195	rtems_unsigned32 _pad5;
196	rtems_unsigned32 _rcrc;
197	rtems_unsigned32 _tcrc;
198	union {
199	struct {
200	rtems_unsigned32 _res0;
201	rtems_unsigned32 _res1;
202	rtems_unsigned16 max_idl;
203	rtems_unsigned16 _idlc;
204	rtems_unsigned16 brkcr;
205	rtems_unsigned16 parec;
206	rtems_unsigned16 frmec;
207	rtems_unsigned16 nosec;
208	rtems_unsigned16 brkec;
209	rtems_unsigned16 brklen;
210	rtems_unsigned16 uaddr[2];
211	rtems_unsigned16 _rtemp;
212	rtems_unsigned16 toseq;
213	rtems_unsigned16 character[8];
214	rtems_unsigned16 rccm;
215	rtems_unsigned16 rccr;
216	rtems_unsigned16 rlbc;
217	} uart;
218	struct {
219	rtems_unsigned32 c_pres;
220	rtems_unsigned32 c_mask;
221	rtems_unsigned32 crcec;
222	rtems_unsigned32 alec;
223	rtems_unsigned32 disfc;
224	rtems_unsigned16 pads;
225	rtems_unsigned16 ret_lim;
226	rtems_unsigned16 _ret_cnt;
227	rtems_unsigned16 mflr;
228	rtems_unsigned16 minflr;
229	rtems_unsigned16 maxd1;
230	rtems_unsigned16 maxd2;
231	rtems_unsigned16 _maxd;
232	rtems_unsigned16 dma_cnt;
233	rtems_unsigned16 _max_b;
234	rtems_unsigned16 gaddr1;
235	rtems_unsigned16 gaddr2;
236	rtems_unsigned16 gaddr3;
237	rtems_unsigned16 gaddr4;
238	rtems_unsigned32 _tbuf0data0;
239	rtems_unsigned32 _tbuf0data1;
240	rtems_unsigned32 _tbuf0rba0;
241	rtems_unsigned32 _tbuf0crc;
242	rtems_unsigned16 _tbuf0bcnt;
243	rtems_unsigned16 paddr_h;
244	rtems_unsigned16 paddr_m;
245	rtems_unsigned16 paddr_l;
246	rtems_unsigned16 p_per;
247	rtems_unsigned16 _rfbd_ptr;
248	rtems_unsigned16 _tfbd_ptr;
249	rtems_unsigned16 _tlbd_ptr;
250	rtems_unsigned32 _tbuf1data0;
251	rtems_unsigned32 _tbuf1data1;
252	rtems_unsigned32 _tbuf1rba0;
253	rtems_unsigned32 _tbuf1crc;
254	rtems_unsigned16 _tbuf1bcnt;
255	rtems_unsigned16 _tx_len;
256	rtems_unsigned16 iaddr1;
257	rtems_unsigned16 iaddr2;
258	rtems_unsigned16 iaddr3;
259	rtems_unsigned16 iaddr4;
260	rtems_unsigned16 _boff_cnt;
261	rtems_unsigned16 taddr_l;
262	rtems_unsigned16 taddr_m;
263	rtems_unsigned16 taddr_h;
264	} ethernet;
265	} un;
266	} m360SCCENparms_t;
267
268	/*
269	* Receive and transmit function code register bits
270	* These apply to the function code registers of all devices, not just SCC.
271	*/
272	#define M360_RFCR_MOT (1<<4)
273	#define M360_RFCR_DMA_SPACE 0x8
274	#define M360_TFCR_MOT (1<<4)
275	#define M360_TFCR_DMA_SPACE 0x8
276
277	/*
278	*************************************************************************
279	* Serial Management Controllers *
280	*************************************************************************
281	*/
282	typedef struct m360SMCparms_ {
283	rtems_unsigned16 rbase;
284	rtems_unsigned16 tbase;
285	rtems_unsigned8 rfcr;
286	rtems_unsigned8 tfcr;
287	rtems_unsigned16 mrblr;
288	rtems_unsigned32 _rstate;
289	rtems_unsigned32 _pad0;
290	rtems_unsigned16 _rbptr;
291	rtems_unsigned16 _pad1;
292	rtems_unsigned32 _pad2;
293	rtems_unsigned32 _tstate;
294	rtems_unsigned32 _pad3;
295	rtems_unsigned16 _tbptr;
296	rtems_unsigned16 _pad4;
297	rtems_unsigned32 _pad5;
298	union {
299	struct {
300	rtems_unsigned16 max_idl;
301	rtems_unsigned16 _pad0;
302	rtems_unsigned16 brklen;
303	rtems_unsigned16 brkec;
304	rtems_unsigned16 brkcr;
305	rtems_unsigned16 _r_mask;
306	} uart;
307	struct {
308	rtems_unsigned16 _pad0[5];
309	} transparent;
310	} un;
311	} m360SMCparms_t;
312
313	/*
314	* Mode register
315	*/
316	#define M360_SMCMR_CLEN(x) ((x)<<11) /* Character length */
317	#define M360_SMCMR_2STOP (1<<10) /* 2 stop bits */
318	#define M360_SMCMR_PARITY (1<<9) /* Enable parity */
319	#define M360_SMCMR_EVEN (1<<8) /* Even parity */
320	#define M360_SMCMR_SM_GCI (0<<4) /* GCI Mode */
321	#define M360_SMCMR_SM_UART (2<<4) /* UART Mode */
322	#define M360_SMCMR_SM_TRANSPARENT (3<<4) /* Transparent Mode */
323	#define M360_SMCMR_DM_LOOPBACK (1<<2) /* Local loopback mode */
324	#define M360_SMCMR_DM_ECHO (2<<2) /* Echo mode */
325	#define M360_SMCMR_TEN (1<<1) /* Enable transmitter */
326	#define M360_SMCMR_REN (1<<0) /* Enable receiver */
327
328	/*
329	* Event and mask registers (SMCE, SMCM)
330	*/
331	#define M360_SMCE_BRK (1<<4)
332	#define M360_SMCE_BSY (1<<2)
333	#define M360_SMCE_TX (1<<1)
334	#define M360_SMCE_RX (1<<0)
335
336	/*
337	*************************************************************************
338	* Serial Peripheral Interface *
339	*************************************************************************
340	*/
341	typedef struct m360SPIparms_ {
342	rtems_unsigned16 rbase;
343	rtems_unsigned16 tbase;
344	rtems_unsigned8 rfcr;
345	rtems_unsigned8 tfcr;
346	rtems_unsigned16 mrblr;
347	rtems_unsigned32 _rstate;
348	rtems_unsigned32 _pad0;
349	rtems_unsigned16 _rbptr;
350	rtems_unsigned16 _pad1;
351	rtems_unsigned32 _pad2;
352	rtems_unsigned32 _tstate;
353	rtems_unsigned32 _pad3;
354	rtems_unsigned16 _tbptr;
355	rtems_unsigned16 _pad4;
356	rtems_unsigned32 _pad5;
357	} m360SPIparms_t;
358
359	/*
360	* Mode register (SPMODE)
361	*/
362	#define M360_SPMODE_LOOP (1<<14) /* Local loopback mode */
363	#define M360_SPMODE_CI (1<<13) /* Clock invert */
364	#define M360_SPMODE_CP (1<<12) /* Clock phase */
365	#define M360_SPMODE_DIV16 (1<<11) /* Divide BRGCLK by 16 */
366	#define M360_SPMODE_REV (1<<10) /* Reverse data */
367	#define M360_SPMODE_MASTER (1<<9) /* SPI is master */
368	#define M360_SPMODE_EN (1<<8) /* Enable SPI */
369	#define M360_SPMODE_CLEN(x) ((x)<<4) /* Character length */
370	#define M360_SPMODE_PM(x) (x) /* Prescaler modulus */
371
372	/*
373	* Mode register (SPCOM)
374	*/
375	#define M360_SPCOM_STR (1<<7) /* Start transmit */
376
377	/*
378	* Event and mask registers (SPIE, SPIM)
379	*/
380	#define M360_SPIE_MME (1<<5) /* Multi-master error */
381	#define M360_SPIE_TXE (1<<4) /* Tx error */
382	#define M360_SPIE_BSY (1<<2) /* Busy condition*/
383	#define M360_SPIE_TXB (1<<1) /* Tx buffer */
384	#define M360_SPIE_RXB (1<<0) /* Rx buffer */
385
386	/*
387	*************************************************************************
388	* SDMA (SCC, SMC, SPI) Buffer Descriptors *
389	*************************************************************************
390	*/
391	typedef struct m360BufferDescriptor_ {
392	rtems_unsigned16 status;
393	rtems_unsigned16 length;
394	volatile void *buffer;
395	} m360BufferDescriptor_t;
396
397	/*
398	* Bits in receive buffer descriptor status word
399	*/
400	#define M360_BD_EMPTY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
401	#define M360_BD_WRAP (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */
402	#define M360_BD_INTERRUPT (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */
403	#define M360_BD_LAST (1<<11) /* Ethernet, SPI */
404	#define M360_BD_CONTROL_CHAR (1<<11) /* SCC UART */
405	#define M360_BD_FIRST_IN_FRAME (1<<10) /* Ethernet */
406	#define M360_BD_ADDRESS (1<<10) /* SCC UART */
407	#define M360_BD_CONTINUOUS (1<<9) /* SCC UART, SMC UART, SPI */
408	#define M360_BD_MISS (1<<8) /* Ethernet */
409	#define M360_BD_IDLE (1<<8) /* SCC UART, SMC UART */
410	#define M360_BD_ADDRSS_MATCH (1<<7) /* SCC UART */
411	#define M360_BD_LONG (1<<5) /* Ethernet */
412	#define M360_BD_BREAK (1<<5) /* SCC UART, SMC UART */
413	#define M360_BD_NONALIGNED (1<<4) /* Ethernet */
414	#define M360_BD_FRAMING_ERROR (1<<4) /* SCC UART, SMC UART */
415	#define M360_BD_SHORT (1<<3) /* Ethernet */
416	#define M360_BD_PARITY_ERROR (1<<3) /* SCC UART, SMC UART */
417	#define M360_BD_CRC_ERROR (1<<2) /* Ethernet */
418	#define M360_BD_OVERRUN (1<<1) /* Ethernet, SCC UART, SMC UART, SPI */
419	#define M360_BD_COLLISION (1<<0) /* Ethernet */
420	#define M360_BD_CARRIER_LOST (1<<0) /* SCC UART */
421	#define M360_BD_MASTER_ERROR (1<<0) /* SPI */
422
423	/*
424	* Bits in transmit buffer descriptor status word
425	* Many bits have the same meaning as those in receiver buffer descriptors.
426	*/
427	#define M360_BD_READY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
428	#define M360_BD_PAD (1<<14) /* Ethernet */
429	#define M360_BD_CTS_REPORT (1<<11) /* SCC UART */
430	#define M360_BD_TX_CRC (1<<10) /* Ethernet */
431	#define M360_BD_DEFER (1<<9) /* Ethernet */
432	#define M360_BD_HEARTBEAT (1<<8) /* Ethernet */
433	#define M360_BD_PREAMBLE (1<<8) /* SCC UART, SMC UART */
434	#define M360_BD_LATE_COLLISION (1<<7) /* Ethernet */
435	#define M360_BD_NO_STOP_BIT (1<<7) /* SCC UART */
436	#define M360_BD_RETRY_LIMIT (1<<6) /* Ethernet */
437	#define M360_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) /* Ethernet */
438	#define M360_BD_UNDERRUN (1<<1) /* Ethernet, SPI */
439	#define M360_BD_CARRIER_LOST (1<<0) /* Ethernet */
440	#define M360_BD_CTS_LOST (1<<0) /* SCC UART */
441
442	/*
443	*************************************************************************
444	* IDMA Buffer Descriptors *
445	*************************************************************************
446	*/
447	typedef struct m360IDMABufferDescriptor_ {
448	rtems_unsigned16 status;
449	rtems_unsigned16 _pad;
450	rtems_unsigned32 length;
451	void *source;
452	void *destination;
453	} m360IDMABufferDescriptor_t;
454
455	/*
456	*************************************************************************
457	* RISC Communication Processor Module Command Register (CR) *
458	*************************************************************************
459	*/
460	#define M360_CR_RST (1<<15) /* Reset communication processor */
461	#define M360_CR_OP_INIT_RX_TX (0<<8) /* SCC, SMC UART, SMC GCI, SPI */
462	#define M360_CR_OP_INIT_RX (1<<8) /* SCC, SMC UART, SPI */
463	#define M360_CR_OP_INIT_TX (2<<8) /* SCC, SMC UART, SPI */
464	#define M360_CR_OP_INIT_HUNT (3<<8) /* SCC, SMC UART */
465	#define M360_CR_OP_STOP_TX (4<<8) /* SCC, SMC UART */
466	#define M360_CR_OP_GR_STOP_TX (5<<8) /* SCC */
467	#define M360_CR_OP_INIT_IDMA (5<<8) /* IDMA */
468	#define M360_CR_OP_RESTART_TX (6<<8) /* SCC, SMC UART */
469	#define M360_CR_OP_CLOSE_RX_BD (7<<8) /* SCC, SMC UART, SPI */
470	#define M360_CR_OP_SET_GRP_ADDR (8<<8) /* SCC */
471	#define M360_CR_OP_SET_TIMER (8<<8) /* Timer */
472	#define M360_CR_OP_GCI_TIMEOUT (9<<8) /* SMC GCI */
473	#define M360_CR_OP_RESERT_BCS (10<<8) /* SCC */
474	#define M360_CR_OP_GCI_ABORT (10<<8) /* SMC GCI */
475	#define M360_CR_CHAN_SCC1 (0<<4) /* Channel selection */
476	#define M360_CR_CHAN_SCC2 (4<<4)
477	#define M360_CR_CHAN_SPI (5<<4)
478	#define M360_CR_CHAN_TIMER (5<<4)
479	#define M360_CR_CHAN_SCC3 (8<<4)
480	#define M360_CR_CHAN_SMC1 (9<<4)
481	#define M360_CR_CHAN_IDMA1 (9<<4)
482	#define M360_CR_CHAN_SCC4 (12<<4)
483	#define M360_CR_CHAN_SMC2 (13<<4)
484	#define M360_CR_CHAN_IDMA2 (13<<4)
485	#define M360_CR_FLG (1<<0) /* Command flag */
486
487	/*
488	*************************************************************************
489	* System Protection Control Register (SYPCR) *
490	*************************************************************************
491	*/
492	#define M360_SYPCR_SWE (1<<7) /* Software watchdog enable */
493	#define M360_SYPCR_SWRI (1<<6) /* Software watchdog reset select */
494	#define M360_SYPCR_SWT1 (1<<5) /* Software watchdog timing bit 1 */
495	#define M360_SYPCR_SWT0 (1<<4) /* Software watchdog timing bit 0 */
496	#define M360_SYPCR_DBFE (1<<3) /* Double bus fault monitor enable */
497	#define M360_SYPCR_BME (1<<2) /* Bus monitor external enable */
498	#define M360_SYPCR_BMT1 (1<<1) /* Bus monitor timing bit 1 */
499	#define M360_SYPCR_BMT0 (1<<0) /* Bus monitor timing bit 0 */
500
501	/*
502	*************************************************************************
503	* Memory Control Registers *
504	*************************************************************************
505	*/
506	#define M360_GMR_RCNT(x) ((x)<<24) /* Refresh count */
507	#define M360_GMR_RFEN (1<<23) /* Refresh enable */
508	#define M360_GMR_RCYC(x) ((x)<<21) /* Refresh cycle length */
509	#define M360_GMR_PGS(x) ((x)<<18) /* Page size */
510	#define M360_GMR_DPS_32BIT (0<<16) /* DRAM port size */
511	#define M360_GMR_DPS_16BIT (1<<16)
512	#define M360_GMR_DPS_8BIT (2<<16)
513	#define M360_GMR_DPS_DSACK (3<<16)
514	#define M360_GMR_WBT40 (1<<15) /* Wait between 040 transfers */
515	#define M360_GMR_WBTQ (1<<14) /* Wait between 360 transfers */
516	#define M360_GMR_SYNC (1<<13) /* Synchronous external access */
517	#define M360_GMR_EMWS (1<<12) /* External master wait state */
518	#define M360_GMR_OPAR (1<<11) /* Odd parity */
519	#define M360_GMR_PBEE (1<<10) /* Parity bus error enable */
520	#define M360_GMR_TSS40 (1<<9) /* TS* sample for 040 */
521	#define M360_GMR_NCS (1<<8) /* No CPU space */
522	#define M360_GMR_DWQ (1<<7) /* Delay write for 360 */
523	#define M360_GMR_DW40 (1<<6) /* Delay write for 040 */
524	#define M360_GMR_GAMX (1<<5) /* Global address mux enable */
525
526	#define M360_MEMC_BR_FC(x) ((x)<<7) /* Function code limit */
527	#define M360_MEMC_BR_TRLXQ (1<<6) /* Relax timing requirements */
528	#define M360_MEMC_BR_BACK40 (1<<5) /* Burst acknowledge to 040 */
529	#define M360_MEMC_BR_CSNT40 (1<<4) /* CS* negate timing for 040 */
530	#define M360_MEMC_BR_CSNTQ (1<<3) /* CS* negate timing for 360 */
531	#define M360_MEMC_BR_PAREN (1<<2) /* Enable parity checking */
532	#define M360_MEMC_BR_WP (1<<1) /* Write Protect */
533	#define M360_MEMC_BR_V (1<<0) /* Base/Option register are valid */
534
535	#define M360_MEMC_OR_TCYC(x) ((x)<<28) /* Cycle length (clocks) */
536	#define M360_MEMC_OR_WAITS(x) M360_MEMC_OR_TCYC((x)+1)
537	#define M360_MEMC_OR_2KB 0x0FFFF800 /* Address range */
538	#define M360_MEMC_OR_4KB 0x0FFFF000
539	#define M360_MEMC_OR_8KB 0x0FFFE000
540	#define M360_MEMC_OR_16KB 0x0FFFC000
541	#define M360_MEMC_OR_32KB 0x0FFF8000
542	#define M360_MEMC_OR_64KB 0x0FFF0000
543	#define M360_MEMC_OR_128KB 0x0FFE0000
544	#define M360_MEMC_OR_256KB 0x0FFC0000
545	#define M360_MEMC_OR_512KB 0x0FF80000
546	#define M360_MEMC_OR_1MB 0x0FF00000
547	#define M360_MEMC_OR_2MB 0x0FE00000
548	#define M360_MEMC_OR_4MB 0x0FC00000
549	#define M360_MEMC_OR_8MB 0x0F800000
550	#define M360_MEMC_OR_16MB 0x0F000000
551	#define M360_MEMC_OR_32MB 0x0E000000
552	#define M360_MEMC_OR_64MB 0x0C000000
553	#define M360_MEMC_OR_128MB 0x08000000
554	#define M360_MEMC_OR_256MB 0x00000000
555	#define M360_MEMC_OR_FCMC(x) ((x)<<7) /* Function code mask */
556	#define M360_MEMC_OR_BCYC(x) ((x)<<5) /* Burst cycle length (clocks) */
557	#define M360_MEMC_OR_PGME (1<<3) /* Page mode enable */
558	#define M360_MEMC_OR_32BIT (0<<1) /* Port size */
559	#define M360_MEMC_OR_16BIT (1<<1)
560	#define M360_MEMC_OR_8BIT (2<<1)
561	#define M360_MEMC_OR_DSACK (3<<1)
562	#define M360_MEMC_OR_DRAM (1<<0) /* Dynamic RAM select */
563
564	/*
565	*************************************************************************
566	* SI Mode Register (SIMODE) *
567	*************************************************************************
568	*/
569	#define M360_SI_SMC2_BITS 0xFFFF0000 /* All SMC2 bits */
570	#define M360_SI_SMC2_TDM (1<<31) /* Multiplexed SMC2 */
571	#define M360_SI_SMC2_BRG1 (0<<28) /* SMC2 clock souce */
572	#define M360_SI_SMC2_BRG2 (1<<28)
573	#define M360_SI_SMC2_BRG3 (2<<28)
574	#define M360_SI_SMC2_BRG4 (3<<28)
575	#define M360_SI_SMC2_CLK5 (0<<28)
576	#define M360_SI_SMC2_CLK6 (1<<28)
577	#define M360_SI_SMC2_CLK7 (2<<28)
578	#define M360_SI_SMC2_CLK8 (3<<28)
579	#define M360_SI_SMC1_BITS 0x0000FFFF /* All SMC1 bits */
580	#define M360_SI_SMC1_TDM (1<<15) /* Multiplexed SMC1 */
581	#define M360_SI_SMC1_BRG1 (0<<12) /* SMC1 clock souce */
582	#define M360_SI_SMC1_BRG2 (1<<12)
583	#define M360_SI_SMC1_BRG3 (2<<12)
584	#define M360_SI_SMC1_BRG4 (3<<12)
585	#define M360_SI_SMC1_CLK1 (0<<12)
586	#define M360_SI_SMC1_CLK2 (1<<12)
587	#define M360_SI_SMC1_CLK3 (2<<12)
588	#define M360_SI_SMC1_CLK4 (3<<12)
589
590	/*
591	*************************************************************************
592	* SDMA Configuration Register (SDMA) *
593	*************************************************************************
594	*/
595	#define M360_SDMA_FREEZE (2<<13) /* Freeze on next bus cycle */
596	#define M360_SDMA_SISM_7 (7<<8) /* Normal interrupt service mask */
597	#define M360_SDMA_SAID_4 (4<<4) /* Normal arbitration ID */
598	#define M360_SDMA_INTE (1<<1) /* SBER interrupt enable */
599	#define M360_SDMA_INTB (1<<0) /* SBKP interrupt enable */
600
601	/*
602	*************************************************************************
603	* Baud (sic) Rate Generators *
604	*************************************************************************
605	*/
606	#define M360_BRG_RST (1<<17) /* Reset generator */
607	#define M360_BRG_EN (1<<16) /* Enable generator */
608	#define M360_BRG_EXTC_BRGCLK (0<<14) /* Source is BRGCLK */
609	#define M360_BRG_EXTC_CLK2 (1<<14) /* Source is CLK2 pin */
610	#define M360_BRG_EXTC_CLK6 (2<<14) /* Source is CLK6 pin */
611	#define M360_BRG_ATB (1<<13) /* Autobaud */
612	#define M360_BRG_115200 (13<<1) /* Assume 25 MHz clock */
613	#define M360_BRG_57600 (26<<1)
614	#define M360_BRG_38400 (40<<1)
615	#define M360_BRG_19200 (80<<1)
616	#define M360_BRG_9600 (162<<1)
617	#define M360_BRG_4800 (324<<1)
618	#define M360_BRG_2400 (650<<1)
619	#define M360_BRG_1200 (1301<<1)
620	#define M360_BRG_600 (2603<<1)
621	#define M360_BRG_300 ((324<<1) \| 1)
622	#define M360_BRG_150 ((650<<1) \| 1)
623	#define M360_BRG_75 ((1301<<1) \| 1)
624
625	/*
626	*************************************************************************
627	* MC68360 DUAL-PORT RAM AND REGISTERS *
628	*************************************************************************
629	*/
630	typedef struct m360_ {
631	/*
632	* Dual-port RAM
633	*/
634	rtems_unsigned8 dpram0[0x400]; /* Microcode program */
635	rtems_unsigned8 dpram1[0x200];
636	rtems_unsigned8 dpram2[0x100]; /* Microcode scratch */
637	rtems_unsigned8 dpram3[0x100]; /* Not on REV A or B masks */
638	rtems_unsigned8 _rsv0[0xC00-0x800];
639	m360SCCENparms_t scc1p;
640	rtems_unsigned8 _rsv1[0xCB0-0xC00-sizeof(m360SCCENparms_t)];
641	m360MiscParms_t miscp;
642	rtems_unsigned8 _rsv2[0xD00-0xCB0-sizeof(m360MiscParms_t)];
643	m360SCCparms_t scc2p;
644	rtems_unsigned8 _rsv3[0xD80-0xD00-sizeof(m360SCCparms_t)];
645	m360SPIparms_t spip;
646	rtems_unsigned8 _rsv4[0xDB0-0xD80-sizeof(m360SPIparms_t)];
647	m360TimerParms_t tmp;
648	rtems_unsigned8 _rsv5[0xE00-0xDB0-sizeof(m360TimerParms_t)];
649	m360SCCparms_t scc3p;
650	rtems_unsigned8 _rsv6[0xE70-0xE00-sizeof(m360SCCparms_t)];
651	m360IDMAparms_t idma1p;
652	rtems_unsigned8 _rsv7[0xE80-0xE70-sizeof(m360IDMAparms_t)];
653	m360SMCparms_t smc1p;
654	rtems_unsigned8 _rsv8[0xF00-0xE80-sizeof(m360SMCparms_t)];
655	m360SCCparms_t scc4p;
656	rtems_unsigned8 _rsv9[0xF70-0xF00-sizeof(m360SCCparms_t)];
657	m360IDMAparms_t idma2p;
658	rtems_unsigned8 _rsv10[0xF80-0xF70-sizeof(m360IDMAparms_t)];
659	m360SMCparms_t smc2p;
660	rtems_unsigned8 _rsv11[0x1000-0xF80-sizeof(m360SMCparms_t)];
661
662	/*
663	* SIM Block
664	*/
665	rtems_unsigned32 mcr;
666	rtems_unsigned32 _pad00;
667	rtems_unsigned8 avr;
668	rtems_unsigned8 rsr;
669	rtems_unsigned16 _pad01;
670	rtems_unsigned8 clkocr;
671	rtems_unsigned8 _pad02;
672	rtems_unsigned16 _pad03;
673	rtems_unsigned16 pllcr;
674	rtems_unsigned16 _pad04;
675	rtems_unsigned16 cdvcr;
676	rtems_unsigned16 pepar;
677	rtems_unsigned32 _pad05[2];
678	rtems_unsigned16 _pad06;
679	rtems_unsigned8 sypcr;
680	rtems_unsigned8 swiv;
681	rtems_unsigned16 _pad07;
682	rtems_unsigned16 picr;
683	rtems_unsigned16 _pad08;
684	rtems_unsigned16 pitr;
685	rtems_unsigned16 _pad09;
686	rtems_unsigned8 _pad10;
687	rtems_unsigned8 swsr;
688	rtems_unsigned32 bkar;
689	rtems_unsigned32 bcar;
690	rtems_unsigned32 _pad11[2];
691
692	/*
693	* MEMC Block
694	*/
695	rtems_unsigned32 gmr;
696	rtems_unsigned16 mstat;
697	rtems_unsigned16 _pad12;
698	rtems_unsigned32 _pad13[2];
699	m360MEMCRegisters_t memc[8];
700	rtems_unsigned8 _pad14[0xF0-0xD0];
701	rtems_unsigned8 _pad15[0x100-0xF0];
702	rtems_unsigned8 _pad16[0x500-0x100];
703
704	/*
705	* IDMA1 Block
706	*/
707	rtems_unsigned16 iccr;
708	rtems_unsigned16 _pad17;
709	rtems_unsigned16 cmr1;
710	rtems_unsigned16 _pad18;
711	rtems_unsigned32 sapr1;
712	rtems_unsigned32 dapr1;
713	rtems_unsigned32 bcr1;
714	rtems_unsigned8 fcr1;
715	rtems_unsigned8 _pad19;
716	rtems_unsigned8 cmar1;
717	rtems_unsigned8 _pad20;
718	rtems_unsigned8 csr1;
719	rtems_unsigned8 _pad21;
720	rtems_unsigned16 _pad22;
721
722	/*
723	* SDMA Block
724	*/
725	rtems_unsigned8 sdsr;
726	rtems_unsigned8 _pad23;
727	rtems_unsigned16 sdcr;
728	rtems_unsigned32 sdar;
729
730	/*
731	* IDMA2 Block
732	*/
733	rtems_unsigned16 _pad24;
734	rtems_unsigned16 cmr2;
735	rtems_unsigned32 sapr2;
736	rtems_unsigned32 dapr2;
737	rtems_unsigned32 bcr2;
738	rtems_unsigned8 fcr2;
739	rtems_unsigned8 _pad26;
740	rtems_unsigned8 cmar2;
741	rtems_unsigned8 _pad27;
742	rtems_unsigned8 csr2;
743	rtems_unsigned8 _pad28;
744	rtems_unsigned16 _pad29;
745	rtems_unsigned32 _pad30;
746
747	/*
748	* CPIC Block
749	*/
750	rtems_unsigned32 cicr;
751	rtems_unsigned32 cipr;
752	rtems_unsigned32 cimr;
753	rtems_unsigned32 cisr;
754
755	/*
756	* Parallel I/O Block
757	*/
758	rtems_unsigned16 padir;
759	rtems_unsigned16 papar;
760	rtems_unsigned16 paodr;
761	rtems_unsigned16 padat;
762	rtems_unsigned32 _pad31[2];
763	rtems_unsigned16 pcdir;
764	rtems_unsigned16 pcpar;
765	rtems_unsigned16 pcso;
766	rtems_unsigned16 pcdat;
767	rtems_unsigned16 pcint;
768	rtems_unsigned16 _pad32;
769	rtems_unsigned32 _pad33[5];
770
771	/*
772	* TIMER Block
773	*/
774	rtems_unsigned16 tgcr;
775	rtems_unsigned16 _pad34;
776	rtems_unsigned32 _pad35[3];
777	rtems_unsigned16 tmr1;
778	rtems_unsigned16 tmr2;
779	rtems_unsigned16 trr1;
780	rtems_unsigned16 trr2;
781	rtems_unsigned16 tcr1;
782	rtems_unsigned16 tcr2;
783	rtems_unsigned16 tcn1;
784	rtems_unsigned16 tcn2;
785	rtems_unsigned16 tmr3;
786	rtems_unsigned16 tmr4;
787	rtems_unsigned16 trr3;
788	rtems_unsigned16 trr4;
789	rtems_unsigned16 tcr3;
790	rtems_unsigned16 tcr4;
791	rtems_unsigned16 tcn3;
792	rtems_unsigned16 tcn4;
793	rtems_unsigned16 ter1;
794	rtems_unsigned16 ter2;
795	rtems_unsigned16 ter3;
796	rtems_unsigned16 ter4;
797	rtems_unsigned32 _pad36[2];
798
799	/*
800	* CP Block
801	*/
802	rtems_unsigned16 cr;
803	rtems_unsigned16 _pad37;
804	rtems_unsigned16 rccr;
805	rtems_unsigned16 _pad38;
806	rtems_unsigned32 _pad39[3];
807	rtems_unsigned16 _pad40;
808	rtems_unsigned16 rter;
809	rtems_unsigned16 _pad41;
810	rtems_unsigned16 rtmr;
811	rtems_unsigned32 _pad42[5];
812
813	/*
814	* BRG Block
815	*/
816	rtems_unsigned32 brgc1;
817	rtems_unsigned32 brgc2;
818	rtems_unsigned32 brgc3;
819	rtems_unsigned32 brgc4;
820
821	/*
822	* SCC Block
823	*/
824	m360SCCRegisters_t scc1;
825	m360SCCRegisters_t scc2;
826	m360SCCRegisters_t scc3;
827	m360SCCRegisters_t scc4;
828
829	/*
830	* SMC Block
831	*/
832	m360SMCRegisters_t smc1;
833	m360SMCRegisters_t smc2;
834
835	/*
836	* SPI Block
837	*/
838	rtems_unsigned16 spmode;
839	rtems_unsigned16 _pad43[2];
840	rtems_unsigned8 spie;
841	rtems_unsigned8 _pad44;
842	rtems_unsigned16 _pad45;
843	rtems_unsigned8 spim;
844	rtems_unsigned8 _pad46[2];
845	rtems_unsigned8 spcom;
846	rtems_unsigned16 _pad47[2];
847
848	/*
849	* PIP Block
850	*/
851	rtems_unsigned16 pipc;
852	rtems_unsigned16 _pad48;
853	rtems_unsigned16 ptpr;
854	rtems_unsigned32 pbdir;
855	rtems_unsigned32 pbpar;
856	rtems_unsigned16 _pad49;
857	rtems_unsigned16 pbodr;
858	rtems_unsigned32 pbdat;
859	rtems_unsigned32 _pad50[6];
860
861	/*
862	* SI Block
863	*/
864	rtems_unsigned32 simode;
865	rtems_unsigned8 sigmr;
866	rtems_unsigned8 _pad51;
867	rtems_unsigned8 sistr;
868	rtems_unsigned8 sicmr;
869	rtems_unsigned32 _pad52;
870	rtems_unsigned32 sicr;
871	rtems_unsigned16 _pad53;
872	rtems_unsigned16 sirp[2];
873	rtems_unsigned16 _pad54;
874	rtems_unsigned32 _pad55[2];
875	rtems_unsigned8 siram[256];
876	} m360_t;
877
878	extern volatile m360_t m360;
879
880	#endif /* __MC68360_h */

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