[12710a56] | 1 | /* |
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| 2 | ************************************************************************** |
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| 3 | ************************************************************************** |
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| 4 | ** ** |
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| 5 | ** MOTOROLA MC68360 QUAD INTEGRATED COMMUNICATIONS CONTROLLER (QUICC) ** |
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| 6 | ** ** |
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| 7 | ** HARDWARE DECLARATIONS ** |
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| 8 | ** ** |
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| 9 | ** ** |
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| 10 | ** Submitted By: ** |
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| 11 | ** ** |
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| 12 | ** W. Eric Norum ** |
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| 13 | ** Saskatchewan Accelerator Laboratory ** |
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| 14 | ** University of Saskatchewan ** |
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| 15 | ** 107 North Road ** |
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| 16 | ** Saskatoon, Saskatchewan, CANADA ** |
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| 17 | ** S7N 5C6 ** |
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| 18 | ** ** |
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| 19 | ** eric@skatter.usask.ca ** |
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| 20 | ** ** |
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| 21 | ** $Id$ ** |
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| 22 | ** ** |
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| 23 | ************************************************************************** |
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| 24 | ************************************************************************** |
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| 25 | */ |
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| 26 | |
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| 27 | #ifndef __MC68360_h |
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| 28 | #define __MC68360_h |
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| 29 | |
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| 30 | /* |
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| 31 | ************************************************************************* |
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| 32 | * REGISTER SUBBLOCKS * |
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| 33 | ************************************************************************* |
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| 34 | */ |
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| 35 | |
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| 36 | /* |
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| 37 | * Memory controller registers |
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| 38 | */ |
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| 39 | typedef struct m360MEMCRegisters_ { |
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| 40 | unsigned long br; |
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| 41 | unsigned long or; |
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| 42 | unsigned long _pad[2]; |
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| 43 | } m360MEMCRegisters_t; |
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| 44 | |
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| 45 | /* |
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| 46 | * Serial Communications Controller registers |
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| 47 | */ |
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| 48 | typedef struct m360SCCRegisters_ { |
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| 49 | unsigned long gsmr_l; |
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| 50 | unsigned long gsmr_h; |
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| 51 | unsigned short psmr; |
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| 52 | unsigned short _pad0; |
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| 53 | unsigned short todr; |
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| 54 | unsigned short dsr; |
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| 55 | unsigned short scce; |
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| 56 | unsigned short _pad1; |
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| 57 | unsigned short sccm; |
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| 58 | unsigned char _pad2; |
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| 59 | unsigned char sccs; |
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| 60 | unsigned long _pad3[2]; |
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| 61 | } m360SCCRegisters_t; |
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| 62 | |
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| 63 | /* |
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| 64 | * Serial Management Controller registers |
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| 65 | */ |
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| 66 | typedef struct m360SMCRegisters_ { |
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| 67 | unsigned short _pad0; |
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| 68 | unsigned short smcmr; |
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| 69 | unsigned short _pad1; |
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| 70 | unsigned char smce; |
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| 71 | unsigned char _pad2; |
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| 72 | unsigned short _pad3; |
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| 73 | unsigned char smcm; |
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| 74 | unsigned char _pad4; |
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| 75 | unsigned long _pad5; |
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| 76 | } m360SMCRegisters_t; |
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| 77 | |
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| 78 | |
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| 79 | /* |
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| 80 | ************************************************************************* |
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| 81 | * Miscellaneous Parameters * |
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| 82 | ************************************************************************* |
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| 83 | */ |
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| 84 | typedef struct m360MiscParms_ { |
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| 85 | unsigned short rev_num; |
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| 86 | unsigned short _res1; |
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| 87 | unsigned long _res2; |
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| 88 | unsigned long _res3; |
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| 89 | } m360MiscParms_t; |
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| 90 | |
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| 91 | /* |
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| 92 | ************************************************************************* |
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| 93 | * RISC Timers * |
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| 94 | ************************************************************************* |
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| 95 | */ |
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| 96 | typedef struct m360TimerParms_ { |
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| 97 | unsigned short tm_base; |
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| 98 | unsigned short _tm_ptr; |
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| 99 | unsigned short _r_tmr; |
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| 100 | unsigned short _r_tmv; |
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| 101 | unsigned long tm_cmd; |
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| 102 | unsigned long tm_cnt; |
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| 103 | } m360TimerParms_t; |
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| 104 | |
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| 105 | /* |
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| 106 | * RISC Controller Configuration Register (RCCR) |
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| 107 | * All other bits in this register are either reserved or |
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| 108 | * used only with a Motorola-supplied RAM microcode packge. |
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| 109 | */ |
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| 110 | #define M360_RCCR_TIME (1<<15) /* Enable timer */ |
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| 111 | #define M360_RCCR_TIMEP(x) ((x)<<8) /* Timer period */ |
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| 112 | |
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| 113 | /* |
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| 114 | * Command register |
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| 115 | * Set up this register before issuing a M360_CR_OP_SET_TIMER command. |
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| 116 | */ |
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| 117 | #define M360_TM_CMD_V (1<<31) /* Set to enable timer */ |
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| 118 | #define M360_TM_CMD_R (1<<30) /* Set for automatic restart */ |
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| 119 | #define M360_TM_CMD_TIMER(x) ((x)<<16) /* Select timer */ |
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| 120 | #define M360_TM_CMD_PERIOD(x) (x) /* Timer period (16 bits) */ |
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| 121 | |
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| 122 | /* |
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| 123 | ************************************************************************* |
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| 124 | * DMA Controllers * |
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| 125 | ************************************************************************* |
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| 126 | */ |
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| 127 | typedef struct m360IDMAparms_ { |
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| 128 | unsigned short ibase; |
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| 129 | unsigned short ibptr; |
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| 130 | unsigned long _istate; |
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| 131 | unsigned long _itemp; |
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| 132 | } m360IDMAparms_t; |
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| 133 | |
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| 134 | /* |
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| 135 | ************************************************************************* |
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| 136 | * Serial Communication Controllers * |
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| 137 | ************************************************************************* |
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| 138 | */ |
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| 139 | typedef struct m360SCCparms_ { |
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| 140 | unsigned short rbase; |
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| 141 | unsigned short tbase; |
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| 142 | unsigned char rfcr; |
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| 143 | unsigned char tfcr; |
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| 144 | unsigned short mrblr; |
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| 145 | unsigned long _rstate; |
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| 146 | unsigned long _pad0; |
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| 147 | unsigned short _rbptr; |
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| 148 | unsigned short _pad1; |
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| 149 | unsigned long _pad2; |
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| 150 | unsigned long _tstate; |
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| 151 | unsigned long _pad3; |
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| 152 | unsigned short _tbptr; |
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| 153 | unsigned short _pad4; |
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| 154 | unsigned long _pad5; |
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| 155 | unsigned long _rcrc; |
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| 156 | unsigned long _tcrc; |
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| 157 | union { |
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| 158 | struct { |
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| 159 | unsigned long _res0; |
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| 160 | unsigned long _res1; |
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| 161 | unsigned short max_idl; |
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| 162 | unsigned short _idlc; |
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| 163 | unsigned short brkcr; |
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| 164 | unsigned short parec; |
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| 165 | unsigned short frmec; |
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| 166 | unsigned short nosec; |
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| 167 | unsigned short brkec; |
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| 168 | unsigned short brklen; |
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| 169 | unsigned short uaddr[2]; |
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| 170 | unsigned short _rtemp; |
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| 171 | unsigned short toseq; |
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| 172 | unsigned short character[8]; |
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| 173 | unsigned short rccm; |
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| 174 | unsigned short rccr; |
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| 175 | unsigned short rlbc; |
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| 176 | } uart; |
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| 177 | struct { |
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| 178 | unsigned long crc_p; |
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| 179 | unsigned long crc_c; |
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| 180 | } transparent; |
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| 181 | |
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| 182 | } un; |
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| 183 | } m360SCCparms_t; |
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| 184 | |
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| 185 | typedef struct m360SCCENparms_ { |
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| 186 | unsigned short rbase; |
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| 187 | unsigned short tbase; |
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| 188 | unsigned char rfcr; |
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| 189 | unsigned char tfcr; |
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| 190 | unsigned short mrblr; |
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| 191 | unsigned long _rstate; |
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| 192 | unsigned long _pad0; |
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| 193 | unsigned short _rbptr; |
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| 194 | unsigned short _pad1; |
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| 195 | unsigned long _pad2; |
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| 196 | unsigned long _tstate; |
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| 197 | unsigned long _pad3; |
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| 198 | unsigned short _tbptr; |
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| 199 | unsigned short _pad4; |
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| 200 | unsigned long _pad5; |
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| 201 | unsigned long _rcrc; |
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| 202 | unsigned long _tcrc; |
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| 203 | union { |
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| 204 | struct { |
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| 205 | unsigned long _res0; |
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| 206 | unsigned long _res1; |
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| 207 | unsigned short max_idl; |
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| 208 | unsigned short _idlc; |
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| 209 | unsigned short brkcr; |
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| 210 | unsigned short parec; |
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| 211 | unsigned short frmec; |
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| 212 | unsigned short nosec; |
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| 213 | unsigned short brkec; |
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| 214 | unsigned short brklen; |
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| 215 | unsigned short uaddr[2]; |
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| 216 | unsigned short _rtemp; |
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| 217 | unsigned short toseq; |
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| 218 | unsigned short character[8]; |
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| 219 | unsigned short rccm; |
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| 220 | unsigned short rccr; |
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| 221 | unsigned short rlbc; |
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| 222 | } uart; |
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| 223 | struct { |
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| 224 | unsigned long c_pres; |
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| 225 | unsigned long c_mask; |
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| 226 | unsigned long crcec; |
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| 227 | unsigned long alec; |
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| 228 | unsigned long disfc; |
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| 229 | unsigned short pads; |
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| 230 | unsigned short ret_lim; |
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| 231 | unsigned short _ret_cnt; |
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| 232 | unsigned short mflr; |
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| 233 | unsigned short minflr; |
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| 234 | unsigned short maxd1; |
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| 235 | unsigned short maxd2; |
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| 236 | unsigned short _maxd; |
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| 237 | unsigned short dma_cnt; |
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| 238 | unsigned short _max_b; |
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| 239 | unsigned short gaddr1; |
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| 240 | unsigned short gaddr2; |
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| 241 | unsigned short gaddr3; |
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| 242 | unsigned short gaddr4; |
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| 243 | unsigned long _tbuf0data0; |
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| 244 | unsigned long _tbuf0data1; |
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| 245 | unsigned long _tbuf0rba0; |
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| 246 | unsigned long _tbuf0crc; |
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| 247 | unsigned short _tbuf0bcnt; |
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| 248 | unsigned short paddr_h; |
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| 249 | unsigned short paddr_m; |
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| 250 | unsigned short paddr_l; |
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| 251 | unsigned short p_per; |
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| 252 | unsigned short _rfbd_ptr; |
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| 253 | unsigned short _tfbd_ptr; |
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| 254 | unsigned short _tlbd_ptr; |
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| 255 | unsigned long _tbuf1data0; |
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| 256 | unsigned long _tbuf1data1; |
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| 257 | unsigned long _tbuf1rba0; |
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| 258 | unsigned long _tbuf1crc; |
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| 259 | unsigned short _tbuf1bcnt; |
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| 260 | unsigned short _tx_len; |
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| 261 | unsigned short iaddr1; |
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| 262 | unsigned short iaddr2; |
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| 263 | unsigned short iaddr3; |
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| 264 | unsigned short iaddr4; |
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| 265 | unsigned short _boff_cnt; |
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| 266 | unsigned short taddr_h; |
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[089e1b04] | 267 | unsigned short taddr_m; |
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| 268 | unsigned short taddr_l; |
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[12710a56] | 269 | } ethernet; |
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| 270 | struct { |
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| 271 | unsigned long crc_p; |
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| 272 | unsigned long crc_c; |
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| 273 | } transparent; |
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| 274 | } un; |
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| 275 | } m360SCCENparms_t; |
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| 276 | |
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| 277 | /* |
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| 278 | * Receive and transmit function code register bits |
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| 279 | * These apply to the function code registers of all devices, not just SCC. |
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| 280 | */ |
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| 281 | #define M360_RFCR_MOT (1<<4) |
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| 282 | #define M360_RFCR_DMA_SPACE 0x8 |
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| 283 | #define M360_TFCR_MOT (1<<4) |
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| 284 | #define M360_TFCR_DMA_SPACE 0x8 |
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| 285 | |
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| 286 | /* |
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| 287 | ************************************************************************* |
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| 288 | * Serial Management Controllers * |
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| 289 | ************************************************************************* |
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| 290 | */ |
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| 291 | typedef struct m360SMCparms_ { |
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| 292 | unsigned short rbase; |
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| 293 | unsigned short tbase; |
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| 294 | unsigned char rfcr; |
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| 295 | unsigned char tfcr; |
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| 296 | unsigned short mrblr; |
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| 297 | unsigned long _rstate; |
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| 298 | unsigned long _pad0; |
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| 299 | unsigned short _rbptr; |
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| 300 | unsigned short _pad1; |
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| 301 | unsigned long _pad2; |
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| 302 | unsigned long _tstate; |
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| 303 | unsigned long _pad3; |
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| 304 | unsigned short _tbptr; |
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| 305 | unsigned short _pad4; |
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| 306 | unsigned long _pad5; |
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| 307 | union { |
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| 308 | struct { |
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| 309 | unsigned short max_idl; |
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| 310 | unsigned short _pad0; |
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| 311 | unsigned short brklen; |
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| 312 | unsigned short brkec; |
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| 313 | unsigned short brkcr; |
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| 314 | unsigned short _r_mask; |
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| 315 | } uart; |
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| 316 | struct { |
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| 317 | unsigned short _pad0[5]; |
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| 318 | } transparent; |
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| 319 | } un; |
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| 320 | } m360SMCparms_t; |
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| 321 | |
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| 322 | /* |
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| 323 | * Mode register |
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| 324 | */ |
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| 325 | #define M360_SMCMR_CLEN(x) ((x)<<11) /* Character length */ |
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| 326 | #define M360_SMCMR_2STOP (1<<10) /* 2 stop bits */ |
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| 327 | #define M360_SMCMR_PARITY (1<<9) /* Enable parity */ |
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| 328 | #define M360_SMCMR_EVEN (1<<8) /* Even parity */ |
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| 329 | #define M360_SMCMR_SM_GCI (0<<4) /* GCI Mode */ |
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| 330 | #define M360_SMCMR_SM_UART (2<<4) /* UART Mode */ |
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| 331 | #define M360_SMCMR_SM_TRANSPARENT (3<<4) /* Transparent Mode */ |
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| 332 | #define M360_SMCMR_DM_LOOPBACK (1<<2) /* Local loopback mode */ |
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| 333 | #define M360_SMCMR_DM_ECHO (2<<2) /* Echo mode */ |
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| 334 | #define M360_SMCMR_TEN (1<<1) /* Enable transmitter */ |
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| 335 | #define M360_SMCMR_REN (1<<0) /* Enable receiver */ |
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| 336 | |
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| 337 | /* |
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| 338 | * Event and mask registers (SMCE, SMCM) |
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| 339 | */ |
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| 340 | #define M360_SMCE_BRK (1<<4) |
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| 341 | #define M360_SMCE_BSY (1<<2) |
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| 342 | #define M360_SMCE_TX (1<<1) |
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| 343 | #define M360_SMCE_RX (1<<0) |
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| 344 | |
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| 345 | /* |
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| 346 | ************************************************************************* |
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| 347 | * Serial Peripheral Interface * |
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| 348 | ************************************************************************* |
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| 349 | */ |
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| 350 | typedef struct m360SPIparms_ { |
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| 351 | unsigned short rbase; |
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| 352 | unsigned short tbase; |
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| 353 | unsigned char rfcr; |
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| 354 | unsigned char tfcr; |
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| 355 | unsigned short mrblr; |
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| 356 | unsigned long _rstate; |
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| 357 | unsigned long _pad0; |
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| 358 | unsigned short _rbptr; |
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| 359 | unsigned short _pad1; |
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| 360 | unsigned long _pad2; |
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| 361 | unsigned long _tstate; |
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| 362 | unsigned long _pad3; |
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| 363 | unsigned short _tbptr; |
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| 364 | unsigned short _pad4; |
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| 365 | unsigned long _pad5; |
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| 366 | } m360SPIparms_t; |
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| 367 | |
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| 368 | /* |
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| 369 | * Mode register (SPMODE) |
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| 370 | */ |
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| 371 | #define M360_SPMODE_LOOP (1<<14) /* Local loopback mode */ |
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| 372 | #define M360_SPMODE_CI (1<<13) /* Clock invert */ |
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| 373 | #define M360_SPMODE_CP (1<<12) /* Clock phase */ |
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| 374 | #define M360_SPMODE_DIV16 (1<<11) /* Divide BRGCLK by 16 */ |
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| 375 | #define M360_SPMODE_REV (1<<10) /* Reverse data */ |
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| 376 | #define M360_SPMODE_MASTER (1<<9) /* SPI is master */ |
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| 377 | #define M360_SPMODE_EN (1<<8) /* Enable SPI */ |
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| 378 | #define M360_SPMODE_CLEN(x) ((x)<<4) /* Character length */ |
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| 379 | #define M360_SPMODE_PM(x) (x) /* Prescaler modulus */ |
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| 380 | |
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| 381 | /* |
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| 382 | * Mode register (SPCOM) |
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| 383 | */ |
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| 384 | #define M360_SPCOM_STR (1<<7) /* Start transmit */ |
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| 385 | |
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| 386 | /* |
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| 387 | * Event and mask registers (SPIE, SPIM) |
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| 388 | */ |
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| 389 | #define M360_SPIE_MME (1<<5) /* Multi-master error */ |
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| 390 | #define M360_SPIE_TXE (1<<4) /* Tx error */ |
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| 391 | #define M360_SPIE_BSY (1<<2) /* Busy condition*/ |
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| 392 | #define M360_SPIE_TXB (1<<1) /* Tx buffer */ |
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| 393 | #define M360_SPIE_RXB (1<<0) /* Rx buffer */ |
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| 394 | |
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| 395 | /* |
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| 396 | ************************************************************************* |
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| 397 | * SDMA (SCC, SMC, SPI) Buffer Descriptors * |
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| 398 | ************************************************************************* |
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| 399 | */ |
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| 400 | typedef struct m360BufferDescriptor_ { |
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| 401 | unsigned short status; |
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| 402 | unsigned short length; |
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| 403 | volatile void *buffer; |
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| 404 | } m360BufferDescriptor_t; |
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| 405 | |
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| 406 | /* |
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| 407 | * Bits in receive buffer descriptor status word |
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| 408 | */ |
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| 409 | #define M360_BD_EMPTY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ |
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| 410 | #define M360_BD_WRAP (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */ |
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| 411 | #define M360_BD_INTERRUPT (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */ |
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| 412 | #define M360_BD_LAST (1<<11) /* Ethernet, SPI */ |
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| 413 | #define M360_BD_CONTROL_CHAR (1<<11) /* SCC UART */ |
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| 414 | #define M360_BD_FIRST_IN_FRAME (1<<10) /* Ethernet */ |
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| 415 | #define M360_BD_ADDRESS (1<<10) /* SCC UART */ |
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| 416 | #define M360_BD_CONTINUOUS (1<<9) /* SCC UART, SMC UART, SPI */ |
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| 417 | #define M360_BD_MISS (1<<8) /* Ethernet */ |
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| 418 | #define M360_BD_IDLE (1<<8) /* SCC UART, SMC UART */ |
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| 419 | #define M360_BD_ADDRSS_MATCH (1<<7) /* SCC UART */ |
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| 420 | #define M360_BD_LONG (1<<5) /* Ethernet */ |
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| 421 | #define M360_BD_BREAK (1<<5) /* SCC UART, SMC UART */ |
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| 422 | #define M360_BD_NONALIGNED (1<<4) /* Ethernet */ |
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| 423 | #define M360_BD_FRAMING_ERROR (1<<4) /* SCC UART, SMC UART */ |
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| 424 | #define M360_BD_SHORT (1<<3) /* Ethernet */ |
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| 425 | #define M360_BD_PARITY_ERROR (1<<3) /* SCC UART, SMC UART */ |
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| 426 | #define M360_BD_CRC_ERROR (1<<2) /* Ethernet */ |
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| 427 | #define M360_BD_OVERRUN (1<<1) /* Ethernet, SCC UART, SMC UART, SPI */ |
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| 428 | #define M360_BD_COLLISION (1<<0) /* Ethernet */ |
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| 429 | #define M360_BD_CARRIER_LOST (1<<0) /* SCC UART */ |
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| 430 | #define M360_BD_MASTER_ERROR (1<<0) /* SPI */ |
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| 431 | |
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| 432 | /* |
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| 433 | * Bits in transmit buffer descriptor status word |
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| 434 | * Many bits have the same meaning as those in receiver buffer descriptors. |
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| 435 | */ |
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| 436 | #define M360_BD_READY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ |
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| 437 | #define M360_BD_PAD (1<<14) /* Ethernet */ |
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| 438 | #define M360_BD_CTS_REPORT (1<<11) /* SCC UART */ |
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| 439 | #define M360_BD_TX_CRC (1<<10) /* Ethernet */ |
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| 440 | #define M360_BD_DEFER (1<<9) /* Ethernet */ |
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| 441 | #define M360_BD_HEARTBEAT (1<<8) /* Ethernet */ |
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| 442 | #define M360_BD_PREAMBLE (1<<8) /* SCC UART, SMC UART */ |
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| 443 | #define M360_BD_LATE_COLLISION (1<<7) /* Ethernet */ |
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| 444 | #define M360_BD_NO_STOP_BIT (1<<7) /* SCC UART */ |
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| 445 | #define M360_BD_RETRY_LIMIT (1<<6) /* Ethernet */ |
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| 446 | #define M360_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) /* Ethernet */ |
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| 447 | #define M360_BD_UNDERRUN (1<<1) /* Ethernet, SPI */ |
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| 448 | #define M360_BD_CARRIER_LOST (1<<0) /* Ethernet */ |
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| 449 | #define M360_BD_CTS_LOST (1<<0) /* SCC UART */ |
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| 450 | |
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| 451 | /* |
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| 452 | ************************************************************************* |
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| 453 | * IDMA Buffer Descriptors * |
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| 454 | ************************************************************************* |
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| 455 | */ |
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| 456 | typedef struct m360IDMABufferDescriptor_ { |
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| 457 | unsigned short status; |
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| 458 | unsigned short _pad; |
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| 459 | unsigned long length; |
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| 460 | void *source; |
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| 461 | void *destination; |
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| 462 | } m360IDMABufferDescriptor_t; |
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| 463 | |
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| 464 | /* |
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| 465 | ************************************************************************* |
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| 466 | * RISC Communication Processor Module Command Register (CR) * |
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| 467 | ************************************************************************* |
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| 468 | */ |
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| 469 | #define M360_CR_RST (1<<15) /* Reset communication processor */ |
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| 470 | #define M360_CR_OP_INIT_RX_TX (0<<8) /* SCC, SMC UART, SMC GCI, SPI */ |
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| 471 | #define M360_CR_OP_INIT_RX (1<<8) /* SCC, SMC UART, SPI */ |
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| 472 | #define M360_CR_OP_INIT_TX (2<<8) /* SCC, SMC UART, SPI */ |
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| 473 | #define M360_CR_OP_INIT_HUNT (3<<8) /* SCC, SMC UART */ |
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| 474 | #define M360_CR_OP_STOP_TX (4<<8) /* SCC, SMC UART */ |
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| 475 | #define M360_CR_OP_GR_STOP_TX (5<<8) /* SCC */ |
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| 476 | #define M360_CR_OP_INIT_IDMA (5<<8) /* IDMA */ |
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| 477 | #define M360_CR_OP_RESTART_TX (6<<8) /* SCC, SMC UART */ |
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| 478 | #define M360_CR_OP_CLOSE_RX_BD (7<<8) /* SCC, SMC UART, SPI */ |
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| 479 | #define M360_CR_OP_SET_GRP_ADDR (8<<8) /* SCC */ |
---|
| 480 | #define M360_CR_OP_SET_TIMER (8<<8) /* Timer */ |
---|
| 481 | #define M360_CR_OP_GCI_TIMEOUT (9<<8) /* SMC GCI */ |
---|
| 482 | #define M360_CR_OP_RESERT_BCS (10<<8) /* SCC */ |
---|
| 483 | #define M360_CR_OP_GCI_ABORT (10<<8) /* SMC GCI */ |
---|
| 484 | #define M360_CR_CHAN_SCC1 (0<<4) /* Channel selection */ |
---|
| 485 | #define M360_CR_CHAN_SCC2 (4<<4) |
---|
| 486 | #define M360_CR_CHAN_SPI (5<<4) |
---|
| 487 | #define M360_CR_CHAN_TIMER (5<<4) |
---|
| 488 | #define M360_CR_CHAN_SCC3 (8<<4) |
---|
| 489 | #define M360_CR_CHAN_SMC1 (9<<4) |
---|
| 490 | #define M360_CR_CHAN_IDMA1 (9<<4) |
---|
| 491 | #define M360_CR_CHAN_SCC4 (12<<4) |
---|
| 492 | #define M360_CR_CHAN_SMC2 (13<<4) |
---|
| 493 | #define M360_CR_CHAN_IDMA2 (13<<4) |
---|
| 494 | #define M360_CR_FLG (1<<0) /* Command flag */ |
---|
| 495 | |
---|
| 496 | /* |
---|
| 497 | ************************************************************************* |
---|
| 498 | * System Protection Control Register (SYPCR) * |
---|
| 499 | ************************************************************************* |
---|
| 500 | */ |
---|
| 501 | #define M360_SYPCR_SWE (1<<7) /* Software watchdog enable */ |
---|
| 502 | #define M360_SYPCR_SWRI (1<<6) /* Software watchdog reset select */ |
---|
| 503 | #define M360_SYPCR_SWT1 (1<<5) /* Software watchdog timing bit 1 */ |
---|
| 504 | #define M360_SYPCR_SWT0 (1<<4) /* Software watchdog timing bit 0 */ |
---|
| 505 | #define M360_SYPCR_DBFE (1<<3) /* Double bus fault monitor enable */ |
---|
| 506 | #define M360_SYPCR_BME (1<<2) /* Bus monitor external enable */ |
---|
| 507 | #define M360_SYPCR_BMT1 (1<<1) /* Bus monitor timing bit 1 */ |
---|
| 508 | #define M360_SYPCR_BMT0 (1<<0) /* Bus monitor timing bit 0 */ |
---|
| 509 | |
---|
| 510 | /* |
---|
| 511 | ************************************************************************* |
---|
| 512 | * Memory Control Registers * |
---|
| 513 | ************************************************************************* |
---|
| 514 | */ |
---|
| 515 | #define M360_GMR_RCNT(x) ((x)<<24) /* Refresh count */ |
---|
| 516 | #define M360_GMR_RFEN (1<<23) /* Refresh enable */ |
---|
| 517 | #define M360_GMR_RCYC(x) ((x)<<21) /* Refresh cycle length */ |
---|
| 518 | #define M360_GMR_PGS(x) ((x)<<18) /* Page size */ |
---|
| 519 | #define M360_GMR_DPS_32BIT (0<<16) /* DRAM port size */ |
---|
| 520 | #define M360_GMR_DPS_16BIT (1<<16) |
---|
| 521 | #define M360_GMR_DPS_8BIT (2<<16) |
---|
| 522 | #define M360_GMR_DPS_DSACK (3<<16) |
---|
| 523 | #define M360_GMR_WBT40 (1<<15) /* Wait between 040 transfers */ |
---|
| 524 | #define M360_GMR_WBTQ (1<<14) /* Wait between 360 transfers */ |
---|
| 525 | #define M360_GMR_SYNC (1<<13) /* Synchronous external access */ |
---|
| 526 | #define M360_GMR_EMWS (1<<12) /* External master wait state */ |
---|
| 527 | #define M360_GMR_OPAR (1<<11) /* Odd parity */ |
---|
| 528 | #define M360_GMR_PBEE (1<<10) /* Parity bus error enable */ |
---|
| 529 | #define M360_GMR_TSS40 (1<<9) /* TS* sample for 040 */ |
---|
| 530 | #define M360_GMR_NCS (1<<8) /* No CPU space */ |
---|
| 531 | #define M360_GMR_DWQ (1<<7) /* Delay write for 360 */ |
---|
| 532 | #define M360_GMR_DW40 (1<<6) /* Delay write for 040 */ |
---|
| 533 | #define M360_GMR_GAMX (1<<5) /* Global address mux enable */ |
---|
| 534 | |
---|
| 535 | #define M360_MEMC_BR_FC(x) ((x)<<7) /* Function code limit */ |
---|
| 536 | #define M360_MEMC_BR_TRLXQ (1<<6) /* Relax timing requirements */ |
---|
| 537 | #define M360_MEMC_BR_BACK40 (1<<5) /* Burst acknowledge to 040 */ |
---|
| 538 | #define M360_MEMC_BR_CSNT40 (1<<4) /* CS* negate timing for 040 */ |
---|
| 539 | #define M360_MEMC_BR_CSNTQ (1<<3) /* CS* negate timing for 360 */ |
---|
| 540 | #define M360_MEMC_BR_PAREN (1<<2) /* Enable parity checking */ |
---|
| 541 | #define M360_MEMC_BR_WP (1<<1) /* Write Protect */ |
---|
| 542 | #define M360_MEMC_BR_V (1<<0) /* Base/Option register are valid */ |
---|
| 543 | |
---|
| 544 | #define M360_MEMC_OR_TCYC(x) ((x)<<28) /* Cycle length (clocks) */ |
---|
| 545 | #define M360_MEMC_OR_WAITS(x) M360_MEMC_OR_TCYC((x)+1) |
---|
| 546 | #define M360_MEMC_OR_2KB 0x0FFFF800 /* Address range */ |
---|
| 547 | #define M360_MEMC_OR_4KB 0x0FFFF000 |
---|
| 548 | #define M360_MEMC_OR_8KB 0x0FFFE000 |
---|
| 549 | #define M360_MEMC_OR_16KB 0x0FFFC000 |
---|
| 550 | #define M360_MEMC_OR_32KB 0x0FFF8000 |
---|
| 551 | #define M360_MEMC_OR_64KB 0x0FFF0000 |
---|
| 552 | #define M360_MEMC_OR_128KB 0x0FFE0000 |
---|
| 553 | #define M360_MEMC_OR_256KB 0x0FFC0000 |
---|
| 554 | #define M360_MEMC_OR_512KB 0x0FF80000 |
---|
| 555 | #define M360_MEMC_OR_1MB 0x0FF00000 |
---|
| 556 | #define M360_MEMC_OR_2MB 0x0FE00000 |
---|
| 557 | #define M360_MEMC_OR_4MB 0x0FC00000 |
---|
| 558 | #define M360_MEMC_OR_8MB 0x0F800000 |
---|
| 559 | #define M360_MEMC_OR_16MB 0x0F000000 |
---|
| 560 | #define M360_MEMC_OR_32MB 0x0E000000 |
---|
| 561 | #define M360_MEMC_OR_64MB 0x0C000000 |
---|
| 562 | #define M360_MEMC_OR_128MB 0x08000000 |
---|
| 563 | #define M360_MEMC_OR_256MB 0x00000000 |
---|
| 564 | #define M360_MEMC_OR_FCMC(x) ((x)<<7) /* Function code mask */ |
---|
| 565 | #define M360_MEMC_OR_BCYC(x) ((x)<<5) /* Burst cycle length (clocks) */ |
---|
| 566 | #define M360_MEMC_OR_PGME (1<<3) /* Page mode enable */ |
---|
| 567 | #define M360_MEMC_OR_32BIT (0<<1) /* Port size */ |
---|
| 568 | #define M360_MEMC_OR_16BIT (1<<1) |
---|
| 569 | #define M360_MEMC_OR_8BIT (2<<1) |
---|
| 570 | #define M360_MEMC_OR_DSACK (3<<1) |
---|
| 571 | #define M360_MEMC_OR_DRAM (1<<0) /* Dynamic RAM select */ |
---|
| 572 | |
---|
| 573 | /* |
---|
| 574 | ************************************************************************* |
---|
| 575 | * SI Mode Register (SIMODE) * |
---|
| 576 | ************************************************************************* |
---|
| 577 | */ |
---|
| 578 | #define M360_SI_SMC2_BITS 0xFFFF0000 /* All SMC2 bits */ |
---|
| 579 | #define M360_SI_SMC2_TDM (1<<31) /* Multiplexed SMC2 */ |
---|
| 580 | #define M360_SI_SMC2_BRG1 (0<<28) /* SMC2 clock souce */ |
---|
| 581 | #define M360_SI_SMC2_BRG2 (1<<28) |
---|
| 582 | #define M360_SI_SMC2_BRG3 (2<<28) |
---|
| 583 | #define M360_SI_SMC2_BRG4 (3<<28) |
---|
| 584 | #define M360_SI_SMC2_CLK5 (0<<28) |
---|
| 585 | #define M360_SI_SMC2_CLK6 (1<<28) |
---|
| 586 | #define M360_SI_SMC2_CLK7 (2<<28) |
---|
| 587 | #define M360_SI_SMC2_CLK8 (3<<28) |
---|
| 588 | #define M360_SI_SMC1_BITS 0x0000FFFF /* All SMC1 bits */ |
---|
| 589 | #define M360_SI_SMC1_TDM (1<<15) /* Multiplexed SMC1 */ |
---|
| 590 | #define M360_SI_SMC1_BRG1 (0<<12) /* SMC1 clock souce */ |
---|
| 591 | #define M360_SI_SMC1_BRG2 (1<<12) |
---|
| 592 | #define M360_SI_SMC1_BRG3 (2<<12) |
---|
| 593 | #define M360_SI_SMC1_BRG4 (3<<12) |
---|
| 594 | #define M360_SI_SMC1_CLK1 (0<<12) |
---|
| 595 | #define M360_SI_SMC1_CLK2 (1<<12) |
---|
| 596 | #define M360_SI_SMC1_CLK3 (2<<12) |
---|
| 597 | #define M360_SI_SMC1_CLK4 (3<<12) |
---|
| 598 | |
---|
| 599 | /* |
---|
| 600 | ************************************************************************* |
---|
| 601 | * SDMA Configuration Register (SDMA) * |
---|
| 602 | ************************************************************************* |
---|
| 603 | */ |
---|
| 604 | #define M360_SDMA_FREEZE (2<<13) /* Freeze on next bus cycle */ |
---|
| 605 | #define M360_SDMA_SISM_7 (7<<8) /* Normal interrupt service mask */ |
---|
| 606 | #define M360_SDMA_SAID_4 (4<<4) /* Normal arbitration ID */ |
---|
| 607 | #define M360_SDMA_INTE (1<<1) /* SBER interrupt enable */ |
---|
| 608 | #define M360_SDMA_INTB (1<<0) /* SBKP interrupt enable */ |
---|
| 609 | |
---|
| 610 | /* |
---|
| 611 | ************************************************************************* |
---|
| 612 | * Baud (sic) Rate Generators * |
---|
| 613 | ************************************************************************* |
---|
| 614 | */ |
---|
| 615 | #define M360_BRG_RST (1<<17) /* Reset generator */ |
---|
| 616 | #define M360_BRG_EN (1<<16) /* Enable generator */ |
---|
| 617 | #define M360_BRG_EXTC_BRGCLK (0<<14) /* Source is BRGCLK */ |
---|
| 618 | #define M360_BRG_EXTC_CLK2 (1<<14) /* Source is CLK2 pin */ |
---|
| 619 | #define M360_BRG_EXTC_CLK6 (2<<14) /* Source is CLK6 pin */ |
---|
| 620 | #define M360_BRG_ATB (1<<13) /* Autobaud */ |
---|
| 621 | #define M360_BRG_115200 (13<<1) /* Assume 25 MHz clock */ |
---|
| 622 | #define M360_BRG_57600 (26<<1) |
---|
| 623 | #define M360_BRG_38400 (40<<1) |
---|
| 624 | #define M360_BRG_19200 (80<<1) |
---|
| 625 | #define M360_BRG_9600 (162<<1) |
---|
| 626 | #define M360_BRG_4800 (324<<1) |
---|
| 627 | #define M360_BRG_2400 (650<<1) |
---|
| 628 | #define M360_BRG_1200 (1301<<1) |
---|
| 629 | #define M360_BRG_600 (2603<<1) |
---|
| 630 | #define M360_BRG_300 ((324<<1) | 1) |
---|
| 631 | #define M360_BRG_150 ((650<<1) | 1) |
---|
| 632 | #define M360_BRG_75 ((1301<<1) | 1) |
---|
| 633 | |
---|
| 634 | /* |
---|
| 635 | ************************************************************************* |
---|
| 636 | * MC68360 DUAL-PORT RAM AND REGISTERS * |
---|
| 637 | ************************************************************************* |
---|
| 638 | */ |
---|
| 639 | typedef struct m360_ { |
---|
| 640 | /* |
---|
| 641 | * Dual-port RAM |
---|
| 642 | */ |
---|
| 643 | unsigned char dpram0[0x400]; /* Microcode program */ |
---|
| 644 | unsigned char dpram1[0x200]; |
---|
| 645 | unsigned char dpram2[0x100]; /* Microcode scratch */ |
---|
| 646 | unsigned char dpram3[0x100]; /* Not on REV A or B masks */ |
---|
| 647 | unsigned char _rsv0[0xC00-0x800]; |
---|
| 648 | m360SCCENparms_t scc1p; |
---|
| 649 | unsigned char _rsv1[0xCB0-0xC00-sizeof(m360SCCENparms_t)]; |
---|
| 650 | m360MiscParms_t miscp; |
---|
| 651 | unsigned char _rsv2[0xD00-0xCB0-sizeof(m360MiscParms_t)]; |
---|
| 652 | m360SCCparms_t scc2p; |
---|
| 653 | unsigned char _rsv3[0xD80-0xD00-sizeof(m360SCCparms_t)]; |
---|
| 654 | m360SPIparms_t spip; |
---|
| 655 | unsigned char _rsv4[0xDB0-0xD80-sizeof(m360SPIparms_t)]; |
---|
| 656 | m360TimerParms_t tmp; |
---|
| 657 | unsigned char _rsv5[0xE00-0xDB0-sizeof(m360TimerParms_t)]; |
---|
| 658 | m360SCCparms_t scc3p; |
---|
| 659 | unsigned char _rsv6[0xE70-0xE00-sizeof(m360SCCparms_t)]; |
---|
| 660 | m360IDMAparms_t idma1p; |
---|
| 661 | unsigned char _rsv7[0xE80-0xE70-sizeof(m360IDMAparms_t)]; |
---|
| 662 | m360SMCparms_t smc1p; |
---|
| 663 | unsigned char _rsv8[0xF00-0xE80-sizeof(m360SMCparms_t)]; |
---|
| 664 | m360SCCparms_t scc4p; |
---|
| 665 | unsigned char _rsv9[0xF70-0xF00-sizeof(m360SCCparms_t)]; |
---|
| 666 | m360IDMAparms_t idma2p; |
---|
| 667 | unsigned char _rsv10[0xF80-0xF70-sizeof(m360IDMAparms_t)]; |
---|
| 668 | m360SMCparms_t smc2p; |
---|
| 669 | unsigned char _rsv11[0x1000-0xF80-sizeof(m360SMCparms_t)]; |
---|
| 670 | |
---|
| 671 | /* |
---|
| 672 | * SIM Block |
---|
| 673 | */ |
---|
| 674 | unsigned long mcr; |
---|
| 675 | unsigned long _pad00; |
---|
| 676 | unsigned char avr; |
---|
| 677 | unsigned char rsr; |
---|
| 678 | unsigned short _pad01; |
---|
| 679 | unsigned char clkocr; |
---|
| 680 | unsigned char _pad02; |
---|
| 681 | unsigned short _pad03; |
---|
| 682 | unsigned short pllcr; |
---|
| 683 | unsigned short _pad04; |
---|
| 684 | unsigned short cdvcr; |
---|
| 685 | unsigned short pepar; |
---|
| 686 | unsigned long _pad05[2]; |
---|
| 687 | unsigned short _pad06; |
---|
| 688 | unsigned char sypcr; |
---|
| 689 | unsigned char swiv; |
---|
| 690 | unsigned short _pad07; |
---|
| 691 | unsigned short picr; |
---|
| 692 | unsigned short _pad08; |
---|
| 693 | unsigned short pitr; |
---|
| 694 | unsigned short _pad09; |
---|
| 695 | unsigned char _pad10; |
---|
| 696 | unsigned char swsr; |
---|
| 697 | unsigned long bkar; |
---|
| 698 | unsigned long bcar; |
---|
| 699 | unsigned long _pad11[2]; |
---|
| 700 | |
---|
| 701 | /* |
---|
| 702 | * MEMC Block |
---|
| 703 | */ |
---|
| 704 | unsigned long gmr; |
---|
| 705 | unsigned short mstat; |
---|
| 706 | unsigned short _pad12; |
---|
| 707 | unsigned long _pad13[2]; |
---|
| 708 | m360MEMCRegisters_t memc[8]; |
---|
| 709 | unsigned char _pad14[0xF0-0xD0]; |
---|
| 710 | unsigned char _pad15[0x100-0xF0]; |
---|
| 711 | unsigned char _pad16[0x500-0x100]; |
---|
| 712 | |
---|
| 713 | /* |
---|
| 714 | * IDMA1 Block |
---|
| 715 | */ |
---|
| 716 | unsigned short iccr; |
---|
| 717 | unsigned short _pad17; |
---|
| 718 | unsigned short cmr1; |
---|
| 719 | unsigned short _pad18; |
---|
| 720 | unsigned long sapr1; |
---|
| 721 | unsigned long dapr1; |
---|
| 722 | unsigned long bcr1; |
---|
| 723 | unsigned char fcr1; |
---|
| 724 | unsigned char _pad19; |
---|
| 725 | unsigned char cmar1; |
---|
| 726 | unsigned char _pad20; |
---|
| 727 | unsigned char csr1; |
---|
| 728 | unsigned char _pad21; |
---|
| 729 | unsigned short _pad22; |
---|
| 730 | |
---|
| 731 | /* |
---|
| 732 | * SDMA Block |
---|
| 733 | */ |
---|
| 734 | unsigned char sdsr; |
---|
| 735 | unsigned char _pad23; |
---|
| 736 | unsigned short sdcr; |
---|
| 737 | unsigned long sdar; |
---|
| 738 | |
---|
| 739 | /* |
---|
| 740 | * IDMA2 Block |
---|
| 741 | */ |
---|
| 742 | unsigned short _pad24; |
---|
| 743 | unsigned short cmr2; |
---|
| 744 | unsigned long sapr2; |
---|
| 745 | unsigned long dapr2; |
---|
| 746 | unsigned long bcr2; |
---|
| 747 | unsigned char fcr2; |
---|
| 748 | unsigned char _pad26; |
---|
| 749 | unsigned char cmar2; |
---|
| 750 | unsigned char _pad27; |
---|
| 751 | unsigned char csr2; |
---|
| 752 | unsigned char _pad28; |
---|
| 753 | unsigned short _pad29; |
---|
| 754 | unsigned long _pad30; |
---|
| 755 | |
---|
| 756 | /* |
---|
| 757 | * CPIC Block |
---|
| 758 | */ |
---|
| 759 | unsigned long cicr; |
---|
| 760 | unsigned long cipr; |
---|
| 761 | unsigned long cimr; |
---|
| 762 | unsigned long cisr; |
---|
| 763 | |
---|
| 764 | /* |
---|
| 765 | * Parallel I/O Block |
---|
| 766 | */ |
---|
| 767 | unsigned short padir; |
---|
| 768 | unsigned short papar; |
---|
| 769 | unsigned short paodr; |
---|
| 770 | unsigned short padat; |
---|
| 771 | unsigned long _pad31[2]; |
---|
| 772 | unsigned short pcdir; |
---|
| 773 | unsigned short pcpar; |
---|
| 774 | unsigned short pcso; |
---|
| 775 | unsigned short pcdat; |
---|
| 776 | unsigned short pcint; |
---|
| 777 | unsigned short _pad32; |
---|
| 778 | unsigned long _pad33[5]; |
---|
| 779 | |
---|
| 780 | /* |
---|
| 781 | * TIMER Block |
---|
| 782 | */ |
---|
| 783 | unsigned short tgcr; |
---|
| 784 | unsigned short _pad34; |
---|
| 785 | unsigned long _pad35[3]; |
---|
| 786 | unsigned short tmr1; |
---|
| 787 | unsigned short tmr2; |
---|
| 788 | unsigned short trr1; |
---|
| 789 | unsigned short trr2; |
---|
| 790 | unsigned short tcr1; |
---|
| 791 | unsigned short tcr2; |
---|
| 792 | unsigned short tcn1; |
---|
| 793 | unsigned short tcn2; |
---|
| 794 | unsigned short tmr3; |
---|
| 795 | unsigned short tmr4; |
---|
| 796 | unsigned short trr3; |
---|
| 797 | unsigned short trr4; |
---|
| 798 | unsigned short tcr3; |
---|
| 799 | unsigned short tcr4; |
---|
| 800 | unsigned short tcn3; |
---|
| 801 | unsigned short tcn4; |
---|
| 802 | unsigned short ter1; |
---|
| 803 | unsigned short ter2; |
---|
| 804 | unsigned short ter3; |
---|
| 805 | unsigned short ter4; |
---|
| 806 | unsigned long _pad36[2]; |
---|
| 807 | |
---|
| 808 | /* |
---|
| 809 | * CP Block |
---|
| 810 | */ |
---|
| 811 | unsigned short cr; |
---|
| 812 | unsigned short _pad37; |
---|
| 813 | unsigned short rccr; |
---|
| 814 | unsigned short _pad38; |
---|
| 815 | unsigned long _pad39[3]; |
---|
| 816 | unsigned short _pad40; |
---|
| 817 | unsigned short rter; |
---|
| 818 | unsigned short _pad41; |
---|
| 819 | unsigned short rtmr; |
---|
| 820 | unsigned long _pad42[5]; |
---|
| 821 | |
---|
| 822 | /* |
---|
| 823 | * BRG Block |
---|
| 824 | */ |
---|
| 825 | unsigned long brgc1; |
---|
| 826 | unsigned long brgc2; |
---|
| 827 | unsigned long brgc3; |
---|
| 828 | unsigned long brgc4; |
---|
| 829 | |
---|
| 830 | /* |
---|
| 831 | * SCC Block |
---|
| 832 | */ |
---|
| 833 | m360SCCRegisters_t scc1; |
---|
| 834 | m360SCCRegisters_t scc2; |
---|
| 835 | m360SCCRegisters_t scc3; |
---|
| 836 | m360SCCRegisters_t scc4; |
---|
| 837 | |
---|
| 838 | /* |
---|
| 839 | * SMC Block |
---|
| 840 | */ |
---|
| 841 | m360SMCRegisters_t smc1; |
---|
| 842 | m360SMCRegisters_t smc2; |
---|
| 843 | |
---|
| 844 | /* |
---|
| 845 | * SPI Block |
---|
| 846 | */ |
---|
| 847 | unsigned short spmode; |
---|
| 848 | unsigned short _pad43[2]; |
---|
| 849 | unsigned char spie; |
---|
| 850 | unsigned char _pad44; |
---|
| 851 | unsigned short _pad45; |
---|
| 852 | unsigned char spim; |
---|
| 853 | unsigned char _pad46[2]; |
---|
| 854 | unsigned char spcom; |
---|
| 855 | unsigned short _pad47[2]; |
---|
| 856 | |
---|
| 857 | /* |
---|
| 858 | * PIP Block |
---|
| 859 | */ |
---|
| 860 | unsigned short pipc; |
---|
| 861 | unsigned short _pad48; |
---|
| 862 | unsigned short ptpr; |
---|
| 863 | unsigned long pbdir; |
---|
| 864 | unsigned long pbpar; |
---|
| 865 | unsigned short _pad49; |
---|
| 866 | unsigned short pbodr; |
---|
| 867 | unsigned long pbdat; |
---|
| 868 | unsigned long _pad50[6]; |
---|
| 869 | |
---|
| 870 | /* |
---|
| 871 | * SI Block |
---|
| 872 | */ |
---|
| 873 | unsigned long simode; |
---|
| 874 | unsigned char sigmr; |
---|
| 875 | unsigned char _pad51; |
---|
| 876 | unsigned char sistr; |
---|
| 877 | unsigned char sicmr; |
---|
| 878 | unsigned long _pad52; |
---|
| 879 | unsigned long sicr; |
---|
| 880 | unsigned short _pad53; |
---|
| 881 | unsigned short sirp[2]; |
---|
| 882 | unsigned short _pad54; |
---|
| 883 | unsigned long _pad55[2]; |
---|
| 884 | unsigned char siram[256]; |
---|
| 885 | } m360_t; |
---|
| 886 | |
---|
| 887 | extern volatile m360_t m360; |
---|
| 888 | |
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| 889 | #endif /* __MC68360_h */ |
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