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source: rtems/cpukit/score/cpu/m68k/m68360.h @ 4deeca3

4.104.114.84.95

Last change on this file since 4deeca3 was 12710a56, checked in by Joel Sherrill <joel.sherrill@…>, on 02/19/99 at 23:35:42
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1	/*
2	**************************************************************************
3	**************************************************************************
4
5	MOTOROLA MC68360 QUAD INTEGRATED COMMUNICATIONS CONTROLLER (QUICC)
6
7	HARDWARE DECLARATIONS
8
9
10	Submitted By:
11
12	W. Eric Norum
13	Saskatchewan Accelerator Laboratory
14	University of Saskatchewan
15	107 North Road
16	Saskatoon, Saskatchewan, CANADA
17	S7N 5C6
18
19	eric@skatter.usask.ca
20
21	$Id$
22
23	**************************************************************************
24	**************************************************************************
25	*/
26
27	#ifndef __MC68360_h
28	#define __MC68360_h
29
30	/*
31	*************************************************************************
32	* REGISTER SUBBLOCKS *
33	*************************************************************************
34	*/
35
36	/*
37	* Memory controller registers
38	*/
39	typedef struct m360MEMCRegisters_ {
40	unsigned long br;
41	unsigned long or;
42	unsigned long _pad[2];
43	} m360MEMCRegisters_t;
44
45	/*
46	* Serial Communications Controller registers
47	*/
48	typedef struct m360SCCRegisters_ {
49	unsigned long gsmr_l;
50	unsigned long gsmr_h;
51	unsigned short psmr;
52	unsigned short _pad0;
53	unsigned short todr;
54	unsigned short dsr;
55	unsigned short scce;
56	unsigned short _pad1;
57	unsigned short sccm;
58	unsigned char _pad2;
59	unsigned char sccs;
60	unsigned long _pad3[2];
61	} m360SCCRegisters_t;
62
63	/*
64	* Serial Management Controller registers
65	*/
66	typedef struct m360SMCRegisters_ {
67	unsigned short _pad0;
68	unsigned short smcmr;
69	unsigned short _pad1;
70	unsigned char smce;
71	unsigned char _pad2;
72	unsigned short _pad3;
73	unsigned char smcm;
74	unsigned char _pad4;
75	unsigned long _pad5;
76	} m360SMCRegisters_t;
77
78
79	/*
80	*************************************************************************
81	* Miscellaneous Parameters *
82	*************************************************************************
83	*/
84	typedef struct m360MiscParms_ {
85	unsigned short rev_num;
86	unsigned short _res1;
87	unsigned long _res2;
88	unsigned long _res3;
89	} m360MiscParms_t;
90
91	/*
92	*************************************************************************
93	* RISC Timers *
94	*************************************************************************
95	*/
96	typedef struct m360TimerParms_ {
97	unsigned short tm_base;
98	unsigned short _tm_ptr;
99	unsigned short _r_tmr;
100	unsigned short _r_tmv;
101	unsigned long tm_cmd;
102	unsigned long tm_cnt;
103	} m360TimerParms_t;
104
105	/*
106	* RISC Controller Configuration Register (RCCR)
107	* All other bits in this register are either reserved or
108	* used only with a Motorola-supplied RAM microcode packge.
109	*/
110	#define M360_RCCR_TIME (1<<15) /* Enable timer */
111	#define M360_RCCR_TIMEP(x) ((x)<<8) /* Timer period */
112
113	/*
114	* Command register
115	* Set up this register before issuing a M360_CR_OP_SET_TIMER command.
116	*/
117	#define M360_TM_CMD_V (1<<31) /* Set to enable timer */
118	#define M360_TM_CMD_R (1<<30) /* Set for automatic restart */
119	#define M360_TM_CMD_TIMER(x) ((x)<<16) /* Select timer */
120	#define M360_TM_CMD_PERIOD(x) (x) /* Timer period (16 bits) */
121
122	/*
123	*************************************************************************
124	* DMA Controllers *
125	*************************************************************************
126	*/
127	typedef struct m360IDMAparms_ {
128	unsigned short ibase;
129	unsigned short ibptr;
130	unsigned long _istate;
131	unsigned long _itemp;
132	} m360IDMAparms_t;
133
134	/*
135	*************************************************************************
136	* Serial Communication Controllers *
137	*************************************************************************
138	*/
139	typedef struct m360SCCparms_ {
140	unsigned short rbase;
141	unsigned short tbase;
142	unsigned char rfcr;
143	unsigned char tfcr;
144	unsigned short mrblr;
145	unsigned long _rstate;
146	unsigned long _pad0;
147	unsigned short _rbptr;
148	unsigned short _pad1;
149	unsigned long _pad2;
150	unsigned long _tstate;
151	unsigned long _pad3;
152	unsigned short _tbptr;
153	unsigned short _pad4;
154	unsigned long _pad5;
155	unsigned long _rcrc;
156	unsigned long _tcrc;
157	union {
158	struct {
159	unsigned long _res0;
160	unsigned long _res1;
161	unsigned short max_idl;
162	unsigned short _idlc;
163	unsigned short brkcr;
164	unsigned short parec;
165	unsigned short frmec;
166	unsigned short nosec;
167	unsigned short brkec;
168	unsigned short brklen;
169	unsigned short uaddr[2];
170	unsigned short _rtemp;
171	unsigned short toseq;
172	unsigned short character[8];
173	unsigned short rccm;
174	unsigned short rccr;
175	unsigned short rlbc;
176	} uart;
177	struct {
178	unsigned long crc_p;
179	unsigned long crc_c;
180	} transparent;
181
182	} un;
183	} m360SCCparms_t;
184
185	typedef struct m360SCCENparms_ {
186	unsigned short rbase;
187	unsigned short tbase;
188	unsigned char rfcr;
189	unsigned char tfcr;
190	unsigned short mrblr;
191	unsigned long _rstate;
192	unsigned long _pad0;
193	unsigned short _rbptr;
194	unsigned short _pad1;
195	unsigned long _pad2;
196	unsigned long _tstate;
197	unsigned long _pad3;
198	unsigned short _tbptr;
199	unsigned short _pad4;
200	unsigned long _pad5;
201	unsigned long _rcrc;
202	unsigned long _tcrc;
203	union {
204	struct {
205	unsigned long _res0;
206	unsigned long _res1;
207	unsigned short max_idl;
208	unsigned short _idlc;
209	unsigned short brkcr;
210	unsigned short parec;
211	unsigned short frmec;
212	unsigned short nosec;
213	unsigned short brkec;
214	unsigned short brklen;
215	unsigned short uaddr[2];
216	unsigned short _rtemp;
217	unsigned short toseq;
218	unsigned short character[8];
219	unsigned short rccm;
220	unsigned short rccr;
221	unsigned short rlbc;
222	} uart;
223	struct {
224	unsigned long c_pres;
225	unsigned long c_mask;
226	unsigned long crcec;
227	unsigned long alec;
228	unsigned long disfc;
229	unsigned short pads;
230	unsigned short ret_lim;
231	unsigned short _ret_cnt;
232	unsigned short mflr;
233	unsigned short minflr;
234	unsigned short maxd1;
235	unsigned short maxd2;
236	unsigned short _maxd;
237	unsigned short dma_cnt;
238	unsigned short _max_b;
239	unsigned short gaddr1;
240	unsigned short gaddr2;
241	unsigned short gaddr3;
242	unsigned short gaddr4;
243	unsigned long _tbuf0data0;
244	unsigned long _tbuf0data1;
245	unsigned long _tbuf0rba0;
246	unsigned long _tbuf0crc;
247	unsigned short _tbuf0bcnt;
248	unsigned short paddr_h;
249	unsigned short paddr_m;
250	unsigned short paddr_l;
251	unsigned short p_per;
252	unsigned short _rfbd_ptr;
253	unsigned short _tfbd_ptr;
254	unsigned short _tlbd_ptr;
255	unsigned long _tbuf1data0;
256	unsigned long _tbuf1data1;
257	unsigned long _tbuf1rba0;
258	unsigned long _tbuf1crc;
259	unsigned short _tbuf1bcnt;
260	unsigned short _tx_len;
261	unsigned short iaddr1;
262	unsigned short iaddr2;
263	unsigned short iaddr3;
264	unsigned short iaddr4;
265	unsigned short _boff_cnt;
266	unsigned short taddr_l;
267	unsigned short taddr_m;
268	unsigned short taddr_h;
269	} ethernet;
270	struct {
271	unsigned long crc_p;
272	unsigned long crc_c;
273	} transparent;
274	} un;
275	} m360SCCENparms_t;
276
277	/*
278	* Receive and transmit function code register bits
279	* These apply to the function code registers of all devices, not just SCC.
280	*/
281	#define M360_RFCR_MOT (1<<4)
282	#define M360_RFCR_DMA_SPACE 0x8
283	#define M360_TFCR_MOT (1<<4)
284	#define M360_TFCR_DMA_SPACE 0x8
285
286	/*
287	*************************************************************************
288	* Serial Management Controllers *
289	*************************************************************************
290	*/
291	typedef struct m360SMCparms_ {
292	unsigned short rbase;
293	unsigned short tbase;
294	unsigned char rfcr;
295	unsigned char tfcr;
296	unsigned short mrblr;
297	unsigned long _rstate;
298	unsigned long _pad0;
299	unsigned short _rbptr;
300	unsigned short _pad1;
301	unsigned long _pad2;
302	unsigned long _tstate;
303	unsigned long _pad3;
304	unsigned short _tbptr;
305	unsigned short _pad4;
306	unsigned long _pad5;
307	union {
308	struct {
309	unsigned short max_idl;
310	unsigned short _pad0;
311	unsigned short brklen;
312	unsigned short brkec;
313	unsigned short brkcr;
314	unsigned short _r_mask;
315	} uart;
316	struct {
317	unsigned short _pad0[5];
318	} transparent;
319	} un;
320	} m360SMCparms_t;
321
322	/*
323	* Mode register
324	*/
325	#define M360_SMCMR_CLEN(x) ((x)<<11) /* Character length */
326	#define M360_SMCMR_2STOP (1<<10) /* 2 stop bits */
327	#define M360_SMCMR_PARITY (1<<9) /* Enable parity */
328	#define M360_SMCMR_EVEN (1<<8) /* Even parity */
329	#define M360_SMCMR_SM_GCI (0<<4) /* GCI Mode */
330	#define M360_SMCMR_SM_UART (2<<4) /* UART Mode */
331	#define M360_SMCMR_SM_TRANSPARENT (3<<4) /* Transparent Mode */
332	#define M360_SMCMR_DM_LOOPBACK (1<<2) /* Local loopback mode */
333	#define M360_SMCMR_DM_ECHO (2<<2) /* Echo mode */
334	#define M360_SMCMR_TEN (1<<1) /* Enable transmitter */
335	#define M360_SMCMR_REN (1<<0) /* Enable receiver */
336
337	/*
338	* Event and mask registers (SMCE, SMCM)
339	*/
340	#define M360_SMCE_BRK (1<<4)
341	#define M360_SMCE_BSY (1<<2)
342	#define M360_SMCE_TX (1<<1)
343	#define M360_SMCE_RX (1<<0)
344
345	/*
346	*************************************************************************
347	* Serial Peripheral Interface *
348	*************************************************************************
349	*/
350	typedef struct m360SPIparms_ {
351	unsigned short rbase;
352	unsigned short tbase;
353	unsigned char rfcr;
354	unsigned char tfcr;
355	unsigned short mrblr;
356	unsigned long _rstate;
357	unsigned long _pad0;
358	unsigned short _rbptr;
359	unsigned short _pad1;
360	unsigned long _pad2;
361	unsigned long _tstate;
362	unsigned long _pad3;
363	unsigned short _tbptr;
364	unsigned short _pad4;
365	unsigned long _pad5;
366	} m360SPIparms_t;
367
368	/*
369	* Mode register (SPMODE)
370	*/
371	#define M360_SPMODE_LOOP (1<<14) /* Local loopback mode */
372	#define M360_SPMODE_CI (1<<13) /* Clock invert */
373	#define M360_SPMODE_CP (1<<12) /* Clock phase */
374	#define M360_SPMODE_DIV16 (1<<11) /* Divide BRGCLK by 16 */
375	#define M360_SPMODE_REV (1<<10) /* Reverse data */
376	#define M360_SPMODE_MASTER (1<<9) /* SPI is master */
377	#define M360_SPMODE_EN (1<<8) /* Enable SPI */
378	#define M360_SPMODE_CLEN(x) ((x)<<4) /* Character length */
379	#define M360_SPMODE_PM(x) (x) /* Prescaler modulus */
380
381	/*
382	* Mode register (SPCOM)
383	*/
384	#define M360_SPCOM_STR (1<<7) /* Start transmit */
385
386	/*
387	* Event and mask registers (SPIE, SPIM)
388	*/
389	#define M360_SPIE_MME (1<<5) /* Multi-master error */
390	#define M360_SPIE_TXE (1<<4) /* Tx error */
391	#define M360_SPIE_BSY (1<<2) /* Busy condition*/
392	#define M360_SPIE_TXB (1<<1) /* Tx buffer */
393	#define M360_SPIE_RXB (1<<0) /* Rx buffer */
394
395	/*
396	*************************************************************************
397	* SDMA (SCC, SMC, SPI) Buffer Descriptors *
398	*************************************************************************
399	*/
400	typedef struct m360BufferDescriptor_ {
401	unsigned short status;
402	unsigned short length;
403	volatile void *buffer;
404	} m360BufferDescriptor_t;
405
406	/*
407	* Bits in receive buffer descriptor status word
408	*/
409	#define M360_BD_EMPTY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
410	#define M360_BD_WRAP (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */
411	#define M360_BD_INTERRUPT (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */
412	#define M360_BD_LAST (1<<11) /* Ethernet, SPI */
413	#define M360_BD_CONTROL_CHAR (1<<11) /* SCC UART */
414	#define M360_BD_FIRST_IN_FRAME (1<<10) /* Ethernet */
415	#define M360_BD_ADDRESS (1<<10) /* SCC UART */
416	#define M360_BD_CONTINUOUS (1<<9) /* SCC UART, SMC UART, SPI */
417	#define M360_BD_MISS (1<<8) /* Ethernet */
418	#define M360_BD_IDLE (1<<8) /* SCC UART, SMC UART */
419	#define M360_BD_ADDRSS_MATCH (1<<7) /* SCC UART */
420	#define M360_BD_LONG (1<<5) /* Ethernet */
421	#define M360_BD_BREAK (1<<5) /* SCC UART, SMC UART */
422	#define M360_BD_NONALIGNED (1<<4) /* Ethernet */
423	#define M360_BD_FRAMING_ERROR (1<<4) /* SCC UART, SMC UART */
424	#define M360_BD_SHORT (1<<3) /* Ethernet */
425	#define M360_BD_PARITY_ERROR (1<<3) /* SCC UART, SMC UART */
426	#define M360_BD_CRC_ERROR (1<<2) /* Ethernet */
427	#define M360_BD_OVERRUN (1<<1) /* Ethernet, SCC UART, SMC UART, SPI */
428	#define M360_BD_COLLISION (1<<0) /* Ethernet */
429	#define M360_BD_CARRIER_LOST (1<<0) /* SCC UART */
430	#define M360_BD_MASTER_ERROR (1<<0) /* SPI */
431
432	/*
433	* Bits in transmit buffer descriptor status word
434	* Many bits have the same meaning as those in receiver buffer descriptors.
435	*/
436	#define M360_BD_READY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
437	#define M360_BD_PAD (1<<14) /* Ethernet */
438	#define M360_BD_CTS_REPORT (1<<11) /* SCC UART */
439	#define M360_BD_TX_CRC (1<<10) /* Ethernet */
440	#define M360_BD_DEFER (1<<9) /* Ethernet */
441	#define M360_BD_HEARTBEAT (1<<8) /* Ethernet */
442	#define M360_BD_PREAMBLE (1<<8) /* SCC UART, SMC UART */
443	#define M360_BD_LATE_COLLISION (1<<7) /* Ethernet */
444	#define M360_BD_NO_STOP_BIT (1<<7) /* SCC UART */
445	#define M360_BD_RETRY_LIMIT (1<<6) /* Ethernet */
446	#define M360_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) /* Ethernet */
447	#define M360_BD_UNDERRUN (1<<1) /* Ethernet, SPI */
448	#define M360_BD_CARRIER_LOST (1<<0) /* Ethernet */
449	#define M360_BD_CTS_LOST (1<<0) /* SCC UART */
450
451	/*
452	*************************************************************************
453	* IDMA Buffer Descriptors *
454	*************************************************************************
455	*/
456	typedef struct m360IDMABufferDescriptor_ {
457	unsigned short status;
458	unsigned short _pad;
459	unsigned long length;
460	void *source;
461	void *destination;
462	} m360IDMABufferDescriptor_t;
463
464	/*
465	*************************************************************************
466	* RISC Communication Processor Module Command Register (CR) *
467	*************************************************************************
468	*/
469	#define M360_CR_RST (1<<15) /* Reset communication processor */
470	#define M360_CR_OP_INIT_RX_TX (0<<8) /* SCC, SMC UART, SMC GCI, SPI */
471	#define M360_CR_OP_INIT_RX (1<<8) /* SCC, SMC UART, SPI */
472	#define M360_CR_OP_INIT_TX (2<<8) /* SCC, SMC UART, SPI */
473	#define M360_CR_OP_INIT_HUNT (3<<8) /* SCC, SMC UART */
474	#define M360_CR_OP_STOP_TX (4<<8) /* SCC, SMC UART */
475	#define M360_CR_OP_GR_STOP_TX (5<<8) /* SCC */
476	#define M360_CR_OP_INIT_IDMA (5<<8) /* IDMA */
477	#define M360_CR_OP_RESTART_TX (6<<8) /* SCC, SMC UART */
478	#define M360_CR_OP_CLOSE_RX_BD (7<<8) /* SCC, SMC UART, SPI */
479	#define M360_CR_OP_SET_GRP_ADDR (8<<8) /* SCC */
480	#define M360_CR_OP_SET_TIMER (8<<8) /* Timer */
481	#define M360_CR_OP_GCI_TIMEOUT (9<<8) /* SMC GCI */
482	#define M360_CR_OP_RESERT_BCS (10<<8) /* SCC */
483	#define M360_CR_OP_GCI_ABORT (10<<8) /* SMC GCI */
484	#define M360_CR_CHAN_SCC1 (0<<4) /* Channel selection */
485	#define M360_CR_CHAN_SCC2 (4<<4)
486	#define M360_CR_CHAN_SPI (5<<4)
487	#define M360_CR_CHAN_TIMER (5<<4)
488	#define M360_CR_CHAN_SCC3 (8<<4)
489	#define M360_CR_CHAN_SMC1 (9<<4)
490	#define M360_CR_CHAN_IDMA1 (9<<4)
491	#define M360_CR_CHAN_SCC4 (12<<4)
492	#define M360_CR_CHAN_SMC2 (13<<4)
493	#define M360_CR_CHAN_IDMA2 (13<<4)
494	#define M360_CR_FLG (1<<0) /* Command flag */
495
496	/*
497	*************************************************************************
498	* System Protection Control Register (SYPCR) *
499	*************************************************************************
500	*/
501	#define M360_SYPCR_SWE (1<<7) /* Software watchdog enable */
502	#define M360_SYPCR_SWRI (1<<6) /* Software watchdog reset select */
503	#define M360_SYPCR_SWT1 (1<<5) /* Software watchdog timing bit 1 */
504	#define M360_SYPCR_SWT0 (1<<4) /* Software watchdog timing bit 0 */
505	#define M360_SYPCR_DBFE (1<<3) /* Double bus fault monitor enable */
506	#define M360_SYPCR_BME (1<<2) /* Bus monitor external enable */
507	#define M360_SYPCR_BMT1 (1<<1) /* Bus monitor timing bit 1 */
508	#define M360_SYPCR_BMT0 (1<<0) /* Bus monitor timing bit 0 */
509
510	/*
511	*************************************************************************
512	* Memory Control Registers *
513	*************************************************************************
514	*/
515	#define M360_GMR_RCNT(x) ((x)<<24) /* Refresh count */
516	#define M360_GMR_RFEN (1<<23) /* Refresh enable */
517	#define M360_GMR_RCYC(x) ((x)<<21) /* Refresh cycle length */
518	#define M360_GMR_PGS(x) ((x)<<18) /* Page size */
519	#define M360_GMR_DPS_32BIT (0<<16) /* DRAM port size */
520	#define M360_GMR_DPS_16BIT (1<<16)
521	#define M360_GMR_DPS_8BIT (2<<16)
522	#define M360_GMR_DPS_DSACK (3<<16)
523	#define M360_GMR_WBT40 (1<<15) /* Wait between 040 transfers */
524	#define M360_GMR_WBTQ (1<<14) /* Wait between 360 transfers */
525	#define M360_GMR_SYNC (1<<13) /* Synchronous external access */
526	#define M360_GMR_EMWS (1<<12) /* External master wait state */
527	#define M360_GMR_OPAR (1<<11) /* Odd parity */
528	#define M360_GMR_PBEE (1<<10) /* Parity bus error enable */
529	#define M360_GMR_TSS40 (1<<9) /* TS* sample for 040 */
530	#define M360_GMR_NCS (1<<8) /* No CPU space */
531	#define M360_GMR_DWQ (1<<7) /* Delay write for 360 */
532	#define M360_GMR_DW40 (1<<6) /* Delay write for 040 */
533	#define M360_GMR_GAMX (1<<5) /* Global address mux enable */
534
535	#define M360_MEMC_BR_FC(x) ((x)<<7) /* Function code limit */
536	#define M360_MEMC_BR_TRLXQ (1<<6) /* Relax timing requirements */
537	#define M360_MEMC_BR_BACK40 (1<<5) /* Burst acknowledge to 040 */
538	#define M360_MEMC_BR_CSNT40 (1<<4) /* CS* negate timing for 040 */
539	#define M360_MEMC_BR_CSNTQ (1<<3) /* CS* negate timing for 360 */
540	#define M360_MEMC_BR_PAREN (1<<2) /* Enable parity checking */
541	#define M360_MEMC_BR_WP (1<<1) /* Write Protect */
542	#define M360_MEMC_BR_V (1<<0) /* Base/Option register are valid */
543
544	#define M360_MEMC_OR_TCYC(x) ((x)<<28) /* Cycle length (clocks) */
545	#define M360_MEMC_OR_WAITS(x) M360_MEMC_OR_TCYC((x)+1)
546	#define M360_MEMC_OR_2KB 0x0FFFF800 /* Address range */
547	#define M360_MEMC_OR_4KB 0x0FFFF000
548	#define M360_MEMC_OR_8KB 0x0FFFE000
549	#define M360_MEMC_OR_16KB 0x0FFFC000
550	#define M360_MEMC_OR_32KB 0x0FFF8000
551	#define M360_MEMC_OR_64KB 0x0FFF0000
552	#define M360_MEMC_OR_128KB 0x0FFE0000
553	#define M360_MEMC_OR_256KB 0x0FFC0000
554	#define M360_MEMC_OR_512KB 0x0FF80000
555	#define M360_MEMC_OR_1MB 0x0FF00000
556	#define M360_MEMC_OR_2MB 0x0FE00000
557	#define M360_MEMC_OR_4MB 0x0FC00000
558	#define M360_MEMC_OR_8MB 0x0F800000
559	#define M360_MEMC_OR_16MB 0x0F000000
560	#define M360_MEMC_OR_32MB 0x0E000000
561	#define M360_MEMC_OR_64MB 0x0C000000
562	#define M360_MEMC_OR_128MB 0x08000000
563	#define M360_MEMC_OR_256MB 0x00000000
564	#define M360_MEMC_OR_FCMC(x) ((x)<<7) /* Function code mask */
565	#define M360_MEMC_OR_BCYC(x) ((x)<<5) /* Burst cycle length (clocks) */
566	#define M360_MEMC_OR_PGME (1<<3) /* Page mode enable */
567	#define M360_MEMC_OR_32BIT (0<<1) /* Port size */
568	#define M360_MEMC_OR_16BIT (1<<1)
569	#define M360_MEMC_OR_8BIT (2<<1)
570	#define M360_MEMC_OR_DSACK (3<<1)
571	#define M360_MEMC_OR_DRAM (1<<0) /* Dynamic RAM select */
572
573	/*
574	*************************************************************************
575	* SI Mode Register (SIMODE) *
576	*************************************************************************
577	*/
578	#define M360_SI_SMC2_BITS 0xFFFF0000 /* All SMC2 bits */
579	#define M360_SI_SMC2_TDM (1<<31) /* Multiplexed SMC2 */
580	#define M360_SI_SMC2_BRG1 (0<<28) /* SMC2 clock souce */
581	#define M360_SI_SMC2_BRG2 (1<<28)
582	#define M360_SI_SMC2_BRG3 (2<<28)
583	#define M360_SI_SMC2_BRG4 (3<<28)
584	#define M360_SI_SMC2_CLK5 (0<<28)
585	#define M360_SI_SMC2_CLK6 (1<<28)
586	#define M360_SI_SMC2_CLK7 (2<<28)
587	#define M360_SI_SMC2_CLK8 (3<<28)
588	#define M360_SI_SMC1_BITS 0x0000FFFF /* All SMC1 bits */
589	#define M360_SI_SMC1_TDM (1<<15) /* Multiplexed SMC1 */
590	#define M360_SI_SMC1_BRG1 (0<<12) /* SMC1 clock souce */
591	#define M360_SI_SMC1_BRG2 (1<<12)
592	#define M360_SI_SMC1_BRG3 (2<<12)
593	#define M360_SI_SMC1_BRG4 (3<<12)
594	#define M360_SI_SMC1_CLK1 (0<<12)
595	#define M360_SI_SMC1_CLK2 (1<<12)
596	#define M360_SI_SMC1_CLK3 (2<<12)
597	#define M360_SI_SMC1_CLK4 (3<<12)
598
599	/*
600	*************************************************************************
601	* SDMA Configuration Register (SDMA) *
602	*************************************************************************
603	*/
604	#define M360_SDMA_FREEZE (2<<13) /* Freeze on next bus cycle */
605	#define M360_SDMA_SISM_7 (7<<8) /* Normal interrupt service mask */
606	#define M360_SDMA_SAID_4 (4<<4) /* Normal arbitration ID */
607	#define M360_SDMA_INTE (1<<1) /* SBER interrupt enable */
608	#define M360_SDMA_INTB (1<<0) /* SBKP interrupt enable */
609
610	/*
611	*************************************************************************
612	* Baud (sic) Rate Generators *
613	*************************************************************************
614	*/
615	#define M360_BRG_RST (1<<17) /* Reset generator */
616	#define M360_BRG_EN (1<<16) /* Enable generator */
617	#define M360_BRG_EXTC_BRGCLK (0<<14) /* Source is BRGCLK */
618	#define M360_BRG_EXTC_CLK2 (1<<14) /* Source is CLK2 pin */
619	#define M360_BRG_EXTC_CLK6 (2<<14) /* Source is CLK6 pin */
620	#define M360_BRG_ATB (1<<13) /* Autobaud */
621	#define M360_BRG_115200 (13<<1) /* Assume 25 MHz clock */
622	#define M360_BRG_57600 (26<<1)
623	#define M360_BRG_38400 (40<<1)
624	#define M360_BRG_19200 (80<<1)
625	#define M360_BRG_9600 (162<<1)
626	#define M360_BRG_4800 (324<<1)
627	#define M360_BRG_2400 (650<<1)
628	#define M360_BRG_1200 (1301<<1)
629	#define M360_BRG_600 (2603<<1)
630	#define M360_BRG_300 ((324<<1) \| 1)
631	#define M360_BRG_150 ((650<<1) \| 1)
632	#define M360_BRG_75 ((1301<<1) \| 1)
633
634	/*
635	*************************************************************************
636	* MC68360 DUAL-PORT RAM AND REGISTERS *
637	*************************************************************************
638	*/
639	typedef struct m360_ {
640	/*
641	* Dual-port RAM
642	*/
643	unsigned char dpram0[0x400]; /* Microcode program */
644	unsigned char dpram1[0x200];
645	unsigned char dpram2[0x100]; /* Microcode scratch */
646	unsigned char dpram3[0x100]; /* Not on REV A or B masks */
647	unsigned char _rsv0[0xC00-0x800];
648	m360SCCENparms_t scc1p;
649	unsigned char _rsv1[0xCB0-0xC00-sizeof(m360SCCENparms_t)];
650	m360MiscParms_t miscp;
651	unsigned char _rsv2[0xD00-0xCB0-sizeof(m360MiscParms_t)];
652	m360SCCparms_t scc2p;
653	unsigned char _rsv3[0xD80-0xD00-sizeof(m360SCCparms_t)];
654	m360SPIparms_t spip;
655	unsigned char _rsv4[0xDB0-0xD80-sizeof(m360SPIparms_t)];
656	m360TimerParms_t tmp;
657	unsigned char _rsv5[0xE00-0xDB0-sizeof(m360TimerParms_t)];
658	m360SCCparms_t scc3p;
659	unsigned char _rsv6[0xE70-0xE00-sizeof(m360SCCparms_t)];
660	m360IDMAparms_t idma1p;
661	unsigned char _rsv7[0xE80-0xE70-sizeof(m360IDMAparms_t)];
662	m360SMCparms_t smc1p;
663	unsigned char _rsv8[0xF00-0xE80-sizeof(m360SMCparms_t)];
664	m360SCCparms_t scc4p;
665	unsigned char _rsv9[0xF70-0xF00-sizeof(m360SCCparms_t)];
666	m360IDMAparms_t idma2p;
667	unsigned char _rsv10[0xF80-0xF70-sizeof(m360IDMAparms_t)];
668	m360SMCparms_t smc2p;
669	unsigned char _rsv11[0x1000-0xF80-sizeof(m360SMCparms_t)];
670
671	/*
672	* SIM Block
673	*/
674	unsigned long mcr;
675	unsigned long _pad00;
676	unsigned char avr;
677	unsigned char rsr;
678	unsigned short _pad01;
679	unsigned char clkocr;
680	unsigned char _pad02;
681	unsigned short _pad03;
682	unsigned short pllcr;
683	unsigned short _pad04;
684	unsigned short cdvcr;
685	unsigned short pepar;
686	unsigned long _pad05[2];
687	unsigned short _pad06;
688	unsigned char sypcr;
689	unsigned char swiv;
690	unsigned short _pad07;
691	unsigned short picr;
692	unsigned short _pad08;
693	unsigned short pitr;
694	unsigned short _pad09;
695	unsigned char _pad10;
696	unsigned char swsr;
697	unsigned long bkar;
698	unsigned long bcar;
699	unsigned long _pad11[2];
700
701	/*
702	* MEMC Block
703	*/
704	unsigned long gmr;
705	unsigned short mstat;
706	unsigned short _pad12;
707	unsigned long _pad13[2];
708	m360MEMCRegisters_t memc[8];
709	unsigned char _pad14[0xF0-0xD0];
710	unsigned char _pad15[0x100-0xF0];
711	unsigned char _pad16[0x500-0x100];
712
713	/*
714	* IDMA1 Block
715	*/
716	unsigned short iccr;
717	unsigned short _pad17;
718	unsigned short cmr1;
719	unsigned short _pad18;
720	unsigned long sapr1;
721	unsigned long dapr1;
722	unsigned long bcr1;
723	unsigned char fcr1;
724	unsigned char _pad19;
725	unsigned char cmar1;
726	unsigned char _pad20;
727	unsigned char csr1;
728	unsigned char _pad21;
729	unsigned short _pad22;
730
731	/*
732	* SDMA Block
733	*/
734	unsigned char sdsr;
735	unsigned char _pad23;
736	unsigned short sdcr;
737	unsigned long sdar;
738
739	/*
740	* IDMA2 Block
741	*/
742	unsigned short _pad24;
743	unsigned short cmr2;
744	unsigned long sapr2;
745	unsigned long dapr2;
746	unsigned long bcr2;
747	unsigned char fcr2;
748	unsigned char _pad26;
749	unsigned char cmar2;
750	unsigned char _pad27;
751	unsigned char csr2;
752	unsigned char _pad28;
753	unsigned short _pad29;
754	unsigned long _pad30;
755
756	/*
757	* CPIC Block
758	*/
759	unsigned long cicr;
760	unsigned long cipr;
761	unsigned long cimr;
762	unsigned long cisr;
763
764	/*
765	* Parallel I/O Block
766	*/
767	unsigned short padir;
768	unsigned short papar;
769	unsigned short paodr;
770	unsigned short padat;
771	unsigned long _pad31[2];
772	unsigned short pcdir;
773	unsigned short pcpar;
774	unsigned short pcso;
775	unsigned short pcdat;
776	unsigned short pcint;
777	unsigned short _pad32;
778	unsigned long _pad33[5];
779
780	/*
781	* TIMER Block
782	*/
783	unsigned short tgcr;
784	unsigned short _pad34;
785	unsigned long _pad35[3];
786	unsigned short tmr1;
787	unsigned short tmr2;
788	unsigned short trr1;
789	unsigned short trr2;
790	unsigned short tcr1;
791	unsigned short tcr2;
792	unsigned short tcn1;
793	unsigned short tcn2;
794	unsigned short tmr3;
795	unsigned short tmr4;
796	unsigned short trr3;
797	unsigned short trr4;
798	unsigned short tcr3;
799	unsigned short tcr4;
800	unsigned short tcn3;
801	unsigned short tcn4;
802	unsigned short ter1;
803	unsigned short ter2;
804	unsigned short ter3;
805	unsigned short ter4;
806	unsigned long _pad36[2];
807
808	/*
809	* CP Block
810	*/
811	unsigned short cr;
812	unsigned short _pad37;
813	unsigned short rccr;
814	unsigned short _pad38;
815	unsigned long _pad39[3];
816	unsigned short _pad40;
817	unsigned short rter;
818	unsigned short _pad41;
819	unsigned short rtmr;
820	unsigned long _pad42[5];
821
822	/*
823	* BRG Block
824	*/
825	unsigned long brgc1;
826	unsigned long brgc2;
827	unsigned long brgc3;
828	unsigned long brgc4;
829
830	/*
831	* SCC Block
832	*/
833	m360SCCRegisters_t scc1;
834	m360SCCRegisters_t scc2;
835	m360SCCRegisters_t scc3;
836	m360SCCRegisters_t scc4;
837
838	/*
839	* SMC Block
840	*/
841	m360SMCRegisters_t smc1;
842	m360SMCRegisters_t smc2;
843
844	/*
845	* SPI Block
846	*/
847	unsigned short spmode;
848	unsigned short _pad43[2];
849	unsigned char spie;
850	unsigned char _pad44;
851	unsigned short _pad45;
852	unsigned char spim;
853	unsigned char _pad46[2];
854	unsigned char spcom;
855	unsigned short _pad47[2];
856
857	/*
858	* PIP Block
859	*/
860	unsigned short pipc;
861	unsigned short _pad48;
862	unsigned short ptpr;
863	unsigned long pbdir;
864	unsigned long pbpar;
865	unsigned short _pad49;
866	unsigned short pbodr;
867	unsigned long pbdat;
868	unsigned long _pad50[6];
869
870	/*
871	* SI Block
872	*/
873	unsigned long simode;
874	unsigned char sigmr;
875	unsigned char _pad51;
876	unsigned char sistr;
877	unsigned char sicmr;
878	unsigned long _pad52;
879	unsigned long sicr;
880	unsigned short _pad53;
881	unsigned short sirp[2];
882	unsigned short _pad54;
883	unsigned long _pad55[2];
884	unsigned char siram[256];
885	} m360_t;
886
887	extern volatile m360_t m360;
888
889	#endif /* __MC68360_h */

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