[9a1ccb3] | 1 | /* |
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| 2 | ************************************************************************** |
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| 3 | ************************************************************************** |
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| 4 | ** ** |
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| 5 | ** MOTOROLA MC68360 QUAD INTEGRATED COMMUNICATIONS CONTROLLER (QUICC) ** |
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| 6 | ** ** |
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| 7 | ** HARDWARE DECLARATIONS ** |
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| 8 | ** ** |
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| 9 | ************************************************************************** |
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| 10 | ************************************************************************** |
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| 11 | */ |
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| 12 | |
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| 13 | #ifndef __MC68360_h |
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| 14 | #define __MC68360_h |
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| 15 | |
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| 16 | /* |
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| 17 | * $Revision$ $Date$ $Author$ |
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| 18 | * |
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| 19 | * This program is free software; you can redistribute it and/or modify |
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| 20 | * it under the terms of the GNU General Public License as published by |
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| 21 | * the Free Software Foundation; either version 2 of the License, or |
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| 22 | * (at your option) any later version. |
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| 23 | * |
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| 24 | * This program is distributed in the hope that it will be useful, |
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| 25 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 26 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 27 | * GNU General Public License for more details. |
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| 28 | * |
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| 29 | * You should have received a copy of the GNU General Public License |
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| 30 | * along with this program; if not, write to the Free Software |
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| 31 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
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| 32 | * |
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| 33 | * W. Eric Norum |
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| 34 | * Saskatchewan Accelerator Laboratory |
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| 35 | * University of Saskatchewan |
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| 36 | * 107 North Road |
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| 37 | * Saskatoon, Saskatchewan, CANADA |
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| 38 | * S7N 5C6 |
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| 39 | * |
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| 40 | * eric@skatter.usask.ca |
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| 41 | */ |
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| 42 | |
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| 43 | /* |
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| 44 | ************************************************************************* |
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| 45 | * REGISTER SUBBLOCKS * |
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| 46 | ************************************************************************* |
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| 47 | */ |
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| 48 | |
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| 49 | /* |
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| 50 | * Memory controller registers |
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| 51 | */ |
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| 52 | typedef struct m360MEMCRegisters_ { |
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| 53 | rtems_unsigned32 br; |
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| 54 | rtems_unsigned32 or; |
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| 55 | rtems_unsigned32 _pad[2]; |
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| 56 | } m360MEMCRegisters_t; |
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| 57 | |
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| 58 | /* |
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| 59 | * Serial Communications Controller registers |
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| 60 | */ |
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| 61 | typedef struct m360SCCRegisters_ { |
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| 62 | rtems_unsigned32 gsmr_l; |
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| 63 | rtems_unsigned32 gsmr_h; |
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| 64 | rtems_unsigned16 psmr; |
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| 65 | rtems_unsigned16 _pad0; |
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| 66 | rtems_unsigned16 todr; |
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| 67 | rtems_unsigned16 dsr; |
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| 68 | rtems_unsigned16 scce; |
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| 69 | rtems_unsigned16 _pad1; |
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| 70 | rtems_unsigned16 sccm; |
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| 71 | rtems_unsigned8 _pad2; |
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| 72 | rtems_unsigned8 sccs; |
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| 73 | rtems_unsigned32 _pad3[2]; |
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| 74 | } m360SCCRegisters_t; |
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| 75 | |
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| 76 | /* |
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| 77 | * Serial Management Controller registers |
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| 78 | */ |
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| 79 | typedef struct m360SMCRegisters_ { |
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| 80 | rtems_unsigned16 _pad0; |
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| 81 | rtems_unsigned16 smcmr; |
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| 82 | rtems_unsigned16 _pad1; |
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| 83 | rtems_unsigned8 smce; |
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| 84 | rtems_unsigned8 _pad2; |
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| 85 | rtems_unsigned16 _pad3; |
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| 86 | rtems_unsigned8 smcm; |
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| 87 | rtems_unsigned8 _pad4; |
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| 88 | rtems_unsigned32 _pad5; |
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| 89 | } m360SMCRegisters_t; |
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| 90 | |
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| 91 | |
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| 92 | /* |
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| 93 | ************************************************************************* |
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| 94 | * Miscellaneous Parameters * |
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| 95 | ************************************************************************* |
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| 96 | */ |
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| 97 | typedef struct m360MiscParms_ { |
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| 98 | rtems_unsigned16 rev_num; |
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| 99 | rtems_unsigned16 _res1; |
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| 100 | rtems_unsigned32 _res2; |
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| 101 | rtems_unsigned32 _res3; |
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| 102 | } m360MiscParms_t; |
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| 103 | |
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| 104 | /* |
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| 105 | ************************************************************************* |
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| 106 | * RISC Timers * |
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| 107 | ************************************************************************* |
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| 108 | */ |
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| 109 | typedef struct m360TimerParms_ { |
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| 110 | rtems_unsigned16 tm_base; |
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| 111 | rtems_unsigned16 _tm_ptr; |
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| 112 | rtems_unsigned16 _r_tmr; |
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| 113 | rtems_unsigned16 _r_tmv; |
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| 114 | rtems_unsigned32 tm_cmd; |
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| 115 | rtems_unsigned32 tm_cnt; |
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| 116 | } m360TimerParms_t; |
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| 117 | |
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| 118 | /* |
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| 119 | * RISC Controller Configuration Register (RCCR) |
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| 120 | * All other bits in this register are either reserved or |
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| 121 | * used only with a Motorola-supplied RAM microcode packge. |
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| 122 | */ |
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| 123 | #define M360_RCCR_TIME (1<<15) /* Enable timer */ |
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| 124 | #define M360_RCCR_TIMEP(x) ((x)<<8) /* Timer period */ |
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| 125 | |
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| 126 | /* |
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| 127 | * Command register |
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| 128 | * Set up this register before issuing a M360_CR_OP_SET_TIMER command. |
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| 129 | */ |
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| 130 | #define M360_TM_CMD_V (1<<31) /* Set to enable timer */ |
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| 131 | #define M360_TM_CMD_R (1<<30) /* Set for automatic restart */ |
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| 132 | #define M360_TM_CMD_TIMER(x) ((x)<<16) /* Select timer */ |
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| 133 | #define M360_TM_CMD_PERIOD(x) (x) /* Timer period (16 bits) */ |
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| 134 | |
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| 135 | /* |
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| 136 | ************************************************************************* |
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| 137 | * DMA Controllers * |
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| 138 | ************************************************************************* |
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| 139 | */ |
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| 140 | typedef struct m360IDMAparms_ { |
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| 141 | rtems_unsigned16 ibase; |
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| 142 | rtems_unsigned16 ibptr; |
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| 143 | rtems_unsigned32 _istate; |
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| 144 | rtems_unsigned32 _itemp; |
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| 145 | } m360IDMAparms_t; |
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| 146 | |
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| 147 | /* |
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| 148 | ************************************************************************* |
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| 149 | * Serial Communication Controllers * |
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| 150 | ************************************************************************* |
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| 151 | */ |
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| 152 | typedef struct m360SCCparms_ { |
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| 153 | rtems_unsigned16 rbase; |
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| 154 | rtems_unsigned16 tbase; |
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| 155 | rtems_unsigned8 rfcr; |
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| 156 | rtems_unsigned8 tfcr; |
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| 157 | rtems_unsigned16 mrblr; |
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| 158 | rtems_unsigned32 _rstate; |
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| 159 | rtems_unsigned32 _pad0; |
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| 160 | rtems_unsigned16 _rbptr; |
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| 161 | rtems_unsigned16 _pad1; |
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| 162 | rtems_unsigned32 _pad2; |
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| 163 | rtems_unsigned32 _tstate; |
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| 164 | rtems_unsigned32 _pad3; |
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| 165 | rtems_unsigned16 _tbptr; |
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| 166 | rtems_unsigned16 _pad4; |
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| 167 | rtems_unsigned32 _pad5; |
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| 168 | rtems_unsigned32 _rcrc; |
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| 169 | rtems_unsigned32 _tcrc; |
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| 170 | union { |
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| 171 | struct { |
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| 172 | rtems_unsigned32 _res0; |
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| 173 | rtems_unsigned32 _res1; |
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| 174 | rtems_unsigned16 max_idl; |
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| 175 | rtems_unsigned16 _idlc; |
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| 176 | rtems_unsigned16 brkcr; |
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| 177 | rtems_unsigned16 parec; |
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| 178 | rtems_unsigned16 frmec; |
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| 179 | rtems_unsigned16 nosec; |
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| 180 | rtems_unsigned16 brkec; |
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| 181 | rtems_unsigned16 brklen; |
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| 182 | rtems_unsigned16 uaddr[2]; |
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| 183 | rtems_unsigned16 _rtemp; |
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| 184 | rtems_unsigned16 toseq; |
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| 185 | rtems_unsigned16 character[8]; |
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| 186 | rtems_unsigned16 rccm; |
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| 187 | rtems_unsigned16 rccr; |
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| 188 | rtems_unsigned16 rlbc; |
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| 189 | } uart; |
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| 190 | } un; |
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| 191 | } m360SCCparms_t; |
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| 192 | |
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| 193 | typedef struct m360SCCENparms_ { |
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| 194 | rtems_unsigned16 rbase; |
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| 195 | rtems_unsigned16 tbase; |
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| 196 | rtems_unsigned8 rfcr; |
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| 197 | rtems_unsigned8 tfcr; |
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| 198 | rtems_unsigned16 mrblr; |
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| 199 | rtems_unsigned32 _rstate; |
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| 200 | rtems_unsigned32 _pad0; |
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| 201 | rtems_unsigned16 _rbptr; |
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| 202 | rtems_unsigned16 _pad1; |
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| 203 | rtems_unsigned32 _pad2; |
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| 204 | rtems_unsigned32 _tstate; |
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| 205 | rtems_unsigned32 _pad3; |
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| 206 | rtems_unsigned16 _tbptr; |
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| 207 | rtems_unsigned16 _pad4; |
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| 208 | rtems_unsigned32 _pad5; |
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| 209 | rtems_unsigned32 _rcrc; |
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| 210 | rtems_unsigned32 _tcrc; |
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| 211 | union { |
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| 212 | struct { |
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| 213 | rtems_unsigned32 _res0; |
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| 214 | rtems_unsigned32 _res1; |
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| 215 | rtems_unsigned16 max_idl; |
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| 216 | rtems_unsigned16 _idlc; |
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| 217 | rtems_unsigned16 brkcr; |
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| 218 | rtems_unsigned16 parec; |
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| 219 | rtems_unsigned16 frmec; |
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| 220 | rtems_unsigned16 nosec; |
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| 221 | rtems_unsigned16 brkec; |
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| 222 | rtems_unsigned16 brklen; |
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| 223 | rtems_unsigned16 uaddr[2]; |
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| 224 | rtems_unsigned16 _rtemp; |
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| 225 | rtems_unsigned16 toseq; |
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| 226 | rtems_unsigned16 character[8]; |
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| 227 | rtems_unsigned16 rccm; |
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| 228 | rtems_unsigned16 rccr; |
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| 229 | rtems_unsigned16 rlbc; |
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| 230 | } uart; |
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| 231 | struct { |
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| 232 | rtems_unsigned32 c_pres; |
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| 233 | rtems_unsigned32 c_mask; |
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| 234 | rtems_unsigned32 crcec; |
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| 235 | rtems_unsigned32 alec; |
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| 236 | rtems_unsigned32 disfc; |
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| 237 | rtems_unsigned16 pads; |
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| 238 | rtems_unsigned16 ret_lim; |
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| 239 | rtems_unsigned16 _ret_cnt; |
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| 240 | rtems_unsigned16 mflr; |
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| 241 | rtems_unsigned16 minflr; |
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| 242 | rtems_unsigned16 maxd1; |
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| 243 | rtems_unsigned16 maxd2; |
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| 244 | rtems_unsigned16 _maxd; |
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| 245 | rtems_unsigned16 dma_cnt; |
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| 246 | rtems_unsigned16 _max_b; |
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| 247 | rtems_unsigned16 gaddr1; |
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| 248 | rtems_unsigned16 gaddr2; |
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| 249 | rtems_unsigned16 gaddr3; |
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| 250 | rtems_unsigned16 gaddr4; |
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| 251 | rtems_unsigned32 _tbuf0data0; |
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| 252 | rtems_unsigned32 _tbuf0data1; |
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| 253 | rtems_unsigned32 _tbuf0rba0; |
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| 254 | rtems_unsigned32 _tbuf0crc; |
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| 255 | rtems_unsigned16 _tbuf0bcnt; |
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| 256 | rtems_unsigned16 paddr_h; |
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| 257 | rtems_unsigned16 paddr_m; |
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| 258 | rtems_unsigned16 paddr_l; |
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| 259 | rtems_unsigned16 p_per; |
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| 260 | rtems_unsigned16 _rfbd_ptr; |
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| 261 | rtems_unsigned16 _tfbd_ptr; |
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| 262 | rtems_unsigned16 _tlbd_ptr; |
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| 263 | rtems_unsigned32 _tbuf1data0; |
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| 264 | rtems_unsigned32 _tbuf1data1; |
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| 265 | rtems_unsigned32 _tbuf1rba0; |
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| 266 | rtems_unsigned32 _tbuf1crc; |
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| 267 | rtems_unsigned16 _tbuf1bcnt; |
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| 268 | rtems_unsigned16 _tx_len; |
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| 269 | rtems_unsigned16 iaddr1; |
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| 270 | rtems_unsigned16 iaddr2; |
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| 271 | rtems_unsigned16 iaddr3; |
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| 272 | rtems_unsigned16 iaddr4; |
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| 273 | rtems_unsigned16 _boff_cnt; |
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| 274 | rtems_unsigned16 taddr_l; |
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| 275 | rtems_unsigned16 taddr_m; |
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| 276 | rtems_unsigned16 taddr_h; |
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| 277 | } ethernet; |
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| 278 | } un; |
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| 279 | } m360SCCENparms_t; |
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| 280 | |
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| 281 | /* |
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| 282 | * Receive and transmit function code register bits |
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| 283 | * These apply to the function code registers of all devices, not just SCC. |
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| 284 | */ |
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| 285 | #define M360_RFCR_MOT (1<<4) |
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| 286 | #define M360_RFCR_DMA_SPACE 0x8 |
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| 287 | #define M360_TFCR_MOT (1<<4) |
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| 288 | #define M360_TFCR_DMA_SPACE 0x8 |
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| 289 | |
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| 290 | /* |
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| 291 | ************************************************************************* |
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| 292 | * Serial Management Controllers * |
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| 293 | ************************************************************************* |
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| 294 | */ |
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| 295 | typedef struct m360SMCparms_ { |
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| 296 | rtems_unsigned16 rbase; |
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| 297 | rtems_unsigned16 tbase; |
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| 298 | rtems_unsigned8 rfcr; |
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| 299 | rtems_unsigned8 tfcr; |
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| 300 | rtems_unsigned16 mrblr; |
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| 301 | rtems_unsigned32 _rstate; |
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| 302 | rtems_unsigned32 _pad0; |
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| 303 | rtems_unsigned16 _rbptr; |
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| 304 | rtems_unsigned16 _pad1; |
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| 305 | rtems_unsigned32 _pad2; |
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| 306 | rtems_unsigned32 _tstate; |
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| 307 | rtems_unsigned32 _pad3; |
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| 308 | rtems_unsigned16 _tbptr; |
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| 309 | rtems_unsigned16 _pad4; |
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| 310 | rtems_unsigned32 _pad5; |
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| 311 | union { |
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| 312 | struct { |
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| 313 | rtems_unsigned16 max_idl; |
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| 314 | rtems_unsigned16 _pad0; |
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| 315 | rtems_unsigned16 brklen; |
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| 316 | rtems_unsigned16 brkec; |
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| 317 | rtems_unsigned16 brkcr; |
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| 318 | rtems_unsigned16 _r_mask; |
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| 319 | } uart; |
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| 320 | struct { |
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| 321 | rtems_unsigned16 _pad0[5]; |
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| 322 | } transparent; |
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| 323 | } un; |
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| 324 | } m360SMCparms_t; |
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| 325 | |
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| 326 | /* |
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| 327 | * Mode register |
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| 328 | */ |
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| 329 | #define M360_SMCMR_CLEN(x) ((x)<<11) /* Character length */ |
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| 330 | #define M360_SMCMR_2STOP (1<<10) /* 2 stop bits */ |
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| 331 | #define M360_SMCMR_PARITY (1<<9) /* Enable parity */ |
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| 332 | #define M360_SMCMR_EVEN (1<<8) /* Even parity */ |
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| 333 | #define M360_SMCMR_SM_GCI (0<<4) /* GCI Mode */ |
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| 334 | #define M360_SMCMR_SM_UART (2<<4) /* UART Mode */ |
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| 335 | #define M360_SMCMR_SM_TRANSPARENT (3<<4) /* Transparent Mode */ |
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| 336 | #define M360_SMCMR_DM_LOOPBACK (1<<2) /* Local loopback mode */ |
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| 337 | #define M360_SMCMR_DM_ECHO (2<<2) /* Echo mode */ |
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| 338 | #define M360_SMCMR_TEN (1<<1) /* Enable transmitter */ |
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| 339 | #define M360_SMCMR_REN (1<<0) /* Enable receiver */ |
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| 340 | |
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| 341 | /* |
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| 342 | * Event and mask registers (SMCE, SMCM) |
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| 343 | */ |
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| 344 | #define M360_SMCE_BRK (1<<4) |
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| 345 | #define M360_SMCE_BSY (1<<2) |
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| 346 | #define M360_SMCE_TX (1<<1) |
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| 347 | #define M360_SMCE_RX (1<<0) |
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| 348 | |
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| 349 | /* |
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| 350 | ************************************************************************* |
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| 351 | * Serial Peripheral Interface * |
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| 352 | ************************************************************************* |
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| 353 | */ |
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| 354 | typedef struct m360SPIparms_ { |
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| 355 | rtems_unsigned16 rbase; |
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| 356 | rtems_unsigned16 tbase; |
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| 357 | rtems_unsigned8 rfcr; |
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| 358 | rtems_unsigned8 tfcr; |
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| 359 | rtems_unsigned16 mrblr; |
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| 360 | rtems_unsigned32 _rstate; |
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| 361 | rtems_unsigned32 _pad0; |
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| 362 | rtems_unsigned16 _rbptr; |
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| 363 | rtems_unsigned16 _pad1; |
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| 364 | rtems_unsigned32 _pad2; |
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| 365 | rtems_unsigned32 _tstate; |
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| 366 | rtems_unsigned32 _pad3; |
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| 367 | rtems_unsigned16 _tbptr; |
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| 368 | rtems_unsigned16 _pad4; |
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| 369 | rtems_unsigned32 _pad5; |
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| 370 | } m360SPIparms_t; |
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| 371 | |
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| 372 | /* |
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| 373 | * Mode register (SPMODE) |
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| 374 | */ |
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| 375 | #define M360_SPMODE_LOOP (1<<14) /* Local loopback mode */ |
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| 376 | #define M360_SPMODE_CI (1<<13) /* Clock invert */ |
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| 377 | #define M360_SPMODE_CP (1<<12) /* Clock phase */ |
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| 378 | #define M360_SPMODE_DIV16 (1<<11) /* Divide BRGCLK by 16 */ |
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| 379 | #define M360_SPMODE_REV (1<<10) /* Reverse data */ |
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| 380 | #define M360_SPMODE_MASTER (1<<9) /* SPI is master */ |
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| 381 | #define M360_SPMODE_EN (1<<8) /* Enable SPI */ |
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| 382 | #define M360_SPMODE_CLEN(x) ((x)<<4) /* Character length */ |
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| 383 | #define M360_SPMODE_PM(x) (x) /* Prescaler modulus */ |
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| 384 | |
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| 385 | /* |
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| 386 | * Mode register (SPCOM) |
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| 387 | */ |
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| 388 | #define M360_SPCOM_STR (1<<7) /* Start transmit */ |
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| 389 | |
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| 390 | /* |
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| 391 | * Event and mask registers (SPIE, SPIM) |
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| 392 | */ |
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| 393 | #define M360_SPIE_MME (1<<5) /* Multi-master error */ |
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| 394 | #define M360_SPIE_TXE (1<<4) /* Tx error */ |
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| 395 | #define M360_SPIE_BSY (1<<2) /* Busy condition*/ |
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| 396 | #define M360_SPIE_TXB (1<<1) /* Tx buffer */ |
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| 397 | #define M360_SPIE_RXB (1<<0) /* Rx buffer */ |
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| 398 | |
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| 399 | /* |
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| 400 | ************************************************************************* |
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| 401 | * SDMA (SCC, SMC, SPI) Buffer Descriptors * |
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| 402 | ************************************************************************* |
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| 403 | */ |
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| 404 | typedef struct m360BufferDescriptor_ { |
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| 405 | rtems_unsigned16 status; |
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| 406 | rtems_unsigned16 length; |
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| 407 | volatile void *buffer; |
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| 408 | } m360BufferDescriptor_t; |
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| 409 | |
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| 410 | /* |
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| 411 | * Bits in receive buffer descriptor status word |
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| 412 | */ |
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| 413 | #define M360_BD_EMPTY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ |
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| 414 | #define M360_BD_WRAP (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */ |
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| 415 | #define M360_BD_INTERRUPT (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */ |
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| 416 | #define M360_BD_LAST (1<<11) /* Ethernet, SPI */ |
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| 417 | #define M360_BD_CONTROL_CHAR (1<<11) /* SCC UART */ |
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| 418 | #define M360_BD_FIRST_IN_FRAME (1<<10) /* Ethernet */ |
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| 419 | #define M360_BD_ADDRESS (1<<10) /* SCC UART */ |
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| 420 | #define M360_BD_CONTINUOUS (1<<9) /* SCC UART, SMC UART, SPI */ |
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| 421 | #define M360_BD_MISS (1<<8) /* Ethernet */ |
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| 422 | #define M360_BD_IDLE (1<<8) /* SCC UART, SMC UART */ |
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| 423 | #define M360_BD_ADDRSS_MATCH (1<<7) /* SCC UART */ |
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| 424 | #define M360_BD_LONG (1<<5) /* Ethernet */ |
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| 425 | #define M360_BD_BREAK (1<<5) /* SCC UART, SMC UART */ |
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| 426 | #define M360_BD_NONALIGNED (1<<4) /* Ethernet */ |
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| 427 | #define M360_BD_FRAMING_ERROR (1<<4) /* SCC UART, SMC UART */ |
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| 428 | #define M360_BD_SHORT (1<<3) /* Ethernet */ |
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| 429 | #define M360_BD_PARITY_ERROR (1<<3) /* SCC UART, SMC UART */ |
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| 430 | #define M360_BD_CRC_ERROR (1<<2) /* Ethernet */ |
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| 431 | #define M360_BD_OVERRUN (1<<1) /* Ethernet, SCC UART, SMC UART, SPI */ |
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| 432 | #define M360_BD_COLLISION (1<<0) /* Ethernet */ |
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| 433 | #define M360_BD_CARRIER_LOST (1<<0) /* SCC UART */ |
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| 434 | #define M360_BD_MASTER_ERROR (1<<0) /* SPI */ |
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| 435 | |
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| 436 | /* |
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| 437 | * Bits in transmit buffer descriptor status word |
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| 438 | * Many bits have the same meaning as those in receiver buffer descriptors. |
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| 439 | */ |
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| 440 | #define M360_BD_READY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ |
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| 441 | #define M360_BD_PAD (1<<14) /* Ethernet */ |
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| 442 | #define M360_BD_CTS_REPORT (1<<11) /* SCC UART */ |
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| 443 | #define M360_BD_TX_CRC (1<<10) /* Ethernet */ |
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| 444 | #define M360_BD_DEFER (1<<9) /* Ethernet */ |
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| 445 | #define M360_BD_HEARTBEAT (1<<8) /* Ethernet */ |
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| 446 | #define M360_BD_PREAMBLE (1<<8) /* SCC UART, SMC UART */ |
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| 447 | #define M360_BD_LATE_COLLISION (1<<7) /* Ethernet */ |
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| 448 | #define M360_BD_NO_STOP_BIT (1<<7) /* SCC UART */ |
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| 449 | #define M360_BD_RETRY_LIMIT (1<<6) /* Ethernet */ |
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| 450 | #define M360_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) /* Ethernet */ |
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| 451 | #define M360_BD_UNDERRUN (1<<1) /* Ethernet, SPI */ |
---|
| 452 | #define M360_BD_CARRIER_LOST (1<<0) /* Ethernet */ |
---|
| 453 | #define M360_BD_CTS_LOST (1<<0) /* SCC UART */ |
---|
| 454 | |
---|
| 455 | /* |
---|
| 456 | ************************************************************************* |
---|
| 457 | * IDMA Buffer Descriptors * |
---|
| 458 | ************************************************************************* |
---|
| 459 | */ |
---|
| 460 | typedef struct m360IDMABufferDescriptor_ { |
---|
| 461 | rtems_unsigned16 status; |
---|
| 462 | rtems_unsigned16 _pad; |
---|
| 463 | rtems_unsigned32 length; |
---|
| 464 | void *source; |
---|
| 465 | void *destination; |
---|
| 466 | } m360IDMABufferDescriptor_t; |
---|
| 467 | |
---|
| 468 | /* |
---|
| 469 | ************************************************************************* |
---|
| 470 | * RISC Communication Processor Module Command Register (CR) * |
---|
| 471 | ************************************************************************* |
---|
| 472 | */ |
---|
| 473 | #define M360_CR_RST (1<<15) /* Reset communication processor */ |
---|
| 474 | #define M360_CR_OP_INIT_RX_TX (0<<8) /* SCC, SMC UART, SMC GCI, SPI */ |
---|
| 475 | #define M360_CR_OP_INIT_RX (1<<8) /* SCC, SMC UART, SPI */ |
---|
| 476 | #define M360_CR_OP_INIT_TX (2<<8) /* SCC, SMC UART, SPI */ |
---|
| 477 | #define M360_CR_OP_INIT_HUNT (3<<8) /* SCC, SMC UART */ |
---|
| 478 | #define M360_CR_OP_STOP_TX (4<<8) /* SCC, SMC UART */ |
---|
| 479 | #define M360_CR_OP_GR_STOP_TX (5<<8) /* SCC */ |
---|
| 480 | #define M360_CR_OP_INIT_IDMA (5<<8) /* IDMA */ |
---|
| 481 | #define M360_CR_OP_RESTART_TX (6<<8) /* SCC, SMC UART */ |
---|
| 482 | #define M360_CR_OP_CLOSE_RX_BD (7<<8) /* SCC, SMC UART, SPI */ |
---|
| 483 | #define M360_CR_OP_SET_GRP_ADDR (8<<8) /* SCC */ |
---|
| 484 | #define M360_CR_OP_SET_TIMER (8<<8) /* Timer */ |
---|
| 485 | #define M360_CR_OP_GCI_TIMEOUT (9<<8) /* SMC GCI */ |
---|
| 486 | #define M360_CR_OP_RESERT_BCS (10<<8) /* SCC */ |
---|
| 487 | #define M360_CR_OP_GCI_ABORT (10<<8) /* SMC GCI */ |
---|
| 488 | #define M360_CR_CHAN_SCC1 (0<<4) /* Channel selection */ |
---|
| 489 | #define M360_CR_CHAN_SCC2 (4<<4) |
---|
| 490 | #define M360_CR_CHAN_SPI (5<<4) |
---|
| 491 | #define M360_CR_CHAN_TIMER (5<<4) |
---|
| 492 | #define M360_CR_CHAN_SCC3 (8<<4) |
---|
| 493 | #define M360_CR_CHAN_SMC1 (9<<4) |
---|
| 494 | #define M360_CR_CHAN_IDMA1 (9<<4) |
---|
| 495 | #define M360_CR_CHAN_SCC4 (12<<4) |
---|
| 496 | #define M360_CR_CHAN_SMC2 (13<<4) |
---|
| 497 | #define M360_CR_CHAN_IDMA2 (13<<4) |
---|
| 498 | #define M360_CR_FLG (1<<0) /* Command flag */ |
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| 499 | |
---|
| 500 | /* |
---|
| 501 | ************************************************************************* |
---|
| 502 | * System Protection Control Register (SYPCR) * |
---|
| 503 | ************************************************************************* |
---|
| 504 | */ |
---|
| 505 | #define M360_SYPCR_SWE (1<<7) /* Software watchdog enable */ |
---|
| 506 | #define M360_SYPCR_SWRI (1<<6) /* Software watchdog reset select */ |
---|
| 507 | #define M360_SYPCR_SWT1 (1<<5) /* Software watchdog timing bit 1 */ |
---|
| 508 | #define M360_SYPCR_SWT0 (1<<4) /* Software watchdog timing bit 0 */ |
---|
| 509 | #define M360_SYPCR_DBFE (1<<3) /* Double bus fault monitor enable */ |
---|
| 510 | #define M360_SYPCR_BME (1<<2) /* Bus monitor external enable */ |
---|
| 511 | #define M360_SYPCR_BMT1 (1<<1) /* Bus monitor timing bit 1 */ |
---|
| 512 | #define M360_SYPCR_BMT0 (1<<0) /* Bus monitor timing bit 0 */ |
---|
| 513 | |
---|
| 514 | /* |
---|
| 515 | ************************************************************************* |
---|
| 516 | * Memory Control Registers * |
---|
| 517 | ************************************************************************* |
---|
| 518 | */ |
---|
| 519 | #define M360_GMR_RCNT(x) ((x)<<24) /* Refresh count */ |
---|
| 520 | #define M360_GMR_RFEN (1<<23) /* Refresh enable */ |
---|
| 521 | #define M360_GMR_RCYC(x) ((x)<<21) /* Refresh cycle length */ |
---|
| 522 | #define M360_GMR_PGS(x) ((x)<<18) /* Page size */ |
---|
| 523 | #define M360_GMR_DPS_32BIT (0<<16) /* DRAM port size */ |
---|
| 524 | #define M360_GMR_DPS_16BIT (1<<16) |
---|
| 525 | #define M360_GMR_DPS_8BIT (2<<16) |
---|
| 526 | #define M360_GMR_DPS_DSACK (3<<16) |
---|
| 527 | #define M360_GMR_WBT40 (1<<15) /* Wait between 040 transfers */ |
---|
| 528 | #define M360_GMR_WBTQ (1<<14) /* Wait between 360 transfers */ |
---|
| 529 | #define M360_GMR_SYNC (1<<13) /* Synchronous external access */ |
---|
| 530 | #define M360_GMR_EMWS (1<<12) /* External master wait state */ |
---|
| 531 | #define M360_GMR_OPAR (1<<11) /* Odd parity */ |
---|
| 532 | #define M360_GMR_PBEE (1<<10) /* Parity bus error enable */ |
---|
| 533 | #define M360_GMR_TSS40 (1<<9) /* TS* sample for 040 */ |
---|
| 534 | #define M360_GMR_NCS (1<<8) /* No CPU space */ |
---|
| 535 | #define M360_GMR_DWQ (1<<7) /* Delay write for 360 */ |
---|
| 536 | #define M360_GMR_DW40 (1<<6) /* Delay write for 040 */ |
---|
| 537 | #define M360_GMR_GAMX (1<<5) /* Global address mux enable */ |
---|
| 538 | |
---|
| 539 | #define M360_MEMC_BR_FC(x) ((x)<<7) /* Function code limit */ |
---|
| 540 | #define M360_MEMC_BR_TRLXQ (1<<6) /* Relax timing requirements */ |
---|
| 541 | #define M360_MEMC_BR_BACK40 (1<<5) /* Burst acknowledge to 040 */ |
---|
| 542 | #define M360_MEMC_BR_CSNT40 (1<<4) /* CS* negate timing for 040 */ |
---|
| 543 | #define M360_MEMC_BR_CSNTQ (1<<3) /* CS* negate timing for 360 */ |
---|
| 544 | #define M360_MEMC_BR_PAREN (1<<2) /* Enable parity checking */ |
---|
| 545 | #define M360_MEMC_BR_WP (1<<1) /* Write Protect */ |
---|
| 546 | #define M360_MEMC_BR_V (1<<0) /* Base/Option register are valid */ |
---|
| 547 | |
---|
| 548 | #define M360_MEMC_OR_TCYC(x) ((x)<<28) /* Cycle length (clocks) */ |
---|
| 549 | #define M360_MEMC_OR_WAITS(x) M360_MEMC_OR_TCYC((x)+1) |
---|
| 550 | #define M360_MEMC_OR_2KB 0x0FFFF800 /* Address range */ |
---|
| 551 | #define M360_MEMC_OR_4KB 0x0FFFF000 |
---|
| 552 | #define M360_MEMC_OR_8KB 0x0FFFE000 |
---|
| 553 | #define M360_MEMC_OR_16KB 0x0FFFC000 |
---|
| 554 | #define M360_MEMC_OR_32KB 0x0FFF8000 |
---|
| 555 | #define M360_MEMC_OR_64KB 0x0FFF0000 |
---|
| 556 | #define M360_MEMC_OR_128KB 0x0FFE0000 |
---|
| 557 | #define M360_MEMC_OR_256KB 0x0FFC0000 |
---|
| 558 | #define M360_MEMC_OR_512KB 0x0FF80000 |
---|
| 559 | #define M360_MEMC_OR_1MB 0x0FF00000 |
---|
| 560 | #define M360_MEMC_OR_2MB 0x0FE00000 |
---|
| 561 | #define M360_MEMC_OR_4MB 0x0FC00000 |
---|
| 562 | #define M360_MEMC_OR_8MB 0x0F800000 |
---|
| 563 | #define M360_MEMC_OR_16MB 0x0F000000 |
---|
| 564 | #define M360_MEMC_OR_32MB 0x0E000000 |
---|
| 565 | #define M360_MEMC_OR_64MB 0x0C000000 |
---|
| 566 | #define M360_MEMC_OR_128MB 0x08000000 |
---|
| 567 | #define M360_MEMC_OR_256MB 0x00000000 |
---|
| 568 | #define M360_MEMC_OR_FCMC(x) ((x)<<7) /* Function code mask */ |
---|
| 569 | #define M360_MEMC_OR_BCYC(x) ((x)<<5) /* Burst cycle length (clocks) */ |
---|
| 570 | #define M360_MEMC_OR_PGME (1<<3) /* Page mode enable */ |
---|
| 571 | #define M360_MEMC_OR_32BIT (0<<1) /* Port size */ |
---|
| 572 | #define M360_MEMC_OR_16BIT (1<<1) |
---|
| 573 | #define M360_MEMC_OR_8BIT (2<<1) |
---|
| 574 | #define M360_MEMC_OR_DSACK (3<<1) |
---|
| 575 | #define M360_MEMC_OR_DRAM (1<<0) /* Dynamic RAM select */ |
---|
| 576 | |
---|
| 577 | /* |
---|
| 578 | ************************************************************************* |
---|
| 579 | * SI Mode Register (SIMODE) * |
---|
| 580 | ************************************************************************* |
---|
| 581 | */ |
---|
| 582 | #define M360_SI_SMC2_BITS 0xFFFF0000 /* All SMC2 bits */ |
---|
| 583 | #define M360_SI_SMC2_TDM (1<<31) /* Multiplexed SMC2 */ |
---|
| 584 | #define M360_SI_SMC2_BRG1 (0<<28) /* SMC2 clock souce */ |
---|
| 585 | #define M360_SI_SMC2_BRG2 (1<<28) |
---|
| 586 | #define M360_SI_SMC2_BRG3 (2<<28) |
---|
| 587 | #define M360_SI_SMC2_BRG4 (3<<28) |
---|
| 588 | #define M360_SI_SMC2_CLK5 (0<<28) |
---|
| 589 | #define M360_SI_SMC2_CLK6 (1<<28) |
---|
| 590 | #define M360_SI_SMC2_CLK7 (2<<28) |
---|
| 591 | #define M360_SI_SMC2_CLK8 (3<<28) |
---|
| 592 | #define M360_SI_SMC1_BITS 0x0000FFFF /* All SMC1 bits */ |
---|
| 593 | #define M360_SI_SMC1_TDM (1<<15) /* Multiplexed SMC1 */ |
---|
| 594 | #define M360_SI_SMC1_BRG1 (0<<12) /* SMC1 clock souce */ |
---|
| 595 | #define M360_SI_SMC1_BRG2 (1<<12) |
---|
| 596 | #define M360_SI_SMC1_BRG3 (2<<12) |
---|
| 597 | #define M360_SI_SMC1_BRG4 (3<<12) |
---|
| 598 | #define M360_SI_SMC1_CLK1 (0<<12) |
---|
| 599 | #define M360_SI_SMC1_CLK2 (1<<12) |
---|
| 600 | #define M360_SI_SMC1_CLK3 (2<<12) |
---|
| 601 | #define M360_SI_SMC1_CLK4 (3<<12) |
---|
| 602 | |
---|
| 603 | /* |
---|
| 604 | ************************************************************************* |
---|
| 605 | * SDMA Configuration Register (SDMA) * |
---|
| 606 | ************************************************************************* |
---|
| 607 | */ |
---|
| 608 | #define M360_SDMA_FREEZE (2<<13) /* Freeze on next bus cycle */ |
---|
| 609 | #define M360_SDMA_SISM_7 (7<<8) /* Normal interrupt service mask */ |
---|
| 610 | #define M360_SDMA_SAID_4 (4<<4) /* Normal arbitration ID */ |
---|
| 611 | #define M360_SDMA_INTE (1<<1) /* SBER interrupt enable */ |
---|
| 612 | #define M360_SDMA_INTB (1<<0) /* SBKP interrupt enable */ |
---|
| 613 | |
---|
| 614 | /* |
---|
| 615 | ************************************************************************* |
---|
| 616 | * Baud (sic) Rate Generators * |
---|
| 617 | ************************************************************************* |
---|
| 618 | */ |
---|
| 619 | #define M360_BRG_RST (1<<17) /* Reset generator */ |
---|
| 620 | #define M360_BRG_EN (1<<16) /* Enable generator */ |
---|
| 621 | #define M360_BRG_EXTC_BRGCLK (0<<14) /* Source is BRGCLK */ |
---|
| 622 | #define M360_BRG_EXTC_CLK2 (1<<14) /* Source is CLK2 pin */ |
---|
| 623 | #define M360_BRG_EXTC_CLK6 (2<<14) /* Source is CLK6 pin */ |
---|
| 624 | #define M360_BRG_ATB (1<<13) /* Autobaud */ |
---|
| 625 | #define M360_BRG_115200 (13<<1) /* Assume 25 MHz clock */ |
---|
| 626 | #define M360_BRG_57600 (26<<1) |
---|
| 627 | #define M360_BRG_38400 (40<<1) |
---|
| 628 | #define M360_BRG_19200 (80<<1) |
---|
| 629 | #define M360_BRG_9600 (162<<1) |
---|
| 630 | #define M360_BRG_4800 (324<<1) |
---|
| 631 | #define M360_BRG_2400 (650<<1) |
---|
| 632 | #define M360_BRG_1200 (1301<<1) |
---|
| 633 | #define M360_BRG_600 (2603<<1) |
---|
| 634 | #define M360_BRG_300 ((324<<1) | 1) |
---|
| 635 | #define M360_BRG_150 ((650<<1) | 1) |
---|
| 636 | #define M360_BRG_75 ((1301<<1) | 1) |
---|
| 637 | |
---|
| 638 | /* |
---|
| 639 | ************************************************************************* |
---|
| 640 | * MC68360 DUAL-PORT RAM AND REGISTERS * |
---|
| 641 | ************************************************************************* |
---|
| 642 | */ |
---|
| 643 | typedef struct m360_ { |
---|
| 644 | /* |
---|
| 645 | * Dual-port RAM |
---|
| 646 | */ |
---|
| 647 | rtems_unsigned8 dpram0[0x400]; /* Microcode program */ |
---|
| 648 | rtems_unsigned8 dpram1[0x200]; |
---|
| 649 | rtems_unsigned8 dpram2[0x100]; /* Microcode scratch */ |
---|
| 650 | rtems_unsigned8 dpram3[0x100]; /* Not on REV A or B masks */ |
---|
| 651 | rtems_unsigned8 _rsv0[0xC00-0x800]; |
---|
| 652 | m360SCCENparms_t scc1p; |
---|
| 653 | rtems_unsigned8 _rsv1[0xCB0-0xC00-sizeof(m360SCCENparms_t)]; |
---|
| 654 | m360MiscParms_t miscp; |
---|
| 655 | rtems_unsigned8 _rsv2[0xD00-0xCB0-sizeof(m360MiscParms_t)]; |
---|
| 656 | m360SCCparms_t scc2p; |
---|
| 657 | rtems_unsigned8 _rsv3[0xD80-0xD00-sizeof(m360SCCparms_t)]; |
---|
| 658 | m360SPIparms_t spip; |
---|
| 659 | rtems_unsigned8 _rsv4[0xDB0-0xD80-sizeof(m360SPIparms_t)]; |
---|
| 660 | m360TimerParms_t tmp; |
---|
| 661 | rtems_unsigned8 _rsv5[0xE00-0xDB0-sizeof(m360TimerParms_t)]; |
---|
| 662 | m360SCCparms_t scc3p; |
---|
| 663 | rtems_unsigned8 _rsv6[0xE70-0xE00-sizeof(m360SCCparms_t)]; |
---|
| 664 | m360IDMAparms_t idma1p; |
---|
| 665 | rtems_unsigned8 _rsv7[0xE80-0xE70-sizeof(m360IDMAparms_t)]; |
---|
| 666 | m360SMCparms_t smc1p; |
---|
| 667 | rtems_unsigned8 _rsv8[0xF00-0xE80-sizeof(m360SMCparms_t)]; |
---|
| 668 | m360SCCparms_t scc4p; |
---|
| 669 | rtems_unsigned8 _rsv9[0xF70-0xF00-sizeof(m360SCCparms_t)]; |
---|
| 670 | m360IDMAparms_t idma2p; |
---|
| 671 | rtems_unsigned8 _rsv10[0xF80-0xF70-sizeof(m360IDMAparms_t)]; |
---|
| 672 | m360SMCparms_t smc2p; |
---|
| 673 | rtems_unsigned8 _rsv11[0x1000-0xF80-sizeof(m360SMCparms_t)]; |
---|
| 674 | |
---|
| 675 | /* |
---|
| 676 | * SIM Block |
---|
| 677 | */ |
---|
| 678 | rtems_unsigned32 mcr; |
---|
| 679 | rtems_unsigned32 _pad00; |
---|
| 680 | rtems_unsigned8 avr; |
---|
| 681 | rtems_unsigned8 rsr; |
---|
| 682 | rtems_unsigned16 _pad01; |
---|
| 683 | rtems_unsigned8 clkocr; |
---|
| 684 | rtems_unsigned8 _pad02; |
---|
| 685 | rtems_unsigned16 _pad03; |
---|
| 686 | rtems_unsigned16 pllcr; |
---|
| 687 | rtems_unsigned16 _pad04; |
---|
| 688 | rtems_unsigned16 cdvcr; |
---|
| 689 | rtems_unsigned16 pepar; |
---|
| 690 | rtems_unsigned32 _pad05[2]; |
---|
| 691 | rtems_unsigned16 _pad06; |
---|
| 692 | rtems_unsigned8 sypcr; |
---|
| 693 | rtems_unsigned8 swiv; |
---|
| 694 | rtems_unsigned16 _pad07; |
---|
| 695 | rtems_unsigned16 picr; |
---|
| 696 | rtems_unsigned16 _pad08; |
---|
| 697 | rtems_unsigned16 pitr; |
---|
| 698 | rtems_unsigned16 _pad09; |
---|
| 699 | rtems_unsigned8 _pad10; |
---|
| 700 | rtems_unsigned8 swsr; |
---|
| 701 | rtems_unsigned32 bkar; |
---|
| 702 | rtems_unsigned32 bcar; |
---|
| 703 | rtems_unsigned32 _pad11[2]; |
---|
| 704 | |
---|
| 705 | /* |
---|
| 706 | * MEMC Block |
---|
| 707 | */ |
---|
| 708 | rtems_unsigned32 gmr; |
---|
| 709 | rtems_unsigned16 mstat; |
---|
| 710 | rtems_unsigned16 _pad12; |
---|
| 711 | rtems_unsigned32 _pad13[2]; |
---|
| 712 | m360MEMCRegisters_t memc[8]; |
---|
| 713 | rtems_unsigned8 _pad14[0xF0-0xD0]; |
---|
| 714 | rtems_unsigned8 _pad15[0x100-0xF0]; |
---|
| 715 | rtems_unsigned8 _pad16[0x500-0x100]; |
---|
| 716 | |
---|
| 717 | /* |
---|
| 718 | * IDMA1 Block |
---|
| 719 | */ |
---|
| 720 | rtems_unsigned16 iccr; |
---|
| 721 | rtems_unsigned16 _pad17; |
---|
| 722 | rtems_unsigned16 cmr1; |
---|
| 723 | rtems_unsigned16 _pad18; |
---|
| 724 | rtems_unsigned32 sapr1; |
---|
| 725 | rtems_unsigned32 dapr1; |
---|
| 726 | rtems_unsigned32 bcr1; |
---|
| 727 | rtems_unsigned8 fcr1; |
---|
| 728 | rtems_unsigned8 _pad19; |
---|
| 729 | rtems_unsigned8 cmar1; |
---|
| 730 | rtems_unsigned8 _pad20; |
---|
| 731 | rtems_unsigned8 csr1; |
---|
| 732 | rtems_unsigned8 _pad21; |
---|
| 733 | rtems_unsigned16 _pad22; |
---|
| 734 | |
---|
| 735 | /* |
---|
| 736 | * SDMA Block |
---|
| 737 | */ |
---|
| 738 | rtems_unsigned8 sdsr; |
---|
| 739 | rtems_unsigned8 _pad23; |
---|
| 740 | rtems_unsigned16 sdcr; |
---|
| 741 | rtems_unsigned32 sdar; |
---|
| 742 | |
---|
| 743 | /* |
---|
| 744 | * IDMA2 Block |
---|
| 745 | */ |
---|
| 746 | rtems_unsigned16 _pad24; |
---|
| 747 | rtems_unsigned16 cmr2; |
---|
| 748 | rtems_unsigned32 sapr2; |
---|
| 749 | rtems_unsigned32 dapr2; |
---|
| 750 | rtems_unsigned32 bcr2; |
---|
| 751 | rtems_unsigned8 fcr2; |
---|
| 752 | rtems_unsigned8 _pad26; |
---|
| 753 | rtems_unsigned8 cmar2; |
---|
| 754 | rtems_unsigned8 _pad27; |
---|
| 755 | rtems_unsigned8 csr2; |
---|
| 756 | rtems_unsigned8 _pad28; |
---|
| 757 | rtems_unsigned16 _pad29; |
---|
| 758 | rtems_unsigned32 _pad30; |
---|
| 759 | |
---|
| 760 | /* |
---|
| 761 | * CPIC Block |
---|
| 762 | */ |
---|
| 763 | rtems_unsigned32 cicr; |
---|
| 764 | rtems_unsigned32 cipr; |
---|
| 765 | rtems_unsigned32 cimr; |
---|
| 766 | rtems_unsigned32 cisr; |
---|
| 767 | |
---|
| 768 | /* |
---|
| 769 | * Parallel I/O Block |
---|
| 770 | */ |
---|
| 771 | rtems_unsigned16 padir; |
---|
| 772 | rtems_unsigned16 papar; |
---|
| 773 | rtems_unsigned16 paodr; |
---|
| 774 | rtems_unsigned16 padat; |
---|
| 775 | rtems_unsigned32 _pad31[2]; |
---|
| 776 | rtems_unsigned16 pcdir; |
---|
| 777 | rtems_unsigned16 pcpar; |
---|
| 778 | rtems_unsigned16 pcso; |
---|
| 779 | rtems_unsigned16 pcdat; |
---|
| 780 | rtems_unsigned16 pcint; |
---|
| 781 | rtems_unsigned16 _pad32; |
---|
| 782 | rtems_unsigned32 _pad33[5]; |
---|
| 783 | |
---|
| 784 | /* |
---|
| 785 | * TIMER Block |
---|
| 786 | */ |
---|
| 787 | rtems_unsigned16 tgcr; |
---|
| 788 | rtems_unsigned16 _pad34; |
---|
| 789 | rtems_unsigned32 _pad35[3]; |
---|
| 790 | rtems_unsigned16 tmr1; |
---|
| 791 | rtems_unsigned16 tmr2; |
---|
| 792 | rtems_unsigned16 trr1; |
---|
| 793 | rtems_unsigned16 trr2; |
---|
| 794 | rtems_unsigned16 tcr1; |
---|
| 795 | rtems_unsigned16 tcr2; |
---|
| 796 | rtems_unsigned16 tcn1; |
---|
| 797 | rtems_unsigned16 tcn2; |
---|
| 798 | rtems_unsigned16 tmr3; |
---|
| 799 | rtems_unsigned16 tmr4; |
---|
| 800 | rtems_unsigned16 trr3; |
---|
| 801 | rtems_unsigned16 trr4; |
---|
| 802 | rtems_unsigned16 tcr3; |
---|
| 803 | rtems_unsigned16 tcr4; |
---|
| 804 | rtems_unsigned16 tcn3; |
---|
| 805 | rtems_unsigned16 tcn4; |
---|
| 806 | rtems_unsigned16 ter1; |
---|
| 807 | rtems_unsigned16 ter2; |
---|
| 808 | rtems_unsigned16 ter3; |
---|
| 809 | rtems_unsigned16 ter4; |
---|
| 810 | rtems_unsigned32 _pad36[2]; |
---|
| 811 | |
---|
| 812 | /* |
---|
| 813 | * CP Block |
---|
| 814 | */ |
---|
| 815 | rtems_unsigned16 cr; |
---|
| 816 | rtems_unsigned16 _pad37; |
---|
| 817 | rtems_unsigned16 rccr; |
---|
| 818 | rtems_unsigned16 _pad38; |
---|
| 819 | rtems_unsigned32 _pad39[3]; |
---|
| 820 | rtems_unsigned16 _pad40; |
---|
| 821 | rtems_unsigned16 rter; |
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| 822 | rtems_unsigned16 _pad41; |
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| 823 | rtems_unsigned16 rtmr; |
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| 824 | rtems_unsigned32 _pad42[5]; |
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| 825 | |
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| 826 | /* |
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| 827 | * BRG Block |
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| 828 | */ |
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| 829 | rtems_unsigned32 brgc1; |
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| 830 | rtems_unsigned32 brgc2; |
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| 831 | rtems_unsigned32 brgc3; |
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| 832 | rtems_unsigned32 brgc4; |
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| 833 | |
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| 834 | /* |
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| 835 | * SCC Block |
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| 836 | */ |
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| 837 | m360SCCRegisters_t scc1; |
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| 838 | m360SCCRegisters_t scc2; |
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| 839 | m360SCCRegisters_t scc3; |
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| 840 | m360SCCRegisters_t scc4; |
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| 841 | |
---|
| 842 | /* |
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| 843 | * SMC Block |
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| 844 | */ |
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| 845 | m360SMCRegisters_t smc1; |
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| 846 | m360SMCRegisters_t smc2; |
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| 847 | |
---|
| 848 | /* |
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| 849 | * SPI Block |
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| 850 | */ |
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| 851 | rtems_unsigned16 spmode; |
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| 852 | rtems_unsigned16 _pad43[2]; |
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| 853 | rtems_unsigned8 spie; |
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| 854 | rtems_unsigned8 _pad44; |
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| 855 | rtems_unsigned16 _pad45; |
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| 856 | rtems_unsigned8 spim; |
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| 857 | rtems_unsigned8 _pad46[2]; |
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| 858 | rtems_unsigned8 spcom; |
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| 859 | rtems_unsigned16 _pad47[2]; |
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| 860 | |
---|
| 861 | /* |
---|
| 862 | * PIP Block |
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| 863 | */ |
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| 864 | rtems_unsigned16 pipc; |
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| 865 | rtems_unsigned16 _pad48; |
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| 866 | rtems_unsigned16 ptpr; |
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| 867 | rtems_unsigned32 pbdir; |
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| 868 | rtems_unsigned32 pbpar; |
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| 869 | rtems_unsigned16 _pad49; |
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| 870 | rtems_unsigned16 pbodr; |
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| 871 | rtems_unsigned32 pbdat; |
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| 872 | rtems_unsigned32 _pad50[6]; |
---|
| 873 | |
---|
| 874 | /* |
---|
| 875 | * SI Block |
---|
| 876 | */ |
---|
| 877 | rtems_unsigned32 simode; |
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| 878 | rtems_unsigned8 sigmr; |
---|
| 879 | rtems_unsigned8 _pad51; |
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| 880 | rtems_unsigned8 sistr; |
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| 881 | rtems_unsigned8 sicmr; |
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| 882 | rtems_unsigned32 _pad52; |
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| 883 | rtems_unsigned32 sicr; |
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| 884 | rtems_unsigned16 _pad53; |
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| 885 | rtems_unsigned16 sirp[2]; |
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| 886 | rtems_unsigned16 _pad54; |
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| 887 | rtems_unsigned32 _pad55[2]; |
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| 888 | rtems_unsigned8 siram[256]; |
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| 889 | } m360_t; |
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| 890 | |
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| 891 | extern volatile m360_t m360; |
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| 892 | |
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| 893 | #endif /* __MC68360_h */ |
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