[12710a56] | 1 | /* |
---|
| 2 | *------------------------------------------------------------------ |
---|
| 3 | * |
---|
| 4 | * m68302.h - Definitions for Motorola MC68302 processor. |
---|
| 5 | * |
---|
| 6 | * Section references in this file refer to revision 2 of Motorola's |
---|
| 7 | * "MC68302 Integrated Multiprotocol Processor User's Manual". |
---|
| 8 | * (Motorola document MC68302UM/AD REV 2.) |
---|
| 9 | * |
---|
| 10 | * Based on Don Meyer's cpu68302.h that was posted in comp.sys.m68k |
---|
| 11 | * on 17 February, 1993. |
---|
| 12 | * |
---|
| 13 | * Copyright 1995 David W. Glessner. |
---|
| 14 | * |
---|
| 15 | * Redistribution and use in source and binary forms are permitted |
---|
| 16 | * provided that the following conditions are met: |
---|
| 17 | * 1. Redistribution of source code and documentation must retain |
---|
| 18 | * the above copyright notice, this list of conditions and the |
---|
| 19 | * following disclaimer. |
---|
| 20 | * 2. The name of the author may not be used to endorse or promote |
---|
| 21 | * products derived from this software without specific prior |
---|
| 22 | * written permission. |
---|
| 23 | * |
---|
| 24 | * This software is provided "AS IS" without warranty of any kind, |
---|
| 25 | * either expressed or implied, including, but not limited to, the |
---|
| 26 | * implied warranties of merchantability, title and fitness for a |
---|
| 27 | * particular purpose. |
---|
| 28 | * |
---|
| 29 | * |
---|
| 30 | * $Id$ |
---|
| 31 | * |
---|
| 32 | *------------------------------------------------------------------ |
---|
| 33 | */ |
---|
| 34 | |
---|
| 35 | #ifndef __MOTOROLA_MC68302_DEFINITIONS_h |
---|
| 36 | #define __MOTOROLA_MC68302_DEFINITIONS_h |
---|
| 37 | |
---|
| 38 | /* |
---|
| 39 | * BAR - Base Address Register |
---|
| 40 | * Section 2.7 |
---|
| 41 | */ |
---|
[d86bae8] | 42 | #define M302_BAR (*((volatile uint16_t *) 0xf2)) |
---|
[12710a56] | 43 | |
---|
| 44 | /* |
---|
| 45 | * SCR - System Control Register |
---|
| 46 | * Section 3.8.1 |
---|
| 47 | */ |
---|
[d86bae8] | 48 | #define M302_SCR (*((volatile uint32_t *) 0xf4)) |
---|
[12710a56] | 49 | /* |
---|
| 50 | * SCR bits |
---|
| 51 | */ |
---|
| 52 | #define RBIT_SCR_IPA 0x08000000 |
---|
| 53 | #define RBIT_SCR_HWT 0x04000000 |
---|
| 54 | #define RBIT_SCR_WPV 0x02000000 |
---|
| 55 | #define RBIT_SCR_ADC 0x01000000 |
---|
| 56 | |
---|
| 57 | #define RBIT_SCR_ERRE 0x00400000 |
---|
| 58 | #define RBIT_SCR_VGE 0x00200000 |
---|
| 59 | #define RBIT_SCR_WPVE 0x00100000 |
---|
| 60 | #define RBIT_SCR_RMCST 0x00080000 |
---|
| 61 | #define RBIT_SCR_EMWS 0x00040000 |
---|
| 62 | #define RBIT_SCR_ADCE 0x00020000 |
---|
| 63 | #define RBIT_SCR_BCLM 0x00010000 |
---|
| 64 | |
---|
| 65 | #define RBIT_SCR_FRZW 0x00008000 |
---|
| 66 | #define RBIT_SCR_FRZ2 0x00004000 |
---|
| 67 | #define RBIT_SCR_FRZ1 0x00002000 |
---|
| 68 | #define RBIT_SCR_SAM 0x00001000 |
---|
| 69 | #define RBIT_SCR_HWDEN 0x00000800 |
---|
| 70 | #define RBIT_SCR_HWDCN2 0x00000400 |
---|
| 71 | #define RBIT_SCR_HWDCN1 0x00000200 /* 512 clocks */ |
---|
| 72 | #define RBIT_SCR_HWDCN0 0x00000100 /* 128 clocks */ |
---|
| 73 | |
---|
| 74 | #define RBIT_SCR_LPREC 0x00000080 |
---|
| 75 | #define RBIT_SCR_LPP16 0x00000040 |
---|
| 76 | #define RBIT_SCR_LPEN 0x00000020 |
---|
| 77 | #define RBIT_SCR_LPCLKDIV 0x0000001f |
---|
| 78 | |
---|
| 79 | |
---|
| 80 | /* |
---|
| 81 | * 68000 interrupt and trap vector numbers |
---|
| 82 | */ |
---|
| 83 | #define M68K_IVEC_BUS_ERROR 2 |
---|
| 84 | #define M68K_IVEC_ADDRESS_ERROR 3 |
---|
| 85 | #define M68K_IVEC_ILLEGAL_OPCODE 4 |
---|
| 86 | #define M68K_IVEC_ZERO_DIVIDE 5 |
---|
| 87 | #define M68K_IVEC_CHK 6 |
---|
| 88 | #define M68K_IVEC_TRAPV 7 |
---|
| 89 | #define M68K_IVEC_PRIVILEGE 8 |
---|
| 90 | #define M68K_IVEC_TRACE 9 |
---|
| 91 | #define M68K_IVEC_LINE_A 10 |
---|
| 92 | #define M68K_IVEC_LINE_F 11 |
---|
| 93 | /* Unassigned, Reserved 12-14 */ |
---|
| 94 | #define M68K_IVEC_UNINITIALIZED_INT 15 |
---|
| 95 | /* Unassigned, Reserved 16-23 */ |
---|
| 96 | #define M68K_IVEC_SPURIOUS_INT 24 |
---|
| 97 | |
---|
| 98 | #define M68K_IVEC_LEVEL1_AUTOVECTOR 25 |
---|
| 99 | #define M68K_IVEC_LEVEL2_AUTOVECTOR 26 |
---|
| 100 | #define M68K_IVEC_LEVEL3_AUTOVECTOR 27 |
---|
| 101 | #define M68K_IVEC_LEVEL4_AUTOVECTOR 28 |
---|
| 102 | #define M68K_IVEC_LEVEL5_AUTOVECTOR 29 |
---|
| 103 | #define M68K_IVEC_LEVEL6_AUTOVECTOR 30 |
---|
| 104 | #define M68K_IVEC_LEVEL7_AUTOVECTOR 31 |
---|
| 105 | |
---|
| 106 | #define M68K_IVEC_TRAP0 32 |
---|
| 107 | #define M68K_IVEC_TRAP1 33 |
---|
| 108 | #define M68K_IVEC_TRAP2 34 |
---|
| 109 | #define M68K_IVEC_TRAP3 35 |
---|
| 110 | #define M68K_IVEC_TRAP4 36 |
---|
| 111 | #define M68K_IVEC_TRAP5 37 |
---|
| 112 | #define M68K_IVEC_TRAP6 38 |
---|
| 113 | #define M68K_IVEC_TRAP7 39 |
---|
| 114 | #define M68K_IVEC_TRAP8 40 |
---|
| 115 | #define M68K_IVEC_TRAP9 41 |
---|
| 116 | #define M68K_IVEC_TRAP10 42 |
---|
| 117 | #define M68K_IVEC_TRAP11 43 |
---|
| 118 | #define M68K_IVEC_TRAP12 44 |
---|
| 119 | #define M68K_IVEC_TRAP13 45 |
---|
| 120 | #define M68K_IVEC_TRAP14 46 |
---|
| 121 | #define M68K_IVEC_TRAP15 47 |
---|
| 122 | /* |
---|
| 123 | * Unassigned, Reserved 48-59 |
---|
| 124 | * |
---|
| 125 | * Note: Vectors 60-63 are used by the MC68302 (e.g. BAR, SCR). |
---|
| 126 | */ |
---|
| 127 | |
---|
| 128 | /* |
---|
| 129 | * MC68302 Interrupt Vectors |
---|
| 130 | * Section 3.2 |
---|
| 131 | */ |
---|
| 132 | enum m68302_ivec_e { |
---|
| 133 | M302_IVEC_ERR =0, |
---|
| 134 | M302_IVEC_PB8 =1, /* General-Purpose Interrupt 0 */ |
---|
| 135 | M302_IVEC_SMC2 =2, |
---|
| 136 | M302_IVEC_SMC1 =3, |
---|
| 137 | M302_IVEC_TIMER3 =4, |
---|
| 138 | M302_IVEC_SCP =5, |
---|
| 139 | M302_IVEC_TIMER2 =6, |
---|
| 140 | M302_IVEC_PB9 =7, /* General-Purpose Interrupt 1 */ |
---|
| 141 | M302_IVEC_SCC3 =8, |
---|
| 142 | M302_IVEC_TIMER1 =9, |
---|
| 143 | M302_IVEC_SCC2 =10, |
---|
| 144 | M302_IVEC_IDMA =11, |
---|
| 145 | M302_IVEC_SDMA =12, /* SDMA Channels Bus Error */ |
---|
| 146 | M302_IVEC_SCC1 =13, |
---|
| 147 | M302_IVEC_PB10 =14, /* General-Purpose Interrupt 2 */ |
---|
| 148 | M302_IVEC_PB11 =15, /* General-Purpose Interrupt 3 */ |
---|
| 149 | M302_IVEC_IRQ1 =17, /* External Device */ |
---|
| 150 | M302_IVEC_IRQ6 =22, /* External Device */ |
---|
| 151 | M302_IVEC_IRQ7 =23 /* External Device */ |
---|
| 152 | }; |
---|
| 153 | |
---|
| 154 | |
---|
| 155 | /* |
---|
| 156 | * GIMR - Global Interrupt Mode Register |
---|
| 157 | * Section 3.2.5.1 |
---|
| 158 | */ |
---|
| 159 | #define RBIT_GIMR_MOD (1<<15) |
---|
| 160 | #define RBIT_GIMR_IV7 (1<<14) |
---|
| 161 | #define RBIT_GIMR_IV6 (1<<13) |
---|
| 162 | #define RBIT_GIMR_IV1 (1<<12) |
---|
| 163 | #define RBIT_GIMR_ET7 (1<<10) |
---|
| 164 | #define RBIT_GIMR_ET6 (1<<9) |
---|
| 165 | #define RBIT_GIMR_ET1 (1<<8) |
---|
| 166 | #define RBIT_GIMR_VECTOR (7<<5) |
---|
| 167 | |
---|
| 168 | /* |
---|
| 169 | * IPR - Interrupt Pending Register (Section 3.2.5.2) |
---|
| 170 | * IMR - Interrupt Mask Register (Section 3.2.5.3) |
---|
| 171 | * ISR - Interrupt In-Service Register (Section 3.2.5.4) |
---|
| 172 | */ |
---|
| 173 | #define RBIT_IPR_PB11 (1<<15) |
---|
| 174 | #define RBIT_IPR_PB10 (1<<14) |
---|
| 175 | #define RBIT_IPR_SCC1 (1<<13) |
---|
| 176 | #define RBIT_IPR_SDMA (1<<12) |
---|
| 177 | #define RBIT_IPR_IDMA (1<<11) |
---|
| 178 | #define RBIT_IPR_SCC2 (1<<10) |
---|
| 179 | #define RBIT_IPR_TIMER1 (1<<9) |
---|
| 180 | #define RBIT_IPR_SCC3 (1<<8) |
---|
| 181 | #define RBIT_IPR_PB9 (1<<7) |
---|
| 182 | #define RBIT_IPR_TIMER2 (1<<6) |
---|
| 183 | #define RBIT_IPR_SCP (1<<5) |
---|
| 184 | #define RBIT_IPR_TIMER3 (1<<4) |
---|
| 185 | #define RBIT_IPR_SMC1 (1<<3) |
---|
| 186 | #define RBIT_IPR_SMC2 (1<<2) |
---|
| 187 | #define RBIT_IPR_PB8 (1<<1) |
---|
| 188 | #define RBIT_IPR_ERR (1<<0) |
---|
| 189 | |
---|
| 190 | #define RBIT_ISR_PB11 (1<<15) |
---|
| 191 | #define RBIT_ISR_PB10 (1<<14) |
---|
| 192 | #define RBIT_ISR_SCC1 (1<<13) |
---|
| 193 | #define RBIT_ISR_SDMA (1<<12) |
---|
| 194 | #define RBIT_ISR_IDMA (1<<11) |
---|
| 195 | #define RBIT_ISR_SCC2 (1<<10) |
---|
| 196 | #define RBIT_ISR_TIMER1 (1<<9) |
---|
| 197 | #define RBIT_ISR_SCC3 (1<<8) |
---|
| 198 | #define RBIT_ISR_PB9 (1<<7) |
---|
| 199 | #define RBIT_ISR_TIMER2 (1<<6) |
---|
| 200 | #define RBIT_ISR_SCP (1<<5) |
---|
| 201 | #define RBIT_ISR_TIMER3 (1<<4) |
---|
| 202 | #define RBIT_ISR_SMC1 (1<<3) |
---|
| 203 | #define RBIT_ISR_SMC2 (1<<2) |
---|
| 204 | #define RBIT_ISR_PB8 (1<<1) |
---|
| 205 | |
---|
| 206 | #define RBIT_IMR_PB11 (1<<15) /* PB11 Interrupt Mask */ |
---|
| 207 | #define RBIT_IMR_PB10 (1<<14) /* PB10 Interrupt Mask */ |
---|
| 208 | #define RBIT_IMR_SCC1 (1<<13) /* SCC1 Interrupt Mask */ |
---|
| 209 | #define RBIT_IMR_SDMA (1<<12) /* SDMA Interrupt Mask */ |
---|
| 210 | #define RBIT_IMR_IDMA (1<<11) /* IDMA Interrupt Mask */ |
---|
| 211 | #define RBIT_IMR_SCC2 (1<<10) /* SCC2 Interrupt Mask */ |
---|
| 212 | #define RBIT_IMR_TIMER1 (1<<9) /* TIMER1 Interrupt Mask */ |
---|
| 213 | #define RBIT_IMR_SCC3 (1<<8) /* SCC3 Interrupt Mask */ |
---|
| 214 | #define RBIT_IMR_PB9 (1<<7) /* PB9 Interrupt Mask */ |
---|
| 215 | #define RBIT_IMR_TIMER2 (1<<6) /* TIMER2 Interrupt Mask */ |
---|
| 216 | #define RBIT_IMR_SCP (1<<5) /* SCP Interrupt Mask */ |
---|
| 217 | #define RBIT_IMR_TIMER3 (1<<4) /* TIMER3 Interrupt Mask */ |
---|
| 218 | #define RBIT_IMR_SMC1 (1<<3) /* SMC1 Interrupt Mask */ |
---|
| 219 | #define RBIT_IMR_SMC2 (1<<2) /* SMC2 Interrupt Mask */ |
---|
| 220 | #define RBIT_IMR_PB8 (1<<1) /* PB8 Interrupt Mask */ |
---|
| 221 | |
---|
| 222 | |
---|
| 223 | /* |
---|
| 224 | * DRAM Refresh |
---|
| 225 | * Section 3.9 |
---|
| 226 | * |
---|
| 227 | * The DRAM refresh memory map replaces the SCC2 Tx BD 6 and Tx BD 7 |
---|
| 228 | * structures in the parameter RAM. |
---|
| 229 | * |
---|
| 230 | * Access to the DRAM registers can be accomplished by |
---|
| 231 | * the following approach: |
---|
| 232 | * |
---|
| 233 | * volatile m302_DRAM_refresh_t *dram; |
---|
| 234 | * dram = (volatile m302_DRAM_refresh_t *) &m302.scc2.bd.tx[6]; |
---|
| 235 | * |
---|
| 236 | * Then simply use pointer references (e.g. dram->count = 3). |
---|
| 237 | */ |
---|
| 238 | typedef struct { |
---|
[d86bae8] | 239 | uint16_t dram_high; /* DRAM high address and FC */ |
---|
| 240 | uint16_t dram_low; /* DRAM low address */ |
---|
| 241 | uint16_t increment; /* increment step (bytes/row) */ |
---|
| 242 | uint16_t count; /* RAM refresh cycle count (#rows) */ |
---|
| 243 | uint16_t t_ptr_h; /* temporary refresh high addr & FC */ |
---|
| 244 | uint16_t t_ptr_l; /* temporary refresh low address */ |
---|
| 245 | uint16_t t_count; /* temporary refresh cycles count */ |
---|
| 246 | uint16_t res; /* reserved */ |
---|
[12710a56] | 247 | } m302_DRAM_refresh_t; |
---|
| 248 | |
---|
| 249 | |
---|
| 250 | /* |
---|
| 251 | * TMR - Timer Mode Register (for timers 1 and 2) |
---|
| 252 | * Section 3.5.2.1 |
---|
| 253 | */ |
---|
| 254 | #define RBIT_TMR_ICLK_STOP (0<<1) |
---|
| 255 | #define RBIT_TMR_ICLK_MASTER (1<<1) |
---|
| 256 | #define RBIT_TMR_ICLK_MASTER16 (2<<1) |
---|
| 257 | #define RBIT_TMR_ICLK_TIN (3<<1) |
---|
| 258 | |
---|
| 259 | #define RBIT_TMR_OM (1<<5) |
---|
| 260 | #define RBIT_TMR_ORI (1<<4) |
---|
| 261 | #define RBIT_TMR_FRR (1<<3) |
---|
| 262 | #define RBIT_TMR_RST (1<<0) |
---|
| 263 | |
---|
| 264 | |
---|
| 265 | /* |
---|
| 266 | * TER - Timer Event Register (for timers 1 and 2) |
---|
| 267 | * Section 3.5.2.5 |
---|
| 268 | */ |
---|
| 269 | #define RBIT_TER_REF (1<<1) /* Output Reference Event */ |
---|
| 270 | #define RBIT_TER_CAP (1<<0) /* Capture Event */ |
---|
| 271 | |
---|
| 272 | |
---|
| 273 | /* |
---|
| 274 | * SCC Buffer Descriptors and Buffer Descriptors Table |
---|
| 275 | * Section 4.5.5 |
---|
| 276 | */ |
---|
| 277 | typedef struct m302_SCC_bd { |
---|
[d86bae8] | 278 | uint16_t status; /* status and control */ |
---|
| 279 | uint16_t length; /* data length */ |
---|
| 280 | volatile uint8_t *buffer; /* data buffer pointer */ |
---|
[12710a56] | 281 | } m302_SCC_bd_t; |
---|
| 282 | |
---|
| 283 | typedef struct { |
---|
| 284 | m302_SCC_bd_t rx[8]; /* receive buffer descriptors */ |
---|
| 285 | m302_SCC_bd_t tx[8]; /* transmit buffer descriptors */ |
---|
| 286 | } m302_SCC_bd_table_t; |
---|
| 287 | |
---|
| 288 | |
---|
| 289 | /* |
---|
| 290 | * SCC Parameter RAM (offset 0x080 from an SCC Base) |
---|
| 291 | * Section 4.5.6 |
---|
| 292 | * |
---|
| 293 | * Each SCC parameter RAM area begins at offset 0x80 from each SCC base |
---|
| 294 | * area (0x400, 0x500, or 0x600 from the dual-port RAM base). |
---|
| 295 | * |
---|
| 296 | * Offsets 0x9c-0xbf from each SCC base area compose the protocol-specific |
---|
| 297 | * portion of the SCC parameter RAM. |
---|
| 298 | */ |
---|
| 299 | typedef struct { |
---|
[d86bae8] | 300 | uint8_t rfcr; /* Rx Function Code */ |
---|
| 301 | uint8_t tfcr; /* Tx Function Code */ |
---|
| 302 | uint16_t mrblr; /* Maximum Rx Buffer Length */ |
---|
| 303 | uint16_t _rstate; /* Rx Internal State */ |
---|
| 304 | uint8_t res2; |
---|
| 305 | uint8_t rbd; /* Rx Internal Buffer Number */ |
---|
| 306 | uint32_t _rdptr; /* Rx Internal Data Pointer */ |
---|
| 307 | uint16_t _rcount; /* Rx Internal Byte Count */ |
---|
| 308 | uint16_t _rtmp; /* Rx Temp */ |
---|
| 309 | uint16_t _tstate; /* Tx Internal State */ |
---|
| 310 | uint8_t res7; |
---|
| 311 | uint8_t tbd; /* Tx Internal Buffer Number */ |
---|
| 312 | uint32_t _tdptr; /* Tx Internal Data Pointer */ |
---|
| 313 | uint16_t _tcount; /* Tx Internal Byte Count */ |
---|
| 314 | uint16_t _ttmp; /* Tx Temp */ |
---|
[12710a56] | 315 | } m302_SCC_parameters_t; |
---|
| 316 | |
---|
| 317 | /* |
---|
| 318 | * UART-Specific SCC Parameter RAM |
---|
| 319 | * Section 4.5.11.3 |
---|
| 320 | */ |
---|
| 321 | typedef struct { |
---|
[d86bae8] | 322 | uint16_t max_idl; /* Maximum IDLE Characters (rx) */ |
---|
| 323 | uint16_t idlc; /* Temporary rx IDLE counter */ |
---|
| 324 | uint16_t brkcr; /* Break Count Register (tx) */ |
---|
| 325 | uint16_t parec; /* Receive Parity Error Counter */ |
---|
| 326 | uint16_t frmec; /* Receive Framing Error Counter */ |
---|
| 327 | uint16_t nosec; /* Receive Noise Counter */ |
---|
| 328 | uint16_t brkec; /* Receive Break Condition Counter */ |
---|
| 329 | uint16_t uaddr1; /* UART ADDRESS Character 1 */ |
---|
| 330 | uint16_t uaddr2; /* UART ADDRESS Character 2 */ |
---|
| 331 | uint16_t rccr; /* Receive Control Character Register */ |
---|
| 332 | uint16_t character[8]; /* Control Characters 1 through 8*/ |
---|
[12710a56] | 333 | } m302_SCC_UartSpecific_t; |
---|
| 334 | /* |
---|
| 335 | * This definition allows for the checking of receive buffers |
---|
| 336 | * for errors. |
---|
| 337 | */ |
---|
| 338 | |
---|
| 339 | #define RCV_ERR 0x003F |
---|
| 340 | |
---|
| 341 | /* |
---|
| 342 | * UART receive buffer descriptor bit definitions. |
---|
| 343 | * Section 4.5.11.14 |
---|
| 344 | */ |
---|
| 345 | #define RBIT_UART_CTRL (1<<11) /* buffer contains a control char */ |
---|
| 346 | #define RBIT_UART_ADDR (1<<10) /* first byte contains an address */ |
---|
| 347 | #define RBIT_UART_MATCH (1<<9) /* indicates which addr char matched */ |
---|
| 348 | #define RBIT_UART_IDLE (1<<8) /* buffer closed due to IDLE sequence */ |
---|
| 349 | #define RBIT_UART_BR (1<<5) /* break sequence was received */ |
---|
| 350 | #define RBIT_UART_FR (1<<4) /* framing error was received */ |
---|
| 351 | #define RBIT_UART_PR (1<<3) /* parity error was received */ |
---|
| 352 | #define RBIT_UART_OV (1<<1) /* receiver overrun occurred */ |
---|
| 353 | #define RBIT_UART_CD (1<<0) /* carrier detect lost */ |
---|
| 354 | #define RBIT_UART_STATUS 0x003B /* all status bits */ |
---|
| 355 | |
---|
| 356 | /* |
---|
| 357 | * UART transmit buffer descriptor bit definitions. |
---|
| 358 | * Section 4.5.11.15 |
---|
| 359 | */ |
---|
| 360 | #define RBIT_UART_CR (1<<11) /* clear-to-send report |
---|
| 361 | * this results in two idle bits |
---|
| 362 | * between back-to-back frames |
---|
| 363 | */ |
---|
| 364 | #define RBIT_UART_A (1<<10) /* buffer contains address characters |
---|
| 365 | * only valid in multidrop mode (UM0=1) |
---|
| 366 | */ |
---|
| 367 | #define RBIT_UART_PREAMBLE (1<<9) /* send preamble before data */ |
---|
| 368 | #define RBIT_UART_CTS_LOST (1<<0) /* CTS lost */ |
---|
| 369 | |
---|
| 370 | /* |
---|
| 371 | * UART event register |
---|
| 372 | * Section 4.5.11.16 |
---|
| 373 | */ |
---|
| 374 | #define M302_UART_EV_CTS (1<<7) /* CTS status changed */ |
---|
| 375 | #define M302_UART_EV_CD (1<<6) /* carrier detect status changed */ |
---|
| 376 | #define M302_UART_EV_IDL (1<<5) /* IDLE sequence status changed */ |
---|
| 377 | #define M302_UART_EV_BRK (1<<4) /* break character was received */ |
---|
| 378 | #define M302_UART_EV_CCR (1<<3) /* control character received */ |
---|
| 379 | #define M302_UART_EV_TX (1<<1) /* buffer has been transmitted */ |
---|
| 380 | #define M302_UART_EV_RX (1<<0) /* buffer has been received */ |
---|
| 381 | |
---|
| 382 | |
---|
| 383 | /* |
---|
| 384 | * HDLC-Specific SCC Parameter RAM |
---|
| 385 | * Section 4.5.12.3 |
---|
| 386 | * |
---|
| 387 | * c_mask_l should be 0xF0B8 for 16-bit CRC, 0xdebb for 32-bit CRC |
---|
| 388 | * c_mask_h is a don't care for 16-bit CRC, 0x20E2 for 32-bit CRC |
---|
| 389 | */ |
---|
| 390 | typedef struct { |
---|
[d86bae8] | 391 | uint16_t rcrc_l; /* Temp Receive CRC Low */ |
---|
| 392 | uint16_t rcrc_h; /* Temp Receive CRC High */ |
---|
| 393 | uint16_t c_mask_l; /* CRC Mask Low */ |
---|
| 394 | uint16_t c_mask_h; /* CRC Mask High */ |
---|
| 395 | uint16_t tcrc_l; /* Temp Transmit CRC Low */ |
---|
| 396 | uint16_t tcrc_h; /* Temp Transmit CRC High */ |
---|
| 397 | |
---|
| 398 | uint16_t disfc; /* Discard Frame Counter */ |
---|
| 399 | uint16_t crcec; /* CRC Error Counter */ |
---|
| 400 | uint16_t abtsc; /* Abort Sequence Counter */ |
---|
| 401 | uint16_t nmarc; /* Nonmatching Address Received Cntr */ |
---|
| 402 | uint16_t retrc; /* Frame Retransmission Counter */ |
---|
| 403 | |
---|
| 404 | uint16_t mflr; /* Maximum Frame Length Register */ |
---|
| 405 | uint16_t max_cnt; /* Maximum_Length Counter */ |
---|
| 406 | |
---|
| 407 | uint16_t hmask; /* User Defined Frame Address Mask */ |
---|
| 408 | uint16_t haddr1; /* User Defined Frame Address */ |
---|
| 409 | uint16_t haddr2; /* " */ |
---|
| 410 | uint16_t haddr3; /* " */ |
---|
| 411 | uint16_t haddr4; /* " */ |
---|
[12710a56] | 412 | } m302_SCC_HdlcSpecific_t; |
---|
| 413 | /* |
---|
| 414 | * HDLC receiver buffer descriptor bit definitions |
---|
| 415 | * Section 4.5.12.10 |
---|
| 416 | */ |
---|
| 417 | #define RBIT_HDLC_EMPTY_BIT 0x8000 /* buffer associated with BD is empty */ |
---|
| 418 | #define RBIT_HDLC_LAST_BIT 0x0800 /* buffer is last in a frame */ |
---|
| 419 | #define RBIT_HDLC_FIRST_BIT 0x0400 /* buffer is first in a frame */ |
---|
| 420 | #define RBIT_HDLC_FRAME_LEN 0x0020 /* receiver frame length violation */ |
---|
| 421 | #define RBIT_HDLC_NONOCT_Rx 0x0010 /* received non-octet aligned frame */ |
---|
| 422 | #define RBIT_HDLC_ABORT_SEQ 0x0008 /* received abort sequence */ |
---|
| 423 | #define RBIT_HDLC_CRC_ERROR 0x0004 /* frame contains a CRC error */ |
---|
| 424 | #define RBIT_HDLC_OVERRUN 0x0002 /* receiver overrun occurred */ |
---|
| 425 | #define RBIT_HDLC_CD_LOST 0x0001 /* carrier detect lost */ |
---|
| 426 | |
---|
| 427 | /* |
---|
| 428 | * HDLC transmit buffer descriptor bit definitions |
---|
| 429 | * Section 4.5.12.11 |
---|
| 430 | */ |
---|
| 431 | #define RBIT_HDLC_READY_BIT 0x8000 /* buffer is ready to transmit */ |
---|
| 432 | #define RBIT_HDLC_EXT_BUFFER 0x4000 /* buffer is in external memory */ |
---|
| 433 | #define RBIT_HDLC_WRAP_BIT 0x2000 /* last buffer in bd table, so wrap */ |
---|
| 434 | #define RBIT_HDLC_WAKE_UP 0x1000 /* interrupt when buffer serviced */ |
---|
| 435 | #define RBIT_HDLC_LAST_BIT 0x0800 /* buffer is last in the frame */ |
---|
| 436 | #define RBIT_HDLC_TxCRC_BIT 0x0400 /* transmit a CRC sequence */ |
---|
| 437 | #define RBIT_HDLC_UNDERRUN 0x0002 /* transmitter underrun */ |
---|
| 438 | #define RBIT_HDLC_CTS_LOST 0x0001 /* CTS lost */ |
---|
| 439 | |
---|
| 440 | /* |
---|
| 441 | * HDLC event register bit definitions |
---|
| 442 | * Section 4.5.12.12 |
---|
| 443 | */ |
---|
| 444 | #define RBIT_HDLC_CTS 0x80 /* CTS status changed */ |
---|
| 445 | #define RBIT_HDLC_CD 0x40 /* carrier detect status changed */ |
---|
| 446 | #define RBIT_HDLC_IDL 0x20 /* IDLE sequence status changed */ |
---|
| 447 | #define RBIT_HDLC_TXE 0x10 /* transmit error */ |
---|
| 448 | #define RBIT_HDLC_RXF 0x08 /* received frame */ |
---|
| 449 | #define RBIT_HDLC_BSY 0x04 /* frame rcvd and discarded due to |
---|
| 450 | * lack of buffers |
---|
| 451 | */ |
---|
| 452 | #define RBIT_HDLC_TXB 0x02 /* buffer has been transmitted */ |
---|
| 453 | #define RBIT_HDLC_RXB 0x01 /* received buffer */ |
---|
| 454 | |
---|
| 455 | |
---|
| 456 | |
---|
| 457 | typedef struct { |
---|
| 458 | m302_SCC_bd_table_t bd; /* +000 Buffer Descriptor Table */ |
---|
| 459 | m302_SCC_parameters_t parm; /* +080 Common Parameter RAM */ |
---|
| 460 | union { /* +09C Protocol-Specific Parm RAM */ |
---|
| 461 | m302_SCC_UartSpecific_t uart; |
---|
| 462 | m302_SCC_HdlcSpecific_t hdlc; |
---|
| 463 | } prot; |
---|
[d86bae8] | 464 | uint8_t res[0x040]; /* +0C0 reserved, (not implemented) */ |
---|
[12710a56] | 465 | } m302_SCC_t; |
---|
| 466 | |
---|
| 467 | |
---|
| 468 | /* |
---|
| 469 | * Common SCC Registers |
---|
| 470 | */ |
---|
| 471 | typedef struct { |
---|
[d86bae8] | 472 | uint16_t res1; |
---|
| 473 | uint16_t scon; /* SCC Configuration Register 4.5.2 */ |
---|
| 474 | uint16_t scm; /* SCC Mode Register 4.5.3 */ |
---|
| 475 | uint16_t dsr; /* SCC Data Synchronization Register 4.5.4 */ |
---|
| 476 | uint8_t scce; /* SCC Event Register 4.5.8.1 */ |
---|
| 477 | uint8_t res2; |
---|
| 478 | uint8_t sccm; /* SCC Mask Register 4.5.8.2 */ |
---|
| 479 | uint8_t res3; |
---|
| 480 | uint8_t sccs; /* SCC Status Register 4.5.8.3 */ |
---|
| 481 | uint8_t res4; |
---|
| 482 | uint16_t res5; |
---|
[12710a56] | 483 | } m302_SCC_Registers_t; |
---|
| 484 | |
---|
| 485 | /* |
---|
| 486 | * SCON - SCC Configuration Register |
---|
| 487 | * Section 4.5.2 |
---|
| 488 | */ |
---|
| 489 | #define RBIT_SCON_WOMS (1<<15) /* Wired-OR Mode Select (NMSI mode only) |
---|
| 490 | * When set, the TXD driver is an |
---|
| 491 | * open-drain output */ |
---|
| 492 | #define RBIT_SCON_EXTC (1<<14) /* External Clock Source */ |
---|
| 493 | #define RBIT_SCON_TCS (1<<13) /* Transmit Clock Source */ |
---|
| 494 | #define RBIT_SCON_RCS (1<<12) /* Receive Clock Source */ |
---|
| 495 | |
---|
| 496 | /* |
---|
| 497 | * SCM - SCC Mode Register bit definitions |
---|
| 498 | * Section 4.5.3 |
---|
| 499 | * The parameter-specific mode bits occupy bits 15 through 6. |
---|
| 500 | */ |
---|
| 501 | #define RBIT_SCM_ENR (1<<3) /* Enable receiver */ |
---|
| 502 | #define RBIT_SCM_ENT (1<<2) /* Enable transmitter */ |
---|
| 503 | |
---|
| 504 | |
---|
| 505 | /* |
---|
| 506 | * Internal MC68302 Registers |
---|
| 507 | * starts at offset 0x800 from dual-port RAM base |
---|
| 508 | * Section 2.8 |
---|
| 509 | */ |
---|
| 510 | typedef struct { |
---|
| 511 | /* offset +800 */ |
---|
[d86bae8] | 512 | uint16_t res0; |
---|
| 513 | uint16_t cmr; /* IDMA Channel Mode Register */ |
---|
| 514 | uint32_t sapr; /* IDMA Source Address Pointer */ |
---|
| 515 | uint32_t dapr; /* IDMA Destination Address Pointer */ |
---|
| 516 | uint16_t bcr; /* IDMA Byte Count Register */ |
---|
| 517 | uint8_t csr; /* IDMA Channel Status Register */ |
---|
| 518 | uint8_t res1; |
---|
| 519 | uint8_t fcr; /* IDMA Function Code Register */ |
---|
| 520 | uint8_t res2; |
---|
[12710a56] | 521 | |
---|
| 522 | /* offset +812 */ |
---|
[d86bae8] | 523 | uint16_t gimr; /* Global Interrupt Mode Register */ |
---|
| 524 | uint16_t ipr; /* Interrupt Pending Register */ |
---|
| 525 | uint16_t imr; /* Interrupt Mask Register */ |
---|
| 526 | uint16_t isr; /* Interrupt In-Service Register */ |
---|
| 527 | uint16_t res3; |
---|
| 528 | uint16_t res4; |
---|
[12710a56] | 529 | |
---|
| 530 | /* offset +81e */ |
---|
[d86bae8] | 531 | uint16_t pacnt; /* Port A Control Register */ |
---|
| 532 | uint16_t paddr; /* Port A Data Direction Register */ |
---|
| 533 | uint16_t padat; /* Port A Data Register */ |
---|
| 534 | uint16_t pbcnt; /* Port B Control Register */ |
---|
| 535 | uint16_t pbddr; /* Port B Data Direction Register */ |
---|
| 536 | uint16_t pbdat; /* Port B Data Register */ |
---|
| 537 | uint16_t res5; |
---|
[12710a56] | 538 | |
---|
| 539 | /* offset +82c */ |
---|
[d86bae8] | 540 | uint16_t res6; |
---|
| 541 | uint16_t res7; |
---|
| 542 | |
---|
| 543 | uint16_t br0; /* Base Register (CS0) */ |
---|
| 544 | uint16_t or0; /* Option Register (CS0) */ |
---|
| 545 | uint16_t br1; /* Base Register (CS1) */ |
---|
| 546 | uint16_t or1; /* Option Register (CS1) */ |
---|
| 547 | uint16_t br2; /* Base Register (CS2) */ |
---|
| 548 | uint16_t or2; /* Option Register (CS2) */ |
---|
| 549 | uint16_t br3; /* Base Register (CS3) */ |
---|
| 550 | uint16_t or3; /* Option Register (CS3) */ |
---|
[12710a56] | 551 | |
---|
| 552 | /* offset +840 */ |
---|
[d86bae8] | 553 | uint16_t tmr1; /* Timer Unit 1 Mode Register */ |
---|
| 554 | uint16_t trr1; /* Timer Unit 1 Reference Register */ |
---|
| 555 | uint16_t tcr1; /* Timer Unit 1 Capture Register */ |
---|
| 556 | uint16_t tcn1; /* Timer Unit 1 Counter */ |
---|
| 557 | uint8_t res8; |
---|
| 558 | uint8_t ter1; /* Timer Unit 1 Event Register */ |
---|
| 559 | uint16_t wrr; /* Watchdog Reference Register */ |
---|
| 560 | uint16_t wcn; /* Watchdog Counter */ |
---|
| 561 | uint16_t res9; |
---|
| 562 | uint16_t tmr2; /* Timer Unit 2 Mode Register */ |
---|
| 563 | uint16_t trr2; /* Timer Unit 2 Reference Register */ |
---|
| 564 | uint16_t tcr2; /* Timer Unit 2 Capture Register */ |
---|
| 565 | uint16_t tcn2; /* Timer Unit 2 Counter */ |
---|
| 566 | uint8_t resa; |
---|
| 567 | uint8_t ter2; /* Timer Unit 2 Event Register */ |
---|
| 568 | uint16_t resb; |
---|
| 569 | uint16_t resc; |
---|
| 570 | uint16_t resd; |
---|
[12710a56] | 571 | |
---|
| 572 | /* offset +860 */ |
---|
[d86bae8] | 573 | uint8_t cr; /* Command Register */ |
---|
| 574 | uint8_t rese[0x1f]; |
---|
[12710a56] | 575 | |
---|
| 576 | /* offset +880, +890, +8a0 */ |
---|
| 577 | m302_SCC_Registers_t scc[3]; /* SCC1, SCC2, SCC3 Registers */ |
---|
| 578 | |
---|
| 579 | /* offset +8b0 */ |
---|
[d86bae8] | 580 | uint16_t spmode; /* SCP,SMC Mode and Clock Cntrl Reg */ |
---|
| 581 | uint16_t simask; /* Serial Interface Mask Register */ |
---|
| 582 | uint16_t simode; /* Serial Interface Mode Register */ |
---|
[12710a56] | 583 | } m302_internalReg_t ; |
---|
| 584 | |
---|
| 585 | |
---|
| 586 | /* |
---|
| 587 | * MC68302 dual-port RAM structure. |
---|
| 588 | * (Includes System RAM, Parameter RAM, and Internal Registers). |
---|
| 589 | * Section 2.8 |
---|
| 590 | */ |
---|
| 591 | typedef struct { |
---|
[d86bae8] | 592 | uint8_t mem[0x240]; /* +000 User Data Memory */ |
---|
| 593 | uint8_t res1[0x1c0]; /* +240 reserved, (not implemented) */ |
---|
[12710a56] | 594 | m302_SCC_t scc1; /* +400 SCC1 */ |
---|
| 595 | m302_SCC_t scc2; /* +500 SCC2 */ |
---|
| 596 | m302_SCC_t scc3; /* +600 SCC3 */ |
---|
[d86bae8] | 597 | uint8_t res2[0x100]; /* +700 reserved, (not implemented) */ |
---|
[12710a56] | 598 | m302_internalReg_t reg; /* +800 68302 Internal Registers */ |
---|
| 599 | } m302_dualPortRAM_t; |
---|
| 600 | |
---|
| 601 | /* some useful defines the some of the registers above */ |
---|
| 602 | |
---|
| 603 | |
---|
| 604 | /* ---- |
---|
| 605 | MC68302 Chip Select Registers |
---|
| 606 | p3-46 2nd Edition |
---|
| 607 | |
---|
| 608 | */ |
---|
| 609 | #define BR_ENABLED 1 |
---|
| 610 | #define BR_DISABLED 0 |
---|
| 611 | #define BR_FC_NULL 0 |
---|
| 612 | #define BR_READ_ONLY 0 |
---|
| 613 | #define BR_READ_WRITE 2 |
---|
| 614 | #define OR_DTACK_0 0x0000 |
---|
| 615 | #define OR_DTACK_1 0x2000 |
---|
| 616 | #define OR_DTACK_2 0x4000 |
---|
| 617 | #define OR_DTACK_3 0x6000 |
---|
| 618 | #define OR_DTACK_4 0x8000 |
---|
| 619 | #define OR_DTACK_5 0xA000 |
---|
| 620 | #define OR_DTACK_6 0xC000 |
---|
| 621 | #define OR_DTACK_EXT 0xE000 |
---|
| 622 | #define OR_SIZE_64K 0x1FE0 |
---|
| 623 | #define OR_SIZE_128K 0x1FC0 |
---|
| 624 | #define OR_SIZE_256K 0x1F80 |
---|
| 625 | #define OR_SIZE_512K 0x1F00 |
---|
| 626 | #define OR_SIZE_1M 0x1E00 |
---|
| 627 | #define OR_SIZE_2M 0x1C00 |
---|
| 628 | #define OR_MASK_RW 0x0000 |
---|
| 629 | #define OR_NO_MASK_RW 0x0002 |
---|
| 630 | #define OR_MASK_FC 0x0000 |
---|
| 631 | #define OR_NO_MASK_FC 0x0001 |
---|
| 632 | |
---|
| 633 | #define MAKE_BR(base_address, enable, rw, fc) \ |
---|
| 634 | ((base_address >> 11) | fc | rw | enable) |
---|
| 635 | |
---|
| 636 | #define MAKE_OR(bsize, DtAck, RW_Mask, FC_Mask) \ |
---|
| 637 | (DtAck | ((~(bsize - 1) & 0x00FFFFFF) >> 11) | FC_Mask | RW_Mask) |
---|
| 638 | |
---|
| 639 | #define __REG_CAT(r, n) r ## n |
---|
| 640 | #define WRITE_BR(csel, base_address, enable, rw, fc) \ |
---|
| 641 | __REG_CAT(m302.reg.br, csel) = MAKE_BR(base_address, enable, rw, fc) |
---|
| 642 | #define WRITE_OR(csel, bsize, DtAck, RW_Mask, FC_Mask) \ |
---|
| 643 | __REG_CAT(m302.reg.or, csel) = MAKE_OR(bsize, DtAck, RW_Mask, FC_Mask) |
---|
| 644 | |
---|
| 645 | /* ---- |
---|
| 646 | MC68302 Watchdog Timer Enable Bit |
---|
| 647 | |
---|
| 648 | */ |
---|
| 649 | #define WATCHDOG_ENABLE (1) |
---|
| 650 | #define WATCHDOG_TRIGGER() (m302.reg.wrr = 0x10 | WATCHDOG_ENABLE, m302.reg.wcn = 0) |
---|
| 651 | #define WATCHDOG_TOGGLE() (m302.reg.wcn = WATCHDOG_TIMEOUT_PERIOD) |
---|
| 652 | #define DISABLE_WATCHDOG() (m302.reg.wrr = 0) |
---|
| 653 | |
---|
| 654 | /* |
---|
| 655 | * Declare the variable that's used to reference the variables in |
---|
| 656 | * the dual-port RAM. |
---|
| 657 | */ |
---|
| 658 | extern volatile m302_dualPortRAM_t m302; |
---|
| 659 | |
---|
| 660 | #endif |
---|