1 | /* SPDX-License-Identifier: BSD-2-Clause */ |
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2 | |
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3 | /** |
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4 | * @file |
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5 | * |
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6 | * @brief CPU Port Implementation API |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2013 embedded brains GmbH |
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11 | * |
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12 | * Redistribution and use in source and binary forms, with or without |
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13 | * modification, are permitted provided that the following conditions |
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14 | * are met: |
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15 | * 1. Redistributions of source code must retain the above copyright |
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16 | * notice, this list of conditions and the following disclaimer. |
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17 | * 2. Redistributions in binary form must reproduce the above copyright |
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18 | * notice, this list of conditions and the following disclaimer in the |
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19 | * documentation and/or other materials provided with the distribution. |
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20 | * |
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21 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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22 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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23 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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24 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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25 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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26 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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27 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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28 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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29 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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30 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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31 | * POSSIBILITY OF SUCH DAMAGE. |
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32 | */ |
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33 | |
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34 | #ifndef _RTEMS_SCORE_CPUIMPL_H |
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35 | #define _RTEMS_SCORE_CPUIMPL_H |
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36 | |
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37 | #include <rtems/score/cpu.h> |
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38 | |
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39 | /** |
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40 | * @defgroup RTEMSScoreCPUm68k Motorola 68000 and NXP ColdFire (m68k) |
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41 | * |
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42 | * @ingroup RTEMSScoreCPU |
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43 | * |
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44 | * @brief Motorola 68000 and NXP ColdFire (m68k) Architecture Support |
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45 | * |
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46 | * @{ |
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47 | */ |
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48 | |
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49 | #define CPU_PER_CPU_CONTROL_SIZE 0 |
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50 | |
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51 | #ifndef ASM |
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52 | |
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53 | #ifdef __cplusplus |
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54 | extern "C" { |
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55 | #endif |
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56 | |
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57 | RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error ); |
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58 | |
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59 | static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) |
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60 | { |
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61 | /* TODO */ |
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62 | } |
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63 | |
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64 | static inline void _CPU_Context_validate( uintptr_t pattern ) |
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65 | { |
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66 | while (1) { |
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67 | /* TODO */ |
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68 | } |
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69 | } |
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70 | |
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71 | static inline void _CPU_Instruction_illegal( void ) |
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72 | { |
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73 | __asm__ volatile ( "illegal" ); |
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74 | } |
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75 | |
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76 | static inline void _CPU_Instruction_no_operation( void ) |
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77 | { |
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78 | __asm__ volatile ( "nop" ); |
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79 | } |
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80 | |
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81 | static inline void _CPU_Use_thread_local_storage( |
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82 | const Context_Control *context |
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83 | ) |
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84 | { |
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85 | /* |
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86 | * There is nothing to do since the thread-local storage area is obtained by |
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87 | * calling __m68k_read_tp(). |
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88 | */ |
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89 | (void) context; |
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90 | } |
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91 | |
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92 | #ifdef __cplusplus |
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93 | } |
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94 | #endif |
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95 | |
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96 | #endif /* ASM */ |
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97 | |
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98 | /** @} */ |
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99 | |
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100 | #endif /* _RTEMS_SCORE_CPUIMPL_H */ |
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