source: rtems/cpukit/score/cpu/m68k/include/rtems/score/cpu.h @ 5c6edee

Last change on this file since 5c6edee was 5c6edee, checked in by Sebastian Huber <sebastian.huber@…>, on Nov 8, 2018 at 2:44:56 PM

m68k: Remove use of proc_ptr

Update #3585.

  • Property mode set to 100644
File size: 17.9 KB
Line 
1/**
2 * @file
3 *
4 * @brief Motorola M68K CPU Dependent Source
5 *
6 * This include file contains information pertaining to the Motorola
7 * m68xxx processor family.
8 */
9
10/*
11 *  COPYRIGHT (c) 1989-2011.
12 *  On-Line Applications Research Corporation (OAR).
13 *
14 *  The license and distribution terms for this file may be
15 *  found in the file LICENSE in this distribution or at
16 *  http://www.rtems.org/license/LICENSE.
17 */
18
19#ifndef _RTEMS_SCORE_CPU_H
20#define _RTEMS_SCORE_CPU_H
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26#include <rtems/score/basedefs.h>
27#include <rtems/score/m68k.h>
28
29/* conditional compilation parameters */
30
31/*
32 *  Does the CPU follow the simple vectored interrupt model?
33 *
34 *  If TRUE, then RTEMS allocates the vector table it internally manages.
35 *  If FALSE, then the BSP is assumed to allocate and manage the vector
36 *  table
37 *
38 *  M68K Specific Information:
39 *
40 *  XXX document implementation including references if appropriate
41 */
42#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
43
44/*
45 *  Does the RTEMS invoke the user's ISR with the vector number and
46 *  a pointer to the saved interrupt frame (1) or just the vector
47 *  number (0)?
48 */
49
50#define CPU_ISR_PASSES_FRAME_POINTER FALSE
51
52/*
53 *  Some family members have no FP, some have an FPU such as the
54 *  MC68881/MC68882 for the MC68020, others have it built in (MC68030, 040).
55 *
56 *  NOTE:  If on a CPU without hardware FP, then one can use software
57 *         emulation.  The gcc software FP emulation code has data which
58 *         must be contexted switched on a per task basis.
59 */
60
61#if ( M68K_HAS_FPU == 1 ) || ( M68K_HAS_EMAC == 1 )
62  #define CPU_HARDWARE_FP TRUE
63  #define CPU_SOFTWARE_FP FALSE
64#else
65  #define CPU_HARDWARE_FP FALSE
66  #if defined( __GNUC__ )
67    #define CPU_SOFTWARE_FP TRUE
68  #else
69    #define CPU_SOFTWARE_FP FALSE
70  #endif
71#endif
72
73/*
74 *  All tasks are not by default floating point tasks on this CPU.
75 *  The IDLE task does not have a floating point context on this CPU.
76 *  It is safe to use the deferred floating point context switch
77 *  algorithm on this CPU.
78 */
79
80#define CPU_ALL_TASKS_ARE_FP             FALSE
81#define CPU_IDLE_TASK_IS_FP              FALSE
82#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
83#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
84
85#define CPU_STACK_GROWS_UP               FALSE
86
87/* FIXME: Is this the right value? */
88#define CPU_CACHE_LINE_BYTES 16
89
90#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
91
92#define CPU_MAXIMUM_PROCESSORS 32
93
94#if ( CPU_HARDWARE_FP == TRUE ) && !defined( __mcoldfire__ )
95  #if defined( __mc68060__ )
96    #define M68K_FP_STATE_SIZE 16
97  #else
98    #define M68K_FP_STATE_SIZE 216
99  #endif
100#endif
101
102#ifndef ASM
103
104/* structures */
105
106/*
107 *  Basic integer context for the m68k family.
108 */
109
110typedef struct {
111  uint32_t    sr;                /* (sr) status register */
112  uint32_t    d2;                /* (d2) data register 2 */
113  uint32_t    d3;                /* (d3) data register 3 */
114  uint32_t    d4;                /* (d4) data register 4 */
115  uint32_t    d5;                /* (d5) data register 5 */
116  uint32_t    d6;                /* (d6) data register 6 */
117  uint32_t    d7;                /* (d7) data register 7 */
118  void       *a2;                /* (a2) address register 2 */
119  void       *a3;                /* (a3) address register 3 */
120  void       *a4;                /* (a4) address register 4 */
121  void       *a5;                /* (a5) address register 5 */
122  void       *a6;                /* (a6) address register 6 */
123  void       *a7_msp;            /* (a7) master stack pointer */
124  #if defined( __mcoldfire__ ) && ( M68K_HAS_FPU == 1 )
125    uint8_t   fpu_dis;
126  #endif
127} Context_Control;
128
129#define _CPU_Context_Get_SP( _context ) \
130  (_context)->a7_msp
131
132/*
133 *  Floating point context areas and support routines
134 */
135
136#if ( CPU_SOFTWARE_FP == TRUE )
137  /*
138   *  This is the same as gcc's view of the software FP condition code
139   *  register _fpCCR.  The implementation of the emulation code is
140   *  in the gcc-VERSION/config/m68k directory.  This structure is
141   *  correct as of gcc 2.7.2.2.
142   */
143  typedef struct {
144    uint16_t _exception_bits;
145    uint16_t _trap_enable_bits;
146    uint16_t _sticky_bits;
147    uint16_t _rounding_mode;
148    uint16_t _format;
149    uint16_t _last_operation;
150    union {
151      float sf;
152      double df;
153    } _operand1;
154    union {
155      float sf;
156      double df;
157    } _operand2;
158  } Context_Control_fp;
159
160  #define _CPU_Context_Initialize_fp( _fp_area ) \
161     { \
162       Context_Control_fp *_fp; \
163       _fp = *(Context_Control_fp **)_fp_area; \
164       _fp->_exception_bits = 0; \
165       _fp->_trap_enable_bits = 0; \
166       _fp->_sticky_bits = 0; \
167       _fp->_rounding_mode = 0;  /* ROUND_TO_NEAREST */ \
168       _fp->_format = 0;         /* NIL */ \
169       _fp->_last_operation = 0; /* NOOP */ \
170       _fp->_operand1.df = 0; \
171       _fp->_operand2.df = 0; \
172     }
173#endif
174
175#if ( CPU_HARDWARE_FP == TRUE )
176  #if defined( __mcoldfire__ )
177    /* We need memset() to initialize the FP context */
178    #include <string.h>
179
180    #if ( M68K_HAS_FPU == 1 )
181      /*
182       * The Cache Control Register (CACR) has write-only access.  It is also
183       * used to enable and disable the FPU.  We need to maintain a copy of
184       * this register to allow per thread values.
185       */
186      extern uint32_t _CPU_cacr_shadow;
187    #endif
188
189    /* We assume that each ColdFire core with a FPU has also an EMAC unit */
190    typedef struct {
191      uint32_t emac_macsr;
192      uint32_t emac_acc0;
193      uint32_t emac_acc1;
194      uint32_t emac_acc2;
195      uint32_t emac_acc3;
196      uint32_t emac_accext01;
197      uint32_t emac_accext23;
198      uint32_t emac_mask;
199      #if ( M68K_HAS_FPU == 1 )
200        uint16_t fp_state_format;
201        uint16_t fp_state_fpcr;
202        double fp_state_op;
203        uint32_t fp_state_fpsr;
204
205        /*
206         * We need to save the FP Instruction Address Register (FPIAR), because
207         * a context switch can occur within a FP exception before the handler
208         * was able to save this register.
209         */
210        uint32_t fp_fpiar;
211
212        double fp_data [8];
213      #endif
214    } Context_Control_fp;
215
216    /*
217     * The reset value for all context relevant registers except the FP data
218     * registers is zero.  The reset value of the FP data register is NAN.  The
219     * restore of the reset FP state will reset the FP data registers, so the
220     * initial value of them can be arbitrary here.
221     */
222    #define _CPU_Context_Initialize_fp( _fp_area ) \
223      memset( *(_fp_area), 0, sizeof( Context_Control_fp ) )
224  #else
225    /*
226     *  FP context save area for the M68881/M68882 and 68060 numeric
227     *  coprocessors.
228     */
229    typedef struct {
230      /*
231       * M68K_FP_STATE_SIZE bytes for FSAVE/FRESTORE
232       * 96 bytes for FMOVEM FP0-7
233       * 12 bytes for FMOVEM CREGS
234       * 4 bytes for non-null flag
235       */
236      uint8_t fp_save_area [M68K_FP_STATE_SIZE + 112];
237    } Context_Control_fp;
238
239    /*
240     * The floating-point context is saved/restored via FSAVE/FRESTORE which
241     * use a growing down stack.  Initialize the stack and adjust the FP area
242     * pointer accordingly.
243     */
244    #define _CPU_Context_Initialize_fp( _fp_area ) \
245       { \
246         uint32_t *_fp_context = _Addresses_Add_offset( \
247           *(_fp_area), CPU_CONTEXT_FP_SIZE - 4); \
248         *(--(_fp_context)) = 0; \
249         *(_fp_area) = (void *)(_fp_context); \
250       }
251  #endif
252#endif
253
254/*
255 *  The following structures define the set of information saved
256 *  on the current stack by RTEMS upon receipt of each exc/interrupt.
257 *  These are not used by m68k handlers.
258 *  The exception frame is for rdbg.
259 */
260
261typedef struct {
262  uint32_t   vecnum; /* vector number */
263} CPU_Interrupt_frame;
264
265typedef struct {
266  uint32_t   vecnum; /* vector number */
267  uint32_t   sr; /* status register */
268  uint32_t   pc; /* program counter */
269  uint32_t   d0, d1, d2, d3, d4, d5, d6, d7;
270  uint32_t   a0, a1, a2, a3, a4, a5, a6, a7;
271} CPU_Exception_frame;
272
273/* variables */
274
275extern void*                     _VBR;
276
277#endif /* ASM */
278
279/* constants */
280
281/*
282 *  This defines the number of levels and the mask used to pick those
283 *  bits out of a thread mode.
284 */
285
286#define CPU_MODES_INTERRUPT_MASK   0x00000007 /* interrupt level in mode */
287
288/*
289 *  context size area for floating point
290 */
291
292#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
293
294/*
295 *  extra stack required by the MPCI receive server thread
296 */
297
298#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
299
300/*
301 *  m68k family supports 256 distinct vectors.
302 */
303
304#define CPU_INTERRUPT_NUMBER_OF_VECTORS      256
305#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
306
307/*
308 *  This is defined if the port has a special way to report the ISR nesting
309 *  level.  Most ports maintain the variable _ISR_Nest_level.
310 */
311
312#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
313
314/*
315 *  Minimum size of a thread's stack.
316 */
317
318#define CPU_STACK_MINIMUM_SIZE           M68K_CPU_STACK_MINIMUM_SIZE
319
320/*
321 *  Maximum priority of a thread. Note based from 0 which is the idle task.
322 */
323#define CPU_PRIORITY_MAXIMUM             M68K_CPU_PRIORITY_MAXIMUM
324
325#define CPU_SIZEOF_POINTER 4
326
327/*
328 *  m68k is pretty tolerant of alignment.  Just put things on 4 byte boundaries.
329 */
330
331#define CPU_ALIGNMENT                    4
332#define CPU_HEAP_ALIGNMENT               CPU_ALIGNMENT
333
334/*
335 *  On m68k thread stacks require no further alignment after allocation
336 *  from the Workspace.
337 */
338
339#define CPU_STACK_ALIGNMENT        0
340
341#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
342
343#ifndef ASM
344
345/* macros */
346
347/*
348 *  ISR handler macros
349 *
350 *  These macros perform the following functions:
351 *     + initialize the RTEMS vector table
352 *     + disable all maskable CPU interrupts
353 *     + restore previous interrupt level (enable)
354 *     + temporarily restore interrupts (flash)
355 *     + set a particular level
356 */
357
358#define _CPU_Initialize_vectors()
359
360#define _CPU_ISR_Disable( _level ) \
361  m68k_disable_interrupts( _level )
362
363#define _CPU_ISR_Enable( _level ) \
364  m68k_enable_interrupts( _level )
365
366#define _CPU_ISR_Flash( _level ) \
367  m68k_flash_interrupts( _level )
368
369RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
370{
371  return ( level & 0x0700 ) == 0;
372}
373
374#define _CPU_ISR_Set_level( _newlevel ) \
375   m68k_set_interrupt_level( _newlevel )
376
377uint32_t   _CPU_ISR_Get_level( void );
378
379/* end of ISR handler macros */
380
381/*
382 *  Context handler macros
383 *
384 *  These macros perform the following functions:
385 *     + initialize a context area
386 *     + restart the current thread
387 *     + calculate the initial pointer into a FP context area
388 *     + initialize an FP context area
389 */
390
391void _CPU_Context_Initialize(
392  Context_Control *the_context,
393  void *stack_area_begin,
394  size_t stack_area_size,
395  uint32_t new_level,
396  void (*entry_point)( void ),
397  bool is_fp,
398  void *tls_area
399);
400
401/* end of Context handler macros */
402
403void *_CPU_Thread_Idle_body( uintptr_t ignored );
404
405/*
406 *  Fatal Error manager macros
407 *
408 *  These macros perform the following functions:
409 *    + disable interrupts and halt the CPU
410 */
411
412#if ( defined(__mcoldfire__) )
413#define _CPU_Fatal_halt( _source, _error ) \
414  { __asm__ volatile( "move.w %%sr,%%d0\n\t" \
415                  "or.l %2,%%d0\n\t" \
416                  "move.w %%d0,%%sr\n\t" \
417                  "move.l %1,%%d0\n\t" \
418                  "move.l #0xDEADBEEF,%%d1\n\t" \
419                  "halt" \
420                  : "=g" (_error) \
421                  : "0" (_error), "d"(0x0700) \
422                  : "d0", "d1" ); \
423  }
424#else
425#define _CPU_Fatal_halt( _source, _error ) \
426  { __asm__ volatile( "movl  %0,%%d0; " \
427                  "orw   #0x0700,%%sr; " \
428                  "stop  #0x2700" : "=d" ((_error)) : "0" ((_error)) ); \
429  }
430#endif
431
432/* end of Fatal Error manager macros */
433
434/*
435 *  Bitfield handler macros
436 *
437 *  These macros perform the following functions:
438 *     + scan for the highest numbered (MSB) set in a 16 bit bitfield
439 *
440 *  NOTE:
441 *
442 *    It appears that on the M68020 bitfield are always 32 bits wide
443 *    when in a register.  This code forces the bitfield to be in
444 *    memory (it really always is anyway). This allows us to
445 *    have a real 16 bit wide bitfield which operates "correctly."
446 */
447
448#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
449
450#if ( M68K_HAS_BFFFO != 1 )
451/*
452 *  Lookup table for BFFFO simulation
453 */
454extern const unsigned char _CPU_m68k_BFFFO_table[256];
455#endif
456
457#if ( M68K_HAS_BFFFO == 1 )
458
459#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
460  __asm__ volatile( "bfffo (%1),#0,#16,%0" : "=d" (_output) : "a" (&_value));
461
462#elif ( __mcfisaaplus__ )
463  /* This is simplified by the fact that RTEMS never calls it with _value=0 */
464#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
465    __asm__ volatile ( \
466       "   swap     %0\n"        \
467       "   ff1.l    %0\n"        \
468       : "=d" ((_output))        \
469       : "0" ((_value))          \
470       : "cc" ) ;
471
472#else
473/* duplicates BFFFO results for 16 bits (i.e., 15-(_priority) in
474   _CPU_Priority_bits_index is not needed), handles the 0 case, and
475   does not molest _value -- jsg */
476#if ( defined(__mcoldfire__) )
477
478#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
479  { \
480    int dumby; \
481    \
482    __asm__ volatile ( \
483       "   clr.l   %1\n"         \
484       "   move.w  %2,%1\n"      \
485       "   lsr.l   #8,%1\n"      \
486       "   beq.s   1f\n"         \
487       "   move.b  (%3,%1),%0\n" \
488       "   bra.s   0f\n"         \
489       "1: move.w  %2,%1\n"      \
490       "   move.b  (%3,%1),%0\n" \
491       "   addq.l  #8,%0\n"      \
492       "0: and.l   #0xff,%0\n"   \
493       : "=&d" ((_output)), "=&d" ((dumby))    \
494       : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \
495       : "cc" ) ; \
496  }
497#elif ( M68K_HAS_EXTB_L == 1 )
498#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
499  { \
500    int dumby; \
501    \
502    __asm__ volatile ( "   move.w  %2,%1\n"        \
503       "   lsr.w   #8,%1\n"        \
504       "   beq.s   1f\n"           \
505       "   move.b  (%3,%1.w),%0\n" \
506       "   extb.l  %0\n"           \
507       "   bra.s   0f\n"           \
508       "1: moveq.l #8,%0\n"        \
509       "   add.b   (%3,%2.w),%0\n" \
510       "0:\n"                      \
511       : "=&d" ((_output)), "=&d" ((dumby)) \
512       : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \
513       : "cc" ) ; \
514  }
515#else
516#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
517  { \
518    int dumby; \
519    \
520    __asm__ volatile ( "   move.w  %2,%1\n"        \
521       "   lsr.w   #8,%1\n"        \
522       "   beq.s   1f\n"           \
523       "   move.b  (%3,%1.w),%0\n" \
524       "   and.l   #0x000000ff,%0\n"\
525       "   bra.s   0f\n"           \
526       "1: moveq.l #8,%0\n"        \
527       "   add.b   (%3,%2.w),%0\n" \
528       "0:\n"                      \
529       : "=&d" ((_output)), "=&d" ((dumby)) \
530       : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \
531       : "cc" ) ; \
532  }
533#endif
534
535#endif
536
537/* end of Bitfield handler macros */
538
539/*
540 *  Priority handler macros
541 *
542 *  These macros perform the following functions:
543 *    + return a mask with the bit for this major/minor portion of
544 *      of thread priority set.
545 *    + translate the bit number returned by "Bitfield_find_first_bit"
546 *      into an index into the thread ready chain bit maps
547 */
548
549#define _CPU_Priority_Mask( _bit_number ) \
550  ( 0x8000 >> (_bit_number) )
551
552#define _CPU_Priority_bits_index( _priority ) \
553  (_priority)
554
555/* end of Priority handler macros */
556
557/* functions */
558
559/*
560 *  _CPU_Initialize
561 *
562 *  This routine performs CPU dependent initialization.
563 */
564
565void _CPU_Initialize(void);
566
567typedef void ( *CPU_ISR_raw_handler )( void );
568
569void _CPU_ISR_install_raw_handler(
570  uint32_t             vector,
571  CPU_ISR_raw_handler  new_handler,
572  CPU_ISR_raw_handler *old_handler
573);
574
575typedef void ( *CPU_ISR_handler )( uint32_t );
576
577void _CPU_ISR_install_vector(
578  uint32_t         vector,
579  CPU_ISR_handler  new_handler,
580  CPU_ISR_handler *old_handler
581);
582
583/*
584 *  _CPU_Context_switch
585 *
586 *  This routine switches from the run context to the heir context.
587 */
588
589void _CPU_Context_switch(
590  Context_Control  *run,
591  Context_Control  *heir
592);
593
594void _CPU_Context_Restart_self(
595  Context_Control  *the_context
596) RTEMS_NO_RETURN;
597
598/*
599 *  _CPU_Context_save_fp
600 *
601 *  This routine saves the floating point context passed to it.
602 */
603
604void _CPU_Context_save_fp(
605  Context_Control_fp **fp_context_ptr
606);
607
608/*
609 *  _CPU_Context_restore_fp
610 *
611 *  This routine restores the floating point context passed to it.
612 */
613
614void _CPU_Context_restore_fp(
615  Context_Control_fp **fp_context_ptr
616);
617
618/**
619 *  This method prints the CPU exception frame.
620 *
621 *  @param[in] frame points to the frame to be printed
622 */
623void _CPU_Exception_frame_print(
624  const CPU_Exception_frame *frame
625);
626
627typedef uint32_t CPU_Counter_ticks;
628
629uint32_t _CPU_Counter_frequency( void );
630
631CPU_Counter_ticks _CPU_Counter_read( void );
632
633static inline CPU_Counter_ticks _CPU_Counter_difference(
634  CPU_Counter_ticks second,
635  CPU_Counter_ticks first
636)
637{
638  return second - first;
639}
640
641#if (M68K_HAS_FPSP_PACKAGE == 1)
642/*
643 *  Hooks for the Floating Point Support Package (FPSP) provided by Motorola
644 *
645 *  NOTES:
646 *
647 *  Motorola 68k family CPU's before the 68040 used a coprocessor
648 *  (68881 or 68882) to handle floating point.  The 68040 has internal
649 *  floating point support -- but *not* the complete support provided by
650 *  the 68881 or 68882.  The leftover functions are taken care of by the
651 *  M68040 Floating Point Support Package.  Quoting from the MC68040
652 *  Microprocessors User's Manual, Section 9, Floating-Point Unit (MC68040):
653 *
654 *    "When used with the M68040FPSP, the MC68040 FPU is fully
655 *    compliant with IEEE floating-point standards."
656 *
657 *  M68KFPSPInstallExceptionHandlers is in libcpu/m68k/MODEL/fpsp and
658 *  is invoked early in the application code to ensure that proper FP
659 *  behavior is installed.  This is not left to the BSP to call, since
660 *  this would force all applications using that BSP to use FPSP which
661 *  is not necessarily desirable.
662 *
663 *  There is a similar package for the 68060 but RTEMS does not yet
664 *  support the 68060.
665 */
666
667void M68KFPSPInstallExceptionHandlers (void);
668
669extern int (*_FPSP_install_raw_handler)(
670  uint32_t   vector,
671  CPU_ISR_raw_handler new_handler,
672  CPU_ISR_raw_handler *old_handler
673);
674
675#endif
676
677/** Type that can store a 32-bit integer or a pointer. */
678typedef uintptr_t CPU_Uint32ptr;
679
680#endif
681
682#ifdef __cplusplus
683}
684#endif
685
686#endif
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