source: rtems/cpukit/score/cpu/m68k/include/rtems/score/cpu.h @ 2afb22b

5
Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on Dec 23, 2017 at 7:18:56 AM

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

  • Property mode set to 100644
File size: 18.9 KB
Line 
1/**
2 * @file
3 *
4 * @brief Motorola M68K CPU Dependent Source
5 *
6 * This include file contains information pertaining to the Motorola
7 * m68xxx processor family.
8 */
9
10/*
11 *  COPYRIGHT (c) 1989-2011.
12 *  On-Line Applications Research Corporation (OAR).
13 *
14 *  The license and distribution terms for this file may be
15 *  found in the file LICENSE in this distribution or at
16 *  http://www.rtems.org/license/LICENSE.
17 */
18
19#ifndef _RTEMS_SCORE_CPU_H
20#define _RTEMS_SCORE_CPU_H
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26#include <rtems/score/types.h>
27#include <rtems/score/m68k.h>
28
29/* conditional compilation parameters */
30
31/*
32 *  Does the CPU follow the simple vectored interrupt model?
33 *
34 *  If TRUE, then RTEMS allocates the vector table it internally manages.
35 *  If FALSE, then the BSP is assumed to allocate and manage the vector
36 *  table
37 *
38 *  M68K Specific Information:
39 *
40 *  XXX document implementation including references if appropriate
41 */
42#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
43
44/*
45 *  Use the m68k's hardware interrupt stack support and have the
46 *  interrupt manager allocate the memory for it.
47 */
48
49#if ( M68K_HAS_SEPARATE_STACKS == 1)
50#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 0
51#define CPU_HAS_HARDWARE_INTERRUPT_STACK 1
52#else
53#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 1
54#define CPU_HAS_HARDWARE_INTERRUPT_STACK 0
55#endif
56#define CPU_ALLOCATE_INTERRUPT_STACK     1
57
58/*
59 *  Does the RTEMS invoke the user's ISR with the vector number and
60 *  a pointer to the saved interrupt frame (1) or just the vector
61 *  number (0)?
62 */
63
64#define CPU_ISR_PASSES_FRAME_POINTER FALSE
65
66/*
67 *  Some family members have no FP, some have an FPU such as the
68 *  MC68881/MC68882 for the MC68020, others have it built in (MC68030, 040).
69 *
70 *  NOTE:  If on a CPU without hardware FP, then one can use software
71 *         emulation.  The gcc software FP emulation code has data which
72 *         must be contexted switched on a per task basis.
73 */
74
75#if ( M68K_HAS_FPU == 1 ) || ( M68K_HAS_EMAC == 1 )
76  #define CPU_HARDWARE_FP TRUE
77  #define CPU_SOFTWARE_FP FALSE
78#else
79  #define CPU_HARDWARE_FP FALSE
80  #if defined( __GNUC__ )
81    #define CPU_SOFTWARE_FP TRUE
82  #else
83    #define CPU_SOFTWARE_FP FALSE
84  #endif
85#endif
86
87/*
88 *  All tasks are not by default floating point tasks on this CPU.
89 *  The IDLE task does not have a floating point context on this CPU.
90 *  It is safe to use the deferred floating point context switch
91 *  algorithm on this CPU.
92 */
93
94#define CPU_ALL_TASKS_ARE_FP             FALSE
95#define CPU_IDLE_TASK_IS_FP              FALSE
96#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
97#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
98
99#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
100#define CPU_STACK_GROWS_UP               FALSE
101
102/* FIXME: Is this the right value? */
103#define CPU_CACHE_LINE_BYTES 16
104
105#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
106
107#define CPU_MAXIMUM_PROCESSORS 32
108
109#if ( CPU_HARDWARE_FP == TRUE ) && !defined( __mcoldfire__ )
110  #if defined( __mc68060__ )
111    #define M68K_FP_STATE_SIZE 16
112  #else
113    #define M68K_FP_STATE_SIZE 216
114  #endif
115#endif
116
117#ifndef ASM
118
119/* structures */
120
121/*
122 *  Basic integer context for the m68k family.
123 */
124
125typedef struct {
126  uint32_t    sr;                /* (sr) status register */
127  uint32_t    d2;                /* (d2) data register 2 */
128  uint32_t    d3;                /* (d3) data register 3 */
129  uint32_t    d4;                /* (d4) data register 4 */
130  uint32_t    d5;                /* (d5) data register 5 */
131  uint32_t    d6;                /* (d6) data register 6 */
132  uint32_t    d7;                /* (d7) data register 7 */
133  void       *a2;                /* (a2) address register 2 */
134  void       *a3;                /* (a3) address register 3 */
135  void       *a4;                /* (a4) address register 4 */
136  void       *a5;                /* (a5) address register 5 */
137  void       *a6;                /* (a6) address register 6 */
138  void       *a7_msp;            /* (a7) master stack pointer */
139  #if defined( __mcoldfire__ ) && ( M68K_HAS_FPU == 1 )
140    uint8_t   fpu_dis;
141  #endif
142} Context_Control;
143
144#define _CPU_Context_Get_SP( _context ) \
145  (_context)->a7_msp
146
147/*
148 *  Floating point context areas and support routines
149 */
150
151#if ( CPU_SOFTWARE_FP == TRUE )
152  /*
153   *  This is the same as gcc's view of the software FP condition code
154   *  register _fpCCR.  The implementation of the emulation code is
155   *  in the gcc-VERSION/config/m68k directory.  This structure is
156   *  correct as of gcc 2.7.2.2.
157   */
158  typedef struct {
159    uint16_t _exception_bits;
160    uint16_t _trap_enable_bits;
161    uint16_t _sticky_bits;
162    uint16_t _rounding_mode;
163    uint16_t _format;
164    uint16_t _last_operation;
165    union {
166      float sf;
167      double df;
168    } _operand1;
169    union {
170      float sf;
171      double df;
172    } _operand2;
173  } Context_Control_fp;
174
175  #define _CPU_Context_Initialize_fp( _fp_area ) \
176     { \
177       Context_Control_fp *_fp; \
178       _fp = *(Context_Control_fp **)_fp_area; \
179       _fp->_exception_bits = 0; \
180       _fp->_trap_enable_bits = 0; \
181       _fp->_sticky_bits = 0; \
182       _fp->_rounding_mode = 0;  /* ROUND_TO_NEAREST */ \
183       _fp->_format = 0;         /* NIL */ \
184       _fp->_last_operation = 0; /* NOOP */ \
185       _fp->_operand1.df = 0; \
186       _fp->_operand2.df = 0; \
187     }
188#endif
189
190#if ( CPU_HARDWARE_FP == TRUE )
191  #if defined( __mcoldfire__ )
192    /* We need memset() to initialize the FP context */
193    #include <string.h>
194
195    #if ( M68K_HAS_FPU == 1 )
196      /*
197       * The Cache Control Register (CACR) has write-only access.  It is also
198       * used to enable and disable the FPU.  We need to maintain a copy of
199       * this register to allow per thread values.
200       */
201      extern uint32_t _CPU_cacr_shadow;
202    #endif
203
204    /* We assume that each ColdFire core with a FPU has also an EMAC unit */
205    typedef struct {
206      uint32_t emac_macsr;
207      uint32_t emac_acc0;
208      uint32_t emac_acc1;
209      uint32_t emac_acc2;
210      uint32_t emac_acc3;
211      uint32_t emac_accext01;
212      uint32_t emac_accext23;
213      uint32_t emac_mask;
214      #if ( M68K_HAS_FPU == 1 )
215        uint16_t fp_state_format;
216        uint16_t fp_state_fpcr;
217        double fp_state_op;
218        uint32_t fp_state_fpsr;
219
220        /*
221         * We need to save the FP Instruction Address Register (FPIAR), because
222         * a context switch can occur within a FP exception before the handler
223         * was able to save this register.
224         */
225        uint32_t fp_fpiar;
226
227        double fp_data [8];
228      #endif
229    } Context_Control_fp;
230
231    /*
232     * The reset value for all context relevant registers except the FP data
233     * registers is zero.  The reset value of the FP data register is NAN.  The
234     * restore of the reset FP state will reset the FP data registers, so the
235     * initial value of them can be arbitrary here.
236     */
237    #define _CPU_Context_Initialize_fp( _fp_area ) \
238      memset( *(_fp_area), 0, sizeof( Context_Control_fp ) )
239  #else
240    /*
241     *  FP context save area for the M68881/M68882 and 68060 numeric
242     *  coprocessors.
243     */
244    typedef struct {
245      /*
246       * M68K_FP_STATE_SIZE bytes for FSAVE/FRESTORE
247       * 96 bytes for FMOVEM FP0-7
248       * 12 bytes for FMOVEM CREGS
249       * 4 bytes for non-null flag
250       */
251      uint8_t fp_save_area [M68K_FP_STATE_SIZE + 112];
252    } Context_Control_fp;
253
254    /*
255     * The floating-point context is saved/restored via FSAVE/FRESTORE which
256     * use a growing down stack.  Initialize the stack and adjust the FP area
257     * pointer accordingly.
258     */
259    #define _CPU_Context_Initialize_fp( _fp_area ) \
260       { \
261         uint32_t *_fp_context = _Addresses_Add_offset( \
262           *(_fp_area), CPU_CONTEXT_FP_SIZE - 4); \
263         *(--(_fp_context)) = 0; \
264         *(_fp_area) = (void *)(_fp_context); \
265       }
266  #endif
267#endif
268
269/*
270 *  The following structures define the set of information saved
271 *  on the current stack by RTEMS upon receipt of each exc/interrupt.
272 *  These are not used by m68k handlers.
273 *  The exception frame is for rdbg.
274 */
275
276typedef struct {
277  uint32_t   vecnum; /* vector number */
278} CPU_Interrupt_frame;
279
280typedef struct {
281  uint32_t   vecnum; /* vector number */
282  uint32_t   sr; /* status register */
283  uint32_t   pc; /* program counter */
284  uint32_t   d0, d1, d2, d3, d4, d5, d6, d7;
285  uint32_t   a0, a1, a2, a3, a4, a5, a6, a7;
286} CPU_Exception_frame;
287
288/* variables */
289
290extern void*                     _VBR;
291
292#endif /* ASM */
293
294/* constants */
295
296/*
297 *  This defines the number of levels and the mask used to pick those
298 *  bits out of a thread mode.
299 */
300
301#define CPU_MODES_INTERRUPT_LEVEL  0x00000007 /* interrupt level in mode */
302#define CPU_MODES_INTERRUPT_MASK   0x00000007 /* interrupt level in mode */
303
304/*
305 *  context size area for floating point
306 */
307
308#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
309
310/*
311 *  extra stack required by the MPCI receive server thread
312 */
313
314#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
315
316/*
317 *  m68k family supports 256 distinct vectors.
318 */
319
320#define CPU_INTERRUPT_NUMBER_OF_VECTORS      256
321#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
322
323/*
324 *  This is defined if the port has a special way to report the ISR nesting
325 *  level.  Most ports maintain the variable _ISR_Nest_level.
326 */
327
328#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
329
330/*
331 *  Minimum size of a thread's stack.
332 */
333
334#define CPU_STACK_MINIMUM_SIZE           M68K_CPU_STACK_MINIMUM_SIZE
335
336/*
337 *  Maximum priority of a thread. Note based from 0 which is the idle task.
338 */
339#define CPU_PRIORITY_MAXIMUM             M68K_CPU_PRIORITY_MAXIMUM
340
341#define CPU_SIZEOF_POINTER 4
342
343/*
344 *  m68k is pretty tolerant of alignment.  Just put things on 4 byte boundaries.
345 */
346
347#define CPU_ALIGNMENT                    4
348#define CPU_HEAP_ALIGNMENT               CPU_ALIGNMENT
349#define CPU_PARTITION_ALIGNMENT          CPU_ALIGNMENT
350
351/*
352 *  On m68k thread stacks require no further alignment after allocation
353 *  from the Workspace.
354 */
355
356#define CPU_STACK_ALIGNMENT        0
357
358#ifndef ASM
359
360/* macros */
361
362/*
363 *  ISR handler macros
364 *
365 *  These macros perform the following functions:
366 *     + initialize the RTEMS vector table
367 *     + disable all maskable CPU interrupts
368 *     + restore previous interrupt level (enable)
369 *     + temporarily restore interrupts (flash)
370 *     + set a particular level
371 */
372
373#define _CPU_Initialize_vectors()
374
375#define _CPU_ISR_Disable( _level ) \
376  m68k_disable_interrupts( _level )
377
378#define _CPU_ISR_Enable( _level ) \
379  m68k_enable_interrupts( _level )
380
381#define _CPU_ISR_Flash( _level ) \
382  m68k_flash_interrupts( _level )
383
384RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
385{
386  return ( level & 0x0700 ) == 0;
387}
388
389#define _CPU_ISR_Set_level( _newlevel ) \
390   m68k_set_interrupt_level( _newlevel )
391
392uint32_t   _CPU_ISR_Get_level( void );
393
394/* end of ISR handler macros */
395
396/*
397 *  Context handler macros
398 *
399 *  These macros perform the following functions:
400 *     + initialize a context area
401 *     + restart the current thread
402 *     + calculate the initial pointer into a FP context area
403 *     + initialize an FP context area
404 */
405
406void _CPU_Context_Initialize(
407  Context_Control *the_context,
408  void *stack_area_begin,
409  size_t stack_area_size,
410  uint32_t new_level,
411  void (*entry_point)( void ),
412  bool is_fp,
413  void *tls_area
414);
415
416/* end of Context handler macros */
417
418/*
419 *  _CPU_Thread_Idle_body
420 *
421 *  This routine is the CPU dependent IDLE thread body.
422 *
423 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
424 *         is TRUE.
425 */
426
427void *_CPU_Thread_Idle_body( uintptr_t ignored );
428
429/*
430 *  Fatal Error manager macros
431 *
432 *  These macros perform the following functions:
433 *    + disable interrupts and halt the CPU
434 */
435
436#if ( defined(__mcoldfire__) )
437#define _CPU_Fatal_halt( _source, _error ) \
438  { __asm__ volatile( "move.w %%sr,%%d0\n\t" \
439                  "or.l %2,%%d0\n\t" \
440                  "move.w %%d0,%%sr\n\t" \
441                  "move.l %1,%%d0\n\t" \
442                  "move.l #0xDEADBEEF,%%d1\n\t" \
443                  "halt" \
444                  : "=g" (_error) \
445                  : "0" (_error), "d"(0x0700) \
446                  : "d0", "d1" ); \
447  }
448#else
449#define _CPU_Fatal_halt( _source, _error ) \
450  { __asm__ volatile( "movl  %0,%%d0; " \
451                  "orw   #0x0700,%%sr; " \
452                  "stop  #0x2700" : "=d" ((_error)) : "0" ((_error)) ); \
453  }
454#endif
455
456/* end of Fatal Error manager macros */
457
458/*
459 *  Bitfield handler macros
460 *
461 *  These macros perform the following functions:
462 *     + scan for the highest numbered (MSB) set in a 16 bit bitfield
463 *
464 *  NOTE:
465 *
466 *    It appears that on the M68020 bitfield are always 32 bits wide
467 *    when in a register.  This code forces the bitfield to be in
468 *    memory (it really always is anyway). This allows us to
469 *    have a real 16 bit wide bitfield which operates "correctly."
470 */
471
472#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
473
474#if ( M68K_HAS_BFFFO != 1 )
475/*
476 *  Lookup table for BFFFO simulation
477 */
478extern const unsigned char _CPU_m68k_BFFFO_table[256];
479#endif
480
481#if ( M68K_HAS_BFFFO == 1 )
482
483#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
484  __asm__ volatile( "bfffo (%1),#0,#16,%0" : "=d" (_output) : "a" (&_value));
485
486#elif ( __mcfisaaplus__ )
487  /* This is simplified by the fact that RTEMS never calls it with _value=0 */
488#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
489    __asm__ volatile ( \
490       "   swap     %0\n"        \
491       "   ff1.l    %0\n"        \
492       : "=d" ((_output))        \
493       : "0" ((_value))          \
494       : "cc" ) ;
495
496#else
497/* duplicates BFFFO results for 16 bits (i.e., 15-(_priority) in
498   _CPU_Priority_bits_index is not needed), handles the 0 case, and
499   does not molest _value -- jsg */
500#if ( defined(__mcoldfire__) )
501
502#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
503  { \
504    register int dumby; \
505    \
506    __asm__ volatile ( \
507       "   clr.l   %1\n"         \
508       "   move.w  %2,%1\n"      \
509       "   lsr.l   #8,%1\n"      \
510       "   beq.s   1f\n"         \
511       "   move.b  (%3,%1),%0\n" \
512       "   bra.s   0f\n"         \
513       "1: move.w  %2,%1\n"      \
514       "   move.b  (%3,%1),%0\n" \
515       "   addq.l  #8,%0\n"      \
516       "0: and.l   #0xff,%0\n"   \
517       : "=&d" ((_output)), "=&d" ((dumby))    \
518       : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \
519       : "cc" ) ; \
520  }
521#elif ( M68K_HAS_EXTB_L == 1 )
522#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
523  { \
524    register int dumby; \
525    \
526    __asm__ volatile ( "   move.w  %2,%1\n"        \
527       "   lsr.w   #8,%1\n"        \
528       "   beq.s   1f\n"           \
529       "   move.b  (%3,%1.w),%0\n" \
530       "   extb.l  %0\n"           \
531       "   bra.s   0f\n"           \
532       "1: moveq.l #8,%0\n"        \
533       "   add.b   (%3,%2.w),%0\n" \
534       "0:\n"                      \
535       : "=&d" ((_output)), "=&d" ((dumby)) \
536       : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \
537       : "cc" ) ; \
538  }
539#else
540#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
541  { \
542    register int dumby; \
543    \
544    __asm__ volatile ( "   move.w  %2,%1\n"        \
545       "   lsr.w   #8,%1\n"        \
546       "   beq.s   1f\n"           \
547       "   move.b  (%3,%1.w),%0\n" \
548       "   and.l   #0x000000ff,%0\n"\
549       "   bra.s   0f\n"           \
550       "1: moveq.l #8,%0\n"        \
551       "   add.b   (%3,%2.w),%0\n" \
552       "0:\n"                      \
553       : "=&d" ((_output)), "=&d" ((dumby)) \
554       : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \
555       : "cc" ) ; \
556  }
557#endif
558
559#endif
560
561/* end of Bitfield handler macros */
562
563/*
564 *  Priority handler macros
565 *
566 *  These macros perform the following functions:
567 *    + return a mask with the bit for this major/minor portion of
568 *      of thread priority set.
569 *    + translate the bit number returned by "Bitfield_find_first_bit"
570 *      into an index into the thread ready chain bit maps
571 */
572
573#define _CPU_Priority_Mask( _bit_number ) \
574  ( 0x8000 >> (_bit_number) )
575
576#define _CPU_Priority_bits_index( _priority ) \
577  (_priority)
578
579/* end of Priority handler macros */
580
581/* functions */
582
583/*
584 *  _CPU_Initialize
585 *
586 *  This routine performs CPU dependent initialization.
587 */
588
589void _CPU_Initialize(void);
590
591/*
592 *  _CPU_ISR_install_raw_handler
593 *
594 *  This routine installs a "raw" interrupt handler directly into the
595 *  processor's vector table.
596 */
597
598void _CPU_ISR_install_raw_handler(
599  uint32_t    vector,
600  proc_ptr    new_handler,
601  proc_ptr   *old_handler
602);
603
604/*
605 *  _CPU_ISR_install_vector
606 *
607 *  This routine installs an interrupt vector.
608 */
609
610void _CPU_ISR_install_vector(
611  uint32_t         vector,
612  proc_ptr         new_handler,
613  proc_ptr        *old_handler
614);
615
616/*
617 *  _CPU_Install_interrupt_stack
618 *
619 *  This routine installs the hardware interrupt stack pointer.
620 */
621
622void _CPU_Install_interrupt_stack( void );
623
624/*
625 *  _CPU_Context_switch
626 *
627 *  This routine switches from the run context to the heir context.
628 */
629
630void _CPU_Context_switch(
631  Context_Control  *run,
632  Context_Control  *heir
633);
634
635void _CPU_Context_Restart_self(
636  Context_Control  *the_context
637) RTEMS_NO_RETURN;
638
639/*
640 *  _CPU_Context_save_fp
641 *
642 *  This routine saves the floating point context passed to it.
643 */
644
645void _CPU_Context_save_fp(
646  Context_Control_fp **fp_context_ptr
647);
648
649/*
650 *  _CPU_Context_restore_fp
651 *
652 *  This routine restores the floating point context passed to it.
653 */
654
655void _CPU_Context_restore_fp(
656  Context_Control_fp **fp_context_ptr
657);
658
659static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
660{
661  /* TODO */
662}
663
664static inline void _CPU_Context_validate( uintptr_t pattern )
665{
666  while (1) {
667    /* TODO */
668  }
669}
670
671/**
672 *  This method prints the CPU exception frame.
673 *
674 *  @param[in] frame points to the frame to be printed
675 */
676void _CPU_Exception_frame_print(
677  const CPU_Exception_frame *frame
678);
679
680typedef uint32_t CPU_Counter_ticks;
681
682CPU_Counter_ticks _CPU_Counter_read( void );
683
684static inline CPU_Counter_ticks _CPU_Counter_difference(
685  CPU_Counter_ticks second,
686  CPU_Counter_ticks first
687)
688{
689  return second - first;
690}
691
692#if (M68K_HAS_FPSP_PACKAGE == 1)
693/*
694 *  Hooks for the Floating Point Support Package (FPSP) provided by Motorola
695 *
696 *  NOTES:
697 *
698 *  Motorola 68k family CPU's before the 68040 used a coprocessor
699 *  (68881 or 68882) to handle floating point.  The 68040 has internal
700 *  floating point support -- but *not* the complete support provided by
701 *  the 68881 or 68882.  The leftover functions are taken care of by the
702 *  M68040 Floating Point Support Package.  Quoting from the MC68040
703 *  Microprocessors User's Manual, Section 9, Floating-Point Unit (MC68040):
704 *
705 *    "When used with the M68040FPSP, the MC68040 FPU is fully
706 *    compliant with IEEE floating-point standards."
707 *
708 *  M68KFPSPInstallExceptionHandlers is in libcpu/m68k/MODEL/fpsp and
709 *  is invoked early in the application code to ensure that proper FP
710 *  behavior is installed.  This is not left to the BSP to call, since
711 *  this would force all applications using that BSP to use FPSP which
712 *  is not necessarily desirable.
713 *
714 *  There is a similar package for the 68060 but RTEMS does not yet
715 *  support the 68060.
716 */
717
718void M68KFPSPInstallExceptionHandlers (void);
719
720extern int (*_FPSP_install_raw_handler)(
721  uint32_t   vector,
722  proc_ptr new_handler,
723  proc_ptr *old_handler
724);
725
726#endif
727
728
729#endif
730
731#ifdef __cplusplus
732}
733#endif
734
735#endif
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