source: rtems/cpukit/score/cpu/m68k/include/rtems/score/cpu.h @ 27bbc05

Last change on this file since 27bbc05 was 27bbc05, checked in by Sebastian Huber <sebastian.huber@…>, on Aug 2, 2018 at 12:49:01 PM

score: Remove CPU_PARTITION_ALIGNMENT

Use the CPU_SIZEOF_POINTER alignment instead. The internal alignment
requirement is defined by the use of Chain_Node (consisting of two
pointers) to manage the free chain of partitions.

It seems that previously the condition

CPU_PARTITION_ALIGNMENT >= sizeof(Chain_Node)

was true on all CPU ports. Now, we need an additional check.

Update #3482.

  • Property mode set to 100644
File size: 18.2 KB
Line 
1/**
2 * @file
3 *
4 * @brief Motorola M68K CPU Dependent Source
5 *
6 * This include file contains information pertaining to the Motorola
7 * m68xxx processor family.
8 */
9
10/*
11 *  COPYRIGHT (c) 1989-2011.
12 *  On-Line Applications Research Corporation (OAR).
13 *
14 *  The license and distribution terms for this file may be
15 *  found in the file LICENSE in this distribution or at
16 *  http://www.rtems.org/license/LICENSE.
17 */
18
19#ifndef _RTEMS_SCORE_CPU_H
20#define _RTEMS_SCORE_CPU_H
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26#include <rtems/score/basedefs.h>
27#include <rtems/score/m68k.h>
28
29/* conditional compilation parameters */
30
31/*
32 *  Does the CPU follow the simple vectored interrupt model?
33 *
34 *  If TRUE, then RTEMS allocates the vector table it internally manages.
35 *  If FALSE, then the BSP is assumed to allocate and manage the vector
36 *  table
37 *
38 *  M68K Specific Information:
39 *
40 *  XXX document implementation including references if appropriate
41 */
42#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
43
44/*
45 *  Does the RTEMS invoke the user's ISR with the vector number and
46 *  a pointer to the saved interrupt frame (1) or just the vector
47 *  number (0)?
48 */
49
50#define CPU_ISR_PASSES_FRAME_POINTER FALSE
51
52/*
53 *  Some family members have no FP, some have an FPU such as the
54 *  MC68881/MC68882 for the MC68020, others have it built in (MC68030, 040).
55 *
56 *  NOTE:  If on a CPU without hardware FP, then one can use software
57 *         emulation.  The gcc software FP emulation code has data which
58 *         must be contexted switched on a per task basis.
59 */
60
61#if ( M68K_HAS_FPU == 1 ) || ( M68K_HAS_EMAC == 1 )
62  #define CPU_HARDWARE_FP TRUE
63  #define CPU_SOFTWARE_FP FALSE
64#else
65  #define CPU_HARDWARE_FP FALSE
66  #if defined( __GNUC__ )
67    #define CPU_SOFTWARE_FP TRUE
68  #else
69    #define CPU_SOFTWARE_FP FALSE
70  #endif
71#endif
72
73/*
74 *  All tasks are not by default floating point tasks on this CPU.
75 *  The IDLE task does not have a floating point context on this CPU.
76 *  It is safe to use the deferred floating point context switch
77 *  algorithm on this CPU.
78 */
79
80#define CPU_ALL_TASKS_ARE_FP             FALSE
81#define CPU_IDLE_TASK_IS_FP              FALSE
82#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
83#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
84
85#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
86#define CPU_STACK_GROWS_UP               FALSE
87
88/* FIXME: Is this the right value? */
89#define CPU_CACHE_LINE_BYTES 16
90
91#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
92
93#define CPU_MAXIMUM_PROCESSORS 32
94
95#if ( CPU_HARDWARE_FP == TRUE ) && !defined( __mcoldfire__ )
96  #if defined( __mc68060__ )
97    #define M68K_FP_STATE_SIZE 16
98  #else
99    #define M68K_FP_STATE_SIZE 216
100  #endif
101#endif
102
103#ifndef ASM
104
105/* structures */
106
107/*
108 *  Basic integer context for the m68k family.
109 */
110
111typedef struct {
112  uint32_t    sr;                /* (sr) status register */
113  uint32_t    d2;                /* (d2) data register 2 */
114  uint32_t    d3;                /* (d3) data register 3 */
115  uint32_t    d4;                /* (d4) data register 4 */
116  uint32_t    d5;                /* (d5) data register 5 */
117  uint32_t    d6;                /* (d6) data register 6 */
118  uint32_t    d7;                /* (d7) data register 7 */
119  void       *a2;                /* (a2) address register 2 */
120  void       *a3;                /* (a3) address register 3 */
121  void       *a4;                /* (a4) address register 4 */
122  void       *a5;                /* (a5) address register 5 */
123  void       *a6;                /* (a6) address register 6 */
124  void       *a7_msp;            /* (a7) master stack pointer */
125  #if defined( __mcoldfire__ ) && ( M68K_HAS_FPU == 1 )
126    uint8_t   fpu_dis;
127  #endif
128} Context_Control;
129
130#define _CPU_Context_Get_SP( _context ) \
131  (_context)->a7_msp
132
133/*
134 *  Floating point context areas and support routines
135 */
136
137#if ( CPU_SOFTWARE_FP == TRUE )
138  /*
139   *  This is the same as gcc's view of the software FP condition code
140   *  register _fpCCR.  The implementation of the emulation code is
141   *  in the gcc-VERSION/config/m68k directory.  This structure is
142   *  correct as of gcc 2.7.2.2.
143   */
144  typedef struct {
145    uint16_t _exception_bits;
146    uint16_t _trap_enable_bits;
147    uint16_t _sticky_bits;
148    uint16_t _rounding_mode;
149    uint16_t _format;
150    uint16_t _last_operation;
151    union {
152      float sf;
153      double df;
154    } _operand1;
155    union {
156      float sf;
157      double df;
158    } _operand2;
159  } Context_Control_fp;
160
161  #define _CPU_Context_Initialize_fp( _fp_area ) \
162     { \
163       Context_Control_fp *_fp; \
164       _fp = *(Context_Control_fp **)_fp_area; \
165       _fp->_exception_bits = 0; \
166       _fp->_trap_enable_bits = 0; \
167       _fp->_sticky_bits = 0; \
168       _fp->_rounding_mode = 0;  /* ROUND_TO_NEAREST */ \
169       _fp->_format = 0;         /* NIL */ \
170       _fp->_last_operation = 0; /* NOOP */ \
171       _fp->_operand1.df = 0; \
172       _fp->_operand2.df = 0; \
173     }
174#endif
175
176#if ( CPU_HARDWARE_FP == TRUE )
177  #if defined( __mcoldfire__ )
178    /* We need memset() to initialize the FP context */
179    #include <string.h>
180
181    #if ( M68K_HAS_FPU == 1 )
182      /*
183       * The Cache Control Register (CACR) has write-only access.  It is also
184       * used to enable and disable the FPU.  We need to maintain a copy of
185       * this register to allow per thread values.
186       */
187      extern uint32_t _CPU_cacr_shadow;
188    #endif
189
190    /* We assume that each ColdFire core with a FPU has also an EMAC unit */
191    typedef struct {
192      uint32_t emac_macsr;
193      uint32_t emac_acc0;
194      uint32_t emac_acc1;
195      uint32_t emac_acc2;
196      uint32_t emac_acc3;
197      uint32_t emac_accext01;
198      uint32_t emac_accext23;
199      uint32_t emac_mask;
200      #if ( M68K_HAS_FPU == 1 )
201        uint16_t fp_state_format;
202        uint16_t fp_state_fpcr;
203        double fp_state_op;
204        uint32_t fp_state_fpsr;
205
206        /*
207         * We need to save the FP Instruction Address Register (FPIAR), because
208         * a context switch can occur within a FP exception before the handler
209         * was able to save this register.
210         */
211        uint32_t fp_fpiar;
212
213        double fp_data [8];
214      #endif
215    } Context_Control_fp;
216
217    /*
218     * The reset value for all context relevant registers except the FP data
219     * registers is zero.  The reset value of the FP data register is NAN.  The
220     * restore of the reset FP state will reset the FP data registers, so the
221     * initial value of them can be arbitrary here.
222     */
223    #define _CPU_Context_Initialize_fp( _fp_area ) \
224      memset( *(_fp_area), 0, sizeof( Context_Control_fp ) )
225  #else
226    /*
227     *  FP context save area for the M68881/M68882 and 68060 numeric
228     *  coprocessors.
229     */
230    typedef struct {
231      /*
232       * M68K_FP_STATE_SIZE bytes for FSAVE/FRESTORE
233       * 96 bytes for FMOVEM FP0-7
234       * 12 bytes for FMOVEM CREGS
235       * 4 bytes for non-null flag
236       */
237      uint8_t fp_save_area [M68K_FP_STATE_SIZE + 112];
238    } Context_Control_fp;
239
240    /*
241     * The floating-point context is saved/restored via FSAVE/FRESTORE which
242     * use a growing down stack.  Initialize the stack and adjust the FP area
243     * pointer accordingly.
244     */
245    #define _CPU_Context_Initialize_fp( _fp_area ) \
246       { \
247         uint32_t *_fp_context = _Addresses_Add_offset( \
248           *(_fp_area), CPU_CONTEXT_FP_SIZE - 4); \
249         *(--(_fp_context)) = 0; \
250         *(_fp_area) = (void *)(_fp_context); \
251       }
252  #endif
253#endif
254
255/*
256 *  The following structures define the set of information saved
257 *  on the current stack by RTEMS upon receipt of each exc/interrupt.
258 *  These are not used by m68k handlers.
259 *  The exception frame is for rdbg.
260 */
261
262typedef struct {
263  uint32_t   vecnum; /* vector number */
264} CPU_Interrupt_frame;
265
266typedef struct {
267  uint32_t   vecnum; /* vector number */
268  uint32_t   sr; /* status register */
269  uint32_t   pc; /* program counter */
270  uint32_t   d0, d1, d2, d3, d4, d5, d6, d7;
271  uint32_t   a0, a1, a2, a3, a4, a5, a6, a7;
272} CPU_Exception_frame;
273
274/* variables */
275
276extern void*                     _VBR;
277
278#endif /* ASM */
279
280/* constants */
281
282/*
283 *  This defines the number of levels and the mask used to pick those
284 *  bits out of a thread mode.
285 */
286
287#define CPU_MODES_INTERRUPT_MASK   0x00000007 /* interrupt level in mode */
288
289/*
290 *  context size area for floating point
291 */
292
293#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
294
295/*
296 *  extra stack required by the MPCI receive server thread
297 */
298
299#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
300
301/*
302 *  m68k family supports 256 distinct vectors.
303 */
304
305#define CPU_INTERRUPT_NUMBER_OF_VECTORS      256
306#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
307
308/*
309 *  This is defined if the port has a special way to report the ISR nesting
310 *  level.  Most ports maintain the variable _ISR_Nest_level.
311 */
312
313#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
314
315/*
316 *  Minimum size of a thread's stack.
317 */
318
319#define CPU_STACK_MINIMUM_SIZE           M68K_CPU_STACK_MINIMUM_SIZE
320
321/*
322 *  Maximum priority of a thread. Note based from 0 which is the idle task.
323 */
324#define CPU_PRIORITY_MAXIMUM             M68K_CPU_PRIORITY_MAXIMUM
325
326#define CPU_SIZEOF_POINTER 4
327
328/*
329 *  m68k is pretty tolerant of alignment.  Just put things on 4 byte boundaries.
330 */
331
332#define CPU_ALIGNMENT                    4
333#define CPU_HEAP_ALIGNMENT               CPU_ALIGNMENT
334
335/*
336 *  On m68k thread stacks require no further alignment after allocation
337 *  from the Workspace.
338 */
339
340#define CPU_STACK_ALIGNMENT        0
341
342#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
343
344#ifndef ASM
345
346/* macros */
347
348/*
349 *  ISR handler macros
350 *
351 *  These macros perform the following functions:
352 *     + initialize the RTEMS vector table
353 *     + disable all maskable CPU interrupts
354 *     + restore previous interrupt level (enable)
355 *     + temporarily restore interrupts (flash)
356 *     + set a particular level
357 */
358
359#define _CPU_Initialize_vectors()
360
361#define _CPU_ISR_Disable( _level ) \
362  m68k_disable_interrupts( _level )
363
364#define _CPU_ISR_Enable( _level ) \
365  m68k_enable_interrupts( _level )
366
367#define _CPU_ISR_Flash( _level ) \
368  m68k_flash_interrupts( _level )
369
370RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
371{
372  return ( level & 0x0700 ) == 0;
373}
374
375#define _CPU_ISR_Set_level( _newlevel ) \
376   m68k_set_interrupt_level( _newlevel )
377
378uint32_t   _CPU_ISR_Get_level( void );
379
380/* end of ISR handler macros */
381
382/*
383 *  Context handler macros
384 *
385 *  These macros perform the following functions:
386 *     + initialize a context area
387 *     + restart the current thread
388 *     + calculate the initial pointer into a FP context area
389 *     + initialize an FP context area
390 */
391
392void _CPU_Context_Initialize(
393  Context_Control *the_context,
394  void *stack_area_begin,
395  size_t stack_area_size,
396  uint32_t new_level,
397  void (*entry_point)( void ),
398  bool is_fp,
399  void *tls_area
400);
401
402/* end of Context handler macros */
403
404/*
405 *  _CPU_Thread_Idle_body
406 *
407 *  This routine is the CPU dependent IDLE thread body.
408 *
409 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
410 *         is TRUE.
411 */
412
413void *_CPU_Thread_Idle_body( uintptr_t ignored );
414
415/*
416 *  Fatal Error manager macros
417 *
418 *  These macros perform the following functions:
419 *    + disable interrupts and halt the CPU
420 */
421
422#if ( defined(__mcoldfire__) )
423#define _CPU_Fatal_halt( _source, _error ) \
424  { __asm__ volatile( "move.w %%sr,%%d0\n\t" \
425                  "or.l %2,%%d0\n\t" \
426                  "move.w %%d0,%%sr\n\t" \
427                  "move.l %1,%%d0\n\t" \
428                  "move.l #0xDEADBEEF,%%d1\n\t" \
429                  "halt" \
430                  : "=g" (_error) \
431                  : "0" (_error), "d"(0x0700) \
432                  : "d0", "d1" ); \
433  }
434#else
435#define _CPU_Fatal_halt( _source, _error ) \
436  { __asm__ volatile( "movl  %0,%%d0; " \
437                  "orw   #0x0700,%%sr; " \
438                  "stop  #0x2700" : "=d" ((_error)) : "0" ((_error)) ); \
439  }
440#endif
441
442/* end of Fatal Error manager macros */
443
444/*
445 *  Bitfield handler macros
446 *
447 *  These macros perform the following functions:
448 *     + scan for the highest numbered (MSB) set in a 16 bit bitfield
449 *
450 *  NOTE:
451 *
452 *    It appears that on the M68020 bitfield are always 32 bits wide
453 *    when in a register.  This code forces the bitfield to be in
454 *    memory (it really always is anyway). This allows us to
455 *    have a real 16 bit wide bitfield which operates "correctly."
456 */
457
458#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
459
460#if ( M68K_HAS_BFFFO != 1 )
461/*
462 *  Lookup table for BFFFO simulation
463 */
464extern const unsigned char _CPU_m68k_BFFFO_table[256];
465#endif
466
467#if ( M68K_HAS_BFFFO == 1 )
468
469#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
470  __asm__ volatile( "bfffo (%1),#0,#16,%0" : "=d" (_output) : "a" (&_value));
471
472#elif ( __mcfisaaplus__ )
473  /* This is simplified by the fact that RTEMS never calls it with _value=0 */
474#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
475    __asm__ volatile ( \
476       "   swap     %0\n"        \
477       "   ff1.l    %0\n"        \
478       : "=d" ((_output))        \
479       : "0" ((_value))          \
480       : "cc" ) ;
481
482#else
483/* duplicates BFFFO results for 16 bits (i.e., 15-(_priority) in
484   _CPU_Priority_bits_index is not needed), handles the 0 case, and
485   does not molest _value -- jsg */
486#if ( defined(__mcoldfire__) )
487
488#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
489  { \
490    int dumby; \
491    \
492    __asm__ volatile ( \
493       "   clr.l   %1\n"         \
494       "   move.w  %2,%1\n"      \
495       "   lsr.l   #8,%1\n"      \
496       "   beq.s   1f\n"         \
497       "   move.b  (%3,%1),%0\n" \
498       "   bra.s   0f\n"         \
499       "1: move.w  %2,%1\n"      \
500       "   move.b  (%3,%1),%0\n" \
501       "   addq.l  #8,%0\n"      \
502       "0: and.l   #0xff,%0\n"   \
503       : "=&d" ((_output)), "=&d" ((dumby))    \
504       : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \
505       : "cc" ) ; \
506  }
507#elif ( M68K_HAS_EXTB_L == 1 )
508#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
509  { \
510    int dumby; \
511    \
512    __asm__ volatile ( "   move.w  %2,%1\n"        \
513       "   lsr.w   #8,%1\n"        \
514       "   beq.s   1f\n"           \
515       "   move.b  (%3,%1.w),%0\n" \
516       "   extb.l  %0\n"           \
517       "   bra.s   0f\n"           \
518       "1: moveq.l #8,%0\n"        \
519       "   add.b   (%3,%2.w),%0\n" \
520       "0:\n"                      \
521       : "=&d" ((_output)), "=&d" ((dumby)) \
522       : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \
523       : "cc" ) ; \
524  }
525#else
526#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
527  { \
528    int dumby; \
529    \
530    __asm__ volatile ( "   move.w  %2,%1\n"        \
531       "   lsr.w   #8,%1\n"        \
532       "   beq.s   1f\n"           \
533       "   move.b  (%3,%1.w),%0\n" \
534       "   and.l   #0x000000ff,%0\n"\
535       "   bra.s   0f\n"           \
536       "1: moveq.l #8,%0\n"        \
537       "   add.b   (%3,%2.w),%0\n" \
538       "0:\n"                      \
539       : "=&d" ((_output)), "=&d" ((dumby)) \
540       : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \
541       : "cc" ) ; \
542  }
543#endif
544
545#endif
546
547/* end of Bitfield handler macros */
548
549/*
550 *  Priority handler macros
551 *
552 *  These macros perform the following functions:
553 *    + return a mask with the bit for this major/minor portion of
554 *      of thread priority set.
555 *    + translate the bit number returned by "Bitfield_find_first_bit"
556 *      into an index into the thread ready chain bit maps
557 */
558
559#define _CPU_Priority_Mask( _bit_number ) \
560  ( 0x8000 >> (_bit_number) )
561
562#define _CPU_Priority_bits_index( _priority ) \
563  (_priority)
564
565/* end of Priority handler macros */
566
567/* functions */
568
569/*
570 *  _CPU_Initialize
571 *
572 *  This routine performs CPU dependent initialization.
573 */
574
575void _CPU_Initialize(void);
576
577/*
578 *  _CPU_ISR_install_raw_handler
579 *
580 *  This routine installs a "raw" interrupt handler directly into the
581 *  processor's vector table.
582 */
583
584void _CPU_ISR_install_raw_handler(
585  uint32_t    vector,
586  proc_ptr    new_handler,
587  proc_ptr   *old_handler
588);
589
590/*
591 *  _CPU_ISR_install_vector
592 *
593 *  This routine installs an interrupt vector.
594 */
595
596void _CPU_ISR_install_vector(
597  uint32_t         vector,
598  proc_ptr         new_handler,
599  proc_ptr        *old_handler
600);
601
602/*
603 *  _CPU_Context_switch
604 *
605 *  This routine switches from the run context to the heir context.
606 */
607
608void _CPU_Context_switch(
609  Context_Control  *run,
610  Context_Control  *heir
611);
612
613void _CPU_Context_Restart_self(
614  Context_Control  *the_context
615) RTEMS_NO_RETURN;
616
617/*
618 *  _CPU_Context_save_fp
619 *
620 *  This routine saves the floating point context passed to it.
621 */
622
623void _CPU_Context_save_fp(
624  Context_Control_fp **fp_context_ptr
625);
626
627/*
628 *  _CPU_Context_restore_fp
629 *
630 *  This routine restores the floating point context passed to it.
631 */
632
633void _CPU_Context_restore_fp(
634  Context_Control_fp **fp_context_ptr
635);
636
637/**
638 *  This method prints the CPU exception frame.
639 *
640 *  @param[in] frame points to the frame to be printed
641 */
642void _CPU_Exception_frame_print(
643  const CPU_Exception_frame *frame
644);
645
646typedef uint32_t CPU_Counter_ticks;
647
648uint32_t _CPU_Counter_frequency( void );
649
650CPU_Counter_ticks _CPU_Counter_read( void );
651
652static inline CPU_Counter_ticks _CPU_Counter_difference(
653  CPU_Counter_ticks second,
654  CPU_Counter_ticks first
655)
656{
657  return second - first;
658}
659
660#if (M68K_HAS_FPSP_PACKAGE == 1)
661/*
662 *  Hooks for the Floating Point Support Package (FPSP) provided by Motorola
663 *
664 *  NOTES:
665 *
666 *  Motorola 68k family CPU's before the 68040 used a coprocessor
667 *  (68881 or 68882) to handle floating point.  The 68040 has internal
668 *  floating point support -- but *not* the complete support provided by
669 *  the 68881 or 68882.  The leftover functions are taken care of by the
670 *  M68040 Floating Point Support Package.  Quoting from the MC68040
671 *  Microprocessors User's Manual, Section 9, Floating-Point Unit (MC68040):
672 *
673 *    "When used with the M68040FPSP, the MC68040 FPU is fully
674 *    compliant with IEEE floating-point standards."
675 *
676 *  M68KFPSPInstallExceptionHandlers is in libcpu/m68k/MODEL/fpsp and
677 *  is invoked early in the application code to ensure that proper FP
678 *  behavior is installed.  This is not left to the BSP to call, since
679 *  this would force all applications using that BSP to use FPSP which
680 *  is not necessarily desirable.
681 *
682 *  There is a similar package for the 68060 but RTEMS does not yet
683 *  support the 68060.
684 */
685
686void M68KFPSPInstallExceptionHandlers (void);
687
688extern int (*_FPSP_install_raw_handler)(
689  uint32_t   vector,
690  proc_ptr new_handler,
691  proc_ptr *old_handler
692);
693
694#endif
695
696/** Type that can store a 32-bit integer or a pointer. */
697typedef uintptr_t CPU_Uint32ptr;
698
699#endif
700
701#ifdef __cplusplus
702}
703#endif
704
705#endif
Note: See TracBrowser for help on using the repository browser.