[a911a77] | 1 | /** |
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[66fffc7] | 2 | * @file |
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| 3 | * |
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| 4 | * @brief Motorola M68K CPU Dependent Source |
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| 5 | * |
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| 6 | * This include file contains information pertaining to the Motorola |
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| 7 | * m68xxx processor family. |
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[a911a77] | 8 | */ |
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| 9 | |
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| 10 | /* |
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[186fee2] | 11 | * COPYRIGHT (c) 1989-2011. |
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[7908ba5b] | 12 | * On-Line Applications Research Corporation (OAR). |
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| 13 | * |
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| 14 | * The license and distribution terms for this file may be |
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| 15 | * found in the file LICENSE in this distribution or at |
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[c499856] | 16 | * http://www.rtems.org/license/LICENSE. |
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[7908ba5b] | 17 | */ |
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| 18 | |
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[7f70d1b7] | 19 | #ifndef _RTEMS_SCORE_CPU_H |
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| 20 | #define _RTEMS_SCORE_CPU_H |
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[7908ba5b] | 21 | |
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| 22 | #ifdef __cplusplus |
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| 23 | extern "C" { |
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| 24 | #endif |
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| 25 | |
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[8d96b46] | 26 | #include <rtems/score/basedefs.h> |
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[89b85e51] | 27 | #include <rtems/score/m68k.h> |
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[7908ba5b] | 28 | |
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| 29 | /* conditional compilation parameters */ |
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| 30 | |
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[2fd427c] | 31 | /* |
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| 32 | * Does the CPU follow the simple vectored interrupt model? |
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| 33 | * |
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| 34 | * If TRUE, then RTEMS allocates the vector table it internally manages. |
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| 35 | * If FALSE, then the BSP is assumed to allocate and manage the vector |
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| 36 | * table |
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| 37 | * |
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| 38 | * M68K Specific Information: |
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| 39 | * |
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| 40 | * XXX document implementation including references if appropriate |
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| 41 | */ |
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| 42 | #define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE |
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| 43 | |
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[7908ba5b] | 44 | /* |
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| 45 | * Does the RTEMS invoke the user's ISR with the vector number and |
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[5bb38e15] | 46 | * a pointer to the saved interrupt frame (1) or just the vector |
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[7908ba5b] | 47 | * number (0)? |
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| 48 | */ |
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| 49 | |
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[141e16d] | 50 | #define CPU_ISR_PASSES_FRAME_POINTER FALSE |
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[7908ba5b] | 51 | |
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| 52 | /* |
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| 53 | * Some family members have no FP, some have an FPU such as the |
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| 54 | * MC68881/MC68882 for the MC68020, others have it built in (MC68030, 040). |
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| 55 | * |
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| 56 | * NOTE: If on a CPU without hardware FP, then one can use software |
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| 57 | * emulation. The gcc software FP emulation code has data which |
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| 58 | * must be contexted switched on a per task basis. |
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| 59 | */ |
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| 60 | |
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[3b7e9bc] | 61 | #if ( M68K_HAS_FPU == 1 ) || ( M68K_HAS_EMAC == 1 ) |
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| 62 | #define CPU_HARDWARE_FP TRUE |
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| 63 | #define CPU_SOFTWARE_FP FALSE |
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[7908ba5b] | 64 | #else |
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[3b7e9bc] | 65 | #define CPU_HARDWARE_FP FALSE |
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| 66 | #if defined( __GNUC__ ) |
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| 67 | #define CPU_SOFTWARE_FP TRUE |
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| 68 | #else |
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| 69 | #define CPU_SOFTWARE_FP FALSE |
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| 70 | #endif |
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[7908ba5b] | 71 | #endif |
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| 72 | |
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| 73 | /* |
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| 74 | * All tasks are not by default floating point tasks on this CPU. |
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| 75 | * The IDLE task does not have a floating point context on this CPU. |
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| 76 | * It is safe to use the deferred floating point context switch |
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| 77 | * algorithm on this CPU. |
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| 78 | */ |
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| 79 | |
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| 80 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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| 81 | #define CPU_IDLE_TASK_IS_FP FALSE |
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| 82 | #define CPU_USE_DEFERRED_FP_SWITCH TRUE |
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[84e6f15] | 83 | #define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE |
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[7908ba5b] | 84 | |
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[8e0738e1] | 85 | #define CPU_PROVIDES_IDLE_THREAD_BODY TRUE |
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[7908ba5b] | 86 | #define CPU_STACK_GROWS_UP FALSE |
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[a8865f8] | 87 | |
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| 88 | /* FIXME: Is this the right value? */ |
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| 89 | #define CPU_CACHE_LINE_BYTES 16 |
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| 90 | |
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| 91 | #define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) |
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[7908ba5b] | 92 | |
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[decff899] | 93 | #define CPU_MAXIMUM_PROCESSORS 32 |
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| 94 | |
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[da42259] | 95 | #if ( CPU_HARDWARE_FP == TRUE ) && !defined( __mcoldfire__ ) |
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| 96 | #if defined( __mc68060__ ) |
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| 97 | #define M68K_FP_STATE_SIZE 16 |
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| 98 | #else |
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| 99 | #define M68K_FP_STATE_SIZE 216 |
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| 100 | #endif |
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| 101 | #endif |
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| 102 | |
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[7908ba5b] | 103 | #ifndef ASM |
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[3b7e9bc] | 104 | |
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[7908ba5b] | 105 | /* structures */ |
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| 106 | |
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| 107 | /* |
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| 108 | * Basic integer context for the m68k family. |
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| 109 | */ |
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| 110 | |
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| 111 | typedef struct { |
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[d86bae8] | 112 | uint32_t sr; /* (sr) status register */ |
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| 113 | uint32_t d2; /* (d2) data register 2 */ |
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| 114 | uint32_t d3; /* (d3) data register 3 */ |
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| 115 | uint32_t d4; /* (d4) data register 4 */ |
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| 116 | uint32_t d5; /* (d5) data register 5 */ |
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| 117 | uint32_t d6; /* (d6) data register 6 */ |
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| 118 | uint32_t d7; /* (d7) data register 7 */ |
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[7908ba5b] | 119 | void *a2; /* (a2) address register 2 */ |
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| 120 | void *a3; /* (a3) address register 3 */ |
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| 121 | void *a4; /* (a4) address register 4 */ |
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| 122 | void *a5; /* (a5) address register 5 */ |
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| 123 | void *a6; /* (a6) address register 6 */ |
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| 124 | void *a7_msp; /* (a7) master stack pointer */ |
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[3b7e9bc] | 125 | #if defined( __mcoldfire__ ) && ( M68K_HAS_FPU == 1 ) |
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| 126 | uint8_t fpu_dis; |
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| 127 | #endif |
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| 128 | } Context_Control; |
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[7908ba5b] | 129 | |
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[0ca6d0d9] | 130 | #define _CPU_Context_Get_SP( _context ) \ |
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| 131 | (_context)->a7_msp |
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| 132 | |
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[7908ba5b] | 133 | /* |
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[3b7e9bc] | 134 | * Floating point context areas and support routines |
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[7908ba5b] | 135 | */ |
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| 136 | |
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[3b7e9bc] | 137 | #if ( CPU_SOFTWARE_FP == TRUE ) |
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| 138 | /* |
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| 139 | * This is the same as gcc's view of the software FP condition code |
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| 140 | * register _fpCCR. The implementation of the emulation code is |
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| 141 | * in the gcc-VERSION/config/m68k directory. This structure is |
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| 142 | * correct as of gcc 2.7.2.2. |
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| 143 | */ |
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| 144 | typedef struct { |
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| 145 | uint16_t _exception_bits; |
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| 146 | uint16_t _trap_enable_bits; |
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| 147 | uint16_t _sticky_bits; |
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| 148 | uint16_t _rounding_mode; |
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| 149 | uint16_t _format; |
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| 150 | uint16_t _last_operation; |
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| 151 | union { |
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| 152 | float sf; |
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| 153 | double df; |
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| 154 | } _operand1; |
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| 155 | union { |
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| 156 | float sf; |
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| 157 | double df; |
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| 158 | } _operand2; |
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| 159 | } Context_Control_fp; |
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| 160 | |
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| 161 | #define _CPU_Context_Initialize_fp( _fp_area ) \ |
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| 162 | { \ |
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| 163 | Context_Control_fp *_fp; \ |
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| 164 | _fp = *(Context_Control_fp **)_fp_area; \ |
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| 165 | _fp->_exception_bits = 0; \ |
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| 166 | _fp->_trap_enable_bits = 0; \ |
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| 167 | _fp->_sticky_bits = 0; \ |
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| 168 | _fp->_rounding_mode = 0; /* ROUND_TO_NEAREST */ \ |
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| 169 | _fp->_format = 0; /* NIL */ \ |
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| 170 | _fp->_last_operation = 0; /* NOOP */ \ |
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| 171 | _fp->_operand1.df = 0; \ |
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| 172 | _fp->_operand2.df = 0; \ |
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| 173 | } |
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[e0b8176] | 174 | #endif |
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| 175 | |
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[3b7e9bc] | 176 | #if ( CPU_HARDWARE_FP == TRUE ) |
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| 177 | #if defined( __mcoldfire__ ) |
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| 178 | /* We need memset() to initialize the FP context */ |
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| 179 | #include <string.h> |
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| 180 | |
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| 181 | #if ( M68K_HAS_FPU == 1 ) |
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| 182 | /* |
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| 183 | * The Cache Control Register (CACR) has write-only access. It is also |
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| 184 | * used to enable and disable the FPU. We need to maintain a copy of |
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| 185 | * this register to allow per thread values. |
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| 186 | */ |
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| 187 | extern uint32_t _CPU_cacr_shadow; |
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| 188 | #endif |
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| 189 | |
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| 190 | /* We assume that each ColdFire core with a FPU has also an EMAC unit */ |
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| 191 | typedef struct { |
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| 192 | uint32_t emac_macsr; |
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| 193 | uint32_t emac_acc0; |
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| 194 | uint32_t emac_acc1; |
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| 195 | uint32_t emac_acc2; |
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| 196 | uint32_t emac_acc3; |
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| 197 | uint32_t emac_accext01; |
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| 198 | uint32_t emac_accext23; |
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| 199 | uint32_t emac_mask; |
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| 200 | #if ( M68K_HAS_FPU == 1 ) |
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| 201 | uint16_t fp_state_format; |
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| 202 | uint16_t fp_state_fpcr; |
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| 203 | double fp_state_op; |
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| 204 | uint32_t fp_state_fpsr; |
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| 205 | |
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| 206 | /* |
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| 207 | * We need to save the FP Instruction Address Register (FPIAR), because |
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| 208 | * a context switch can occur within a FP exception before the handler |
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| 209 | * was able to save this register. |
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| 210 | */ |
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| 211 | uint32_t fp_fpiar; |
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| 212 | |
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| 213 | double fp_data [8]; |
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| 214 | #endif |
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| 215 | } Context_Control_fp; |
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| 216 | |
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| 217 | /* |
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| 218 | * The reset value for all context relevant registers except the FP data |
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| 219 | * registers is zero. The reset value of the FP data register is NAN. The |
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| 220 | * restore of the reset FP state will reset the FP data registers, so the |
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| 221 | * initial value of them can be arbitrary here. |
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| 222 | */ |
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| 223 | #define _CPU_Context_Initialize_fp( _fp_area ) \ |
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| 224 | memset( *(_fp_area), 0, sizeof( Context_Control_fp ) ) |
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| 225 | #else |
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| 226 | /* |
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[4bcd8dc] | 227 | * FP context save area for the M68881/M68882 and 68060 numeric |
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| 228 | * coprocessors. |
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[3b7e9bc] | 229 | */ |
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| 230 | typedef struct { |
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| 231 | /* |
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| 232 | * M68K_FP_STATE_SIZE bytes for FSAVE/FRESTORE |
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| 233 | * 96 bytes for FMOVEM FP0-7 |
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| 234 | * 12 bytes for FMOVEM CREGS |
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| 235 | * 4 bytes for non-null flag |
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| 236 | */ |
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| 237 | uint8_t fp_save_area [M68K_FP_STATE_SIZE + 112]; |
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| 238 | } Context_Control_fp; |
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| 239 | |
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[27bfcd8] | 240 | /* |
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| 241 | * The floating-point context is saved/restored via FSAVE/FRESTORE which |
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| 242 | * use a growing down stack. Initialize the stack and adjust the FP area |
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| 243 | * pointer accordingly. |
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| 244 | */ |
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[3b7e9bc] | 245 | #define _CPU_Context_Initialize_fp( _fp_area ) \ |
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| 246 | { \ |
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[27bfcd8] | 247 | uint32_t *_fp_context = _Addresses_Add_offset( \ |
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| 248 | *(_fp_area), CPU_CONTEXT_FP_SIZE - 4); \ |
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[3b7e9bc] | 249 | *(--(_fp_context)) = 0; \ |
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| 250 | *(_fp_area) = (void *)(_fp_context); \ |
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| 251 | } |
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[da42259] | 252 | #endif |
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[7908ba5b] | 253 | #endif |
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| 254 | |
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| 255 | /* |
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[e090b7e] | 256 | * The following structures define the set of information saved |
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| 257 | * on the current stack by RTEMS upon receipt of each exc/interrupt. |
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| 258 | * These are not used by m68k handlers. |
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| 259 | * The exception frame is for rdbg. |
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[7908ba5b] | 260 | */ |
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| 261 | |
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| 262 | typedef struct { |
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[d86bae8] | 263 | uint32_t vecnum; /* vector number */ |
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[7908ba5b] | 264 | } CPU_Interrupt_frame; |
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| 265 | |
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[e090b7e] | 266 | typedef struct { |
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[d86bae8] | 267 | uint32_t vecnum; /* vector number */ |
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| 268 | uint32_t sr; /* status register */ |
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| 269 | uint32_t pc; /* program counter */ |
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| 270 | uint32_t d0, d1, d2, d3, d4, d5, d6, d7; |
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| 271 | uint32_t a0, a1, a2, a3, a4, a5, a6, a7; |
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[e090b7e] | 272 | } CPU_Exception_frame; |
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| 273 | |
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[7908ba5b] | 274 | /* variables */ |
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| 275 | |
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[5bb38e15] | 276 | extern void* _VBR; |
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[7908ba5b] | 277 | |
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| 278 | #endif /* ASM */ |
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| 279 | |
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| 280 | /* constants */ |
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| 281 | |
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| 282 | /* |
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| 283 | * This defines the number of levels and the mask used to pick those |
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| 284 | * bits out of a thread mode. |
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| 285 | */ |
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| 286 | |
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| 287 | #define CPU_MODES_INTERRUPT_MASK 0x00000007 /* interrupt level in mode */ |
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| 288 | |
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| 289 | /* |
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| 290 | * context size area for floating point |
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| 291 | */ |
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| 292 | |
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| 293 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
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| 294 | |
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| 295 | /* |
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| 296 | * extra stack required by the MPCI receive server thread |
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| 297 | */ |
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| 298 | |
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| 299 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 |
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| 300 | |
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| 301 | /* |
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| 302 | * m68k family supports 256 distinct vectors. |
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| 303 | */ |
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| 304 | |
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| 305 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 |
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| 306 | #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) |
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| 307 | |
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[4db30283] | 308 | /* |
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| 309 | * This is defined if the port has a special way to report the ISR nesting |
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| 310 | * level. Most ports maintain the variable _ISR_Nest_level. |
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| 311 | */ |
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| 312 | |
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| 313 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
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| 314 | |
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[7908ba5b] | 315 | /* |
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| 316 | * Minimum size of a thread's stack. |
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| 317 | */ |
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| 318 | |
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[e339d8b] | 319 | #define CPU_STACK_MINIMUM_SIZE M68K_CPU_STACK_MINIMUM_SIZE |
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| 320 | |
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| 321 | /* |
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| 322 | * Maximum priority of a thread. Note based from 0 which is the idle task. |
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| 323 | */ |
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| 324 | #define CPU_PRIORITY_MAXIMUM M68K_CPU_PRIORITY_MAXIMUM |
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[7908ba5b] | 325 | |
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[f1738ed] | 326 | #define CPU_SIZEOF_POINTER 4 |
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| 327 | |
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[7908ba5b] | 328 | /* |
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| 329 | * m68k is pretty tolerant of alignment. Just put things on 4 byte boundaries. |
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| 330 | */ |
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| 331 | |
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| 332 | #define CPU_ALIGNMENT 4 |
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| 333 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
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| 334 | |
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| 335 | /* |
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| 336 | * On m68k thread stacks require no further alignment after allocation |
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| 337 | * from the Workspace. |
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| 338 | */ |
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| 339 | |
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| 340 | #define CPU_STACK_ALIGNMENT 0 |
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| 341 | |
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[c8df844] | 342 | #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES |
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| 343 | |
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[7908ba5b] | 344 | #ifndef ASM |
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| 345 | |
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| 346 | /* macros */ |
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| 347 | |
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| 348 | /* |
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| 349 | * ISR handler macros |
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| 350 | * |
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| 351 | * These macros perform the following functions: |
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[fe7acdcf] | 352 | * + initialize the RTEMS vector table |
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[7908ba5b] | 353 | * + disable all maskable CPU interrupts |
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| 354 | * + restore previous interrupt level (enable) |
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| 355 | * + temporarily restore interrupts (flash) |
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| 356 | * + set a particular level |
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| 357 | */ |
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| 358 | |
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[fe7acdcf] | 359 | #define _CPU_Initialize_vectors() |
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| 360 | |
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[7908ba5b] | 361 | #define _CPU_ISR_Disable( _level ) \ |
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| 362 | m68k_disable_interrupts( _level ) |
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| 363 | |
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| 364 | #define _CPU_ISR_Enable( _level ) \ |
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| 365 | m68k_enable_interrupts( _level ) |
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| 366 | |
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| 367 | #define _CPU_ISR_Flash( _level ) \ |
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| 368 | m68k_flash_interrupts( _level ) |
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| 369 | |
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[408609f6] | 370 | RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) |
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| 371 | { |
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| 372 | return ( level & 0x0700 ) == 0; |
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| 373 | } |
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| 374 | |
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[7908ba5b] | 375 | #define _CPU_ISR_Set_level( _newlevel ) \ |
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| 376 | m68k_set_interrupt_level( _newlevel ) |
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| 377 | |
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[d86bae8] | 378 | uint32_t _CPU_ISR_Get_level( void ); |
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[7908ba5b] | 379 | |
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| 380 | /* end of ISR handler macros */ |
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| 381 | |
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| 382 | /* |
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| 383 | * Context handler macros |
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| 384 | * |
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| 385 | * These macros perform the following functions: |
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| 386 | * + initialize a context area |
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| 387 | * + restart the current thread |
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| 388 | * + calculate the initial pointer into a FP context area |
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| 389 | * + initialize an FP context area |
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| 390 | */ |
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| 391 | |
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[022851a] | 392 | void _CPU_Context_Initialize( |
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| 393 | Context_Control *the_context, |
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| 394 | void *stack_area_begin, |
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| 395 | size_t stack_area_size, |
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| 396 | uint32_t new_level, |
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| 397 | void (*entry_point)( void ), |
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| 398 | bool is_fp, |
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| 399 | void *tls_area |
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| 400 | ); |
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[7908ba5b] | 401 | |
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| 402 | /* end of Context handler macros */ |
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| 403 | |
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[8e0738e1] | 404 | /* |
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| 405 | * _CPU_Thread_Idle_body |
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| 406 | * |
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| 407 | * This routine is the CPU dependent IDLE thread body. |
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| 408 | * |
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| 409 | * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY |
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| 410 | * is TRUE. |
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| 411 | */ |
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| 412 | |
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[59b68bd] | 413 | void *_CPU_Thread_Idle_body( uintptr_t ignored ); |
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[8e0738e1] | 414 | |
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[7908ba5b] | 415 | /* |
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| 416 | * Fatal Error manager macros |
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| 417 | * |
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| 418 | * These macros perform the following functions: |
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| 419 | * + disable interrupts and halt the CPU |
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| 420 | */ |
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| 421 | |
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[97c73ed] | 422 | #if ( defined(__mcoldfire__) ) |
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[f82752a4] | 423 | #define _CPU_Fatal_halt( _source, _error ) \ |
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[0e900873] | 424 | { __asm__ volatile( "move.w %%sr,%%d0\n\t" \ |
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[7908ba5b] | 425 | "or.l %2,%%d0\n\t" \ |
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| 426 | "move.w %%d0,%%sr\n\t" \ |
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| 427 | "move.l %1,%%d0\n\t" \ |
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| 428 | "move.l #0xDEADBEEF,%%d1\n\t" \ |
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| 429 | "halt" \ |
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| 430 | : "=g" (_error) \ |
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| 431 | : "0" (_error), "d"(0x0700) \ |
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| 432 | : "d0", "d1" ); \ |
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| 433 | } |
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| 434 | #else |
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[f82752a4] | 435 | #define _CPU_Fatal_halt( _source, _error ) \ |
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[0e900873] | 436 | { __asm__ volatile( "movl %0,%%d0; " \ |
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[7908ba5b] | 437 | "orw #0x0700,%%sr; " \ |
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| 438 | "stop #0x2700" : "=d" ((_error)) : "0" ((_error)) ); \ |
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| 439 | } |
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| 440 | #endif |
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| 441 | |
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| 442 | /* end of Fatal Error manager macros */ |
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| 443 | |
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| 444 | /* |
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| 445 | * Bitfield handler macros |
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| 446 | * |
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| 447 | * These macros perform the following functions: |
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| 448 | * + scan for the highest numbered (MSB) set in a 16 bit bitfield |
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| 449 | * |
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| 450 | * NOTE: |
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| 451 | * |
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| 452 | * It appears that on the M68020 bitfield are always 32 bits wide |
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| 453 | * when in a register. This code forces the bitfield to be in |
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| 454 | * memory (it really always is anyway). This allows us to |
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| 455 | * have a real 16 bit wide bitfield which operates "correctly." |
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| 456 | */ |
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| 457 | |
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| 458 | #define CPU_USE_GENERIC_BITFIELD_CODE FALSE |
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| 459 | |
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[60a3fa0c] | 460 | #if ( M68K_HAS_BFFFO != 1 ) |
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| 461 | /* |
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| 462 | * Lookup table for BFFFO simulation |
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| 463 | */ |
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| 464 | extern const unsigned char _CPU_m68k_BFFFO_table[256]; |
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| 465 | #endif |
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| 466 | |
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[7908ba5b] | 467 | #if ( M68K_HAS_BFFFO == 1 ) |
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| 468 | |
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| 469 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
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[0e900873] | 470 | __asm__ volatile( "bfffo (%1),#0,#16,%0" : "=d" (_output) : "a" (&_value)); |
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[7908ba5b] | 471 | |
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[e339d8b] | 472 | #elif ( __mcfisaaplus__ ) |
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[fa9fa1e4] | 473 | /* This is simplified by the fact that RTEMS never calls it with _value=0 */ |
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| 474 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
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[0e900873] | 475 | __asm__ volatile ( \ |
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[fa9fa1e4] | 476 | " swap %0\n" \ |
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| 477 | " ff1.l %0\n" \ |
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| 478 | : "=d" ((_output)) \ |
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| 479 | : "0" ((_value)) \ |
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| 480 | : "cc" ) ; |
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| 481 | |
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| 482 | #else |
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[7908ba5b] | 483 | /* duplicates BFFFO results for 16 bits (i.e., 15-(_priority) in |
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| 484 | _CPU_Priority_bits_index is not needed), handles the 0 case, and |
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| 485 | does not molest _value -- jsg */ |
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[97c73ed] | 486 | #if ( defined(__mcoldfire__) ) |
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[60a3fa0c] | 487 | |
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[7908ba5b] | 488 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
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| 489 | { \ |
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[f35c3be9] | 490 | int dumby; \ |
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[7908ba5b] | 491 | \ |
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[0e900873] | 492 | __asm__ volatile ( \ |
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[7908ba5b] | 493 | " clr.l %1\n" \ |
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| 494 | " move.w %2,%1\n" \ |
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| 495 | " lsr.l #8,%1\n" \ |
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| 496 | " beq.s 1f\n" \ |
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| 497 | " move.b (%3,%1),%0\n" \ |
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| 498 | " bra.s 0f\n" \ |
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| 499 | "1: move.w %2,%1\n" \ |
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| 500 | " move.b (%3,%1),%0\n" \ |
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| 501 | " addq.l #8,%0\n" \ |
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| 502 | "0: and.l #0xff,%0\n" \ |
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| 503 | : "=&d" ((_output)), "=&d" ((dumby)) \ |
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[60a3fa0c] | 504 | : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \ |
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[7908ba5b] | 505 | : "cc" ) ; \ |
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| 506 | } |
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| 507 | #elif ( M68K_HAS_EXTB_L == 1 ) |
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| 508 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
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| 509 | { \ |
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[f35c3be9] | 510 | int dumby; \ |
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[7908ba5b] | 511 | \ |
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[0e900873] | 512 | __asm__ volatile ( " move.w %2,%1\n" \ |
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[7908ba5b] | 513 | " lsr.w #8,%1\n" \ |
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| 514 | " beq.s 1f\n" \ |
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| 515 | " move.b (%3,%1.w),%0\n" \ |
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| 516 | " extb.l %0\n" \ |
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| 517 | " bra.s 0f\n" \ |
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| 518 | "1: moveq.l #8,%0\n" \ |
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| 519 | " add.b (%3,%2.w),%0\n" \ |
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| 520 | "0:\n" \ |
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| 521 | : "=&d" ((_output)), "=&d" ((dumby)) \ |
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[60a3fa0c] | 522 | : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \ |
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[7908ba5b] | 523 | : "cc" ) ; \ |
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| 524 | } |
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| 525 | #else |
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| 526 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
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| 527 | { \ |
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[f35c3be9] | 528 | int dumby; \ |
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[7908ba5b] | 529 | \ |
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[0e900873] | 530 | __asm__ volatile ( " move.w %2,%1\n" \ |
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[7908ba5b] | 531 | " lsr.w #8,%1\n" \ |
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| 532 | " beq.s 1f\n" \ |
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| 533 | " move.b (%3,%1.w),%0\n" \ |
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| 534 | " and.l #0x000000ff,%0\n"\ |
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| 535 | " bra.s 0f\n" \ |
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| 536 | "1: moveq.l #8,%0\n" \ |
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| 537 | " add.b (%3,%2.w),%0\n" \ |
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| 538 | "0:\n" \ |
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| 539 | : "=&d" ((_output)), "=&d" ((dumby)) \ |
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[60a3fa0c] | 540 | : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \ |
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[7908ba5b] | 541 | : "cc" ) ; \ |
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| 542 | } |
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| 543 | #endif |
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| 544 | |
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| 545 | #endif |
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| 546 | |
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| 547 | /* end of Bitfield handler macros */ |
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| 548 | |
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| 549 | /* |
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| 550 | * Priority handler macros |
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| 551 | * |
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| 552 | * These macros perform the following functions: |
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| 553 | * + return a mask with the bit for this major/minor portion of |
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| 554 | * of thread priority set. |
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| 555 | * + translate the bit number returned by "Bitfield_find_first_bit" |
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| 556 | * into an index into the thread ready chain bit maps |
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| 557 | */ |
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| 558 | |
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| 559 | #define _CPU_Priority_Mask( _bit_number ) \ |
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| 560 | ( 0x8000 >> (_bit_number) ) |
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| 561 | |
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| 562 | #define _CPU_Priority_bits_index( _priority ) \ |
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| 563 | (_priority) |
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| 564 | |
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| 565 | /* end of Priority handler macros */ |
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| 566 | |
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| 567 | /* functions */ |
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| 568 | |
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| 569 | /* |
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| 570 | * _CPU_Initialize |
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| 571 | * |
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| 572 | * This routine performs CPU dependent initialization. |
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| 573 | */ |
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| 574 | |
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[c03e2bc] | 575 | void _CPU_Initialize(void); |
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[7908ba5b] | 576 | |
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| 577 | /* |
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| 578 | * _CPU_ISR_install_raw_handler |
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| 579 | * |
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[5bb38e15] | 580 | * This routine installs a "raw" interrupt handler directly into the |
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[7908ba5b] | 581 | * processor's vector table. |
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| 582 | */ |
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[5bb38e15] | 583 | |
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[7908ba5b] | 584 | void _CPU_ISR_install_raw_handler( |
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[d86bae8] | 585 | uint32_t vector, |
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[7908ba5b] | 586 | proc_ptr new_handler, |
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| 587 | proc_ptr *old_handler |
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| 588 | ); |
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| 589 | |
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| 590 | /* |
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| 591 | * _CPU_ISR_install_vector |
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| 592 | * |
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| 593 | * This routine installs an interrupt vector. |
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| 594 | */ |
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| 595 | |
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| 596 | void _CPU_ISR_install_vector( |
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[d86bae8] | 597 | uint32_t vector, |
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[7908ba5b] | 598 | proc_ptr new_handler, |
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| 599 | proc_ptr *old_handler |
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| 600 | ); |
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| 601 | |
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| 602 | /* |
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| 603 | * _CPU_Context_switch |
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| 604 | * |
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| 605 | * This routine switches from the run context to the heir context. |
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| 606 | */ |
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| 607 | |
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| 608 | void _CPU_Context_switch( |
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| 609 | Context_Control *run, |
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| 610 | Context_Control *heir |
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| 611 | ); |
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| 612 | |
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[4ad55267] | 613 | void _CPU_Context_Restart_self( |
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| 614 | Context_Control *the_context |
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[143696a] | 615 | ) RTEMS_NO_RETURN; |
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[4ad55267] | 616 | |
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[7908ba5b] | 617 | /* |
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| 618 | * _CPU_Context_save_fp |
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| 619 | * |
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| 620 | * This routine saves the floating point context passed to it. |
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| 621 | */ |
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| 622 | |
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| 623 | void _CPU_Context_save_fp( |
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[14865ec7] | 624 | Context_Control_fp **fp_context_ptr |
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[7908ba5b] | 625 | ); |
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| 626 | |
---|
| 627 | /* |
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| 628 | * _CPU_Context_restore_fp |
---|
| 629 | * |
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| 630 | * This routine restores the floating point context passed to it. |
---|
| 631 | */ |
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| 632 | |
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| 633 | void _CPU_Context_restore_fp( |
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[14865ec7] | 634 | Context_Control_fp **fp_context_ptr |
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[7908ba5b] | 635 | ); |
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| 636 | |
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[4bcd8dc] | 637 | /** |
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| 638 | * This method prints the CPU exception frame. |
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| 639 | * |
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| 640 | * @param[in] frame points to the frame to be printed |
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| 641 | */ |
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| 642 | void _CPU_Exception_frame_print( |
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| 643 | const CPU_Exception_frame *frame |
---|
| 644 | ); |
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[815994f] | 645 | |
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[24bf11e] | 646 | typedef uint32_t CPU_Counter_ticks; |
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| 647 | |
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[65f868c] | 648 | uint32_t _CPU_Counter_frequency( void ); |
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| 649 | |
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[24bf11e] | 650 | CPU_Counter_ticks _CPU_Counter_read( void ); |
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| 651 | |
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| 652 | static inline CPU_Counter_ticks _CPU_Counter_difference( |
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| 653 | CPU_Counter_ticks second, |
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| 654 | CPU_Counter_ticks first |
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| 655 | ) |
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| 656 | { |
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| 657 | return second - first; |
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| 658 | } |
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| 659 | |
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[7908ba5b] | 660 | #if (M68K_HAS_FPSP_PACKAGE == 1) |
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| 661 | /* |
---|
| 662 | * Hooks for the Floating Point Support Package (FPSP) provided by Motorola |
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| 663 | * |
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[5bb38e15] | 664 | * NOTES: |
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[7908ba5b] | 665 | * |
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| 666 | * Motorola 68k family CPU's before the 68040 used a coprocessor |
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| 667 | * (68881 or 68882) to handle floating point. The 68040 has internal |
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| 668 | * floating point support -- but *not* the complete support provided by |
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| 669 | * the 68881 or 68882. The leftover functions are taken care of by the |
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| 670 | * M68040 Floating Point Support Package. Quoting from the MC68040 |
---|
| 671 | * Microprocessors User's Manual, Section 9, Floating-Point Unit (MC68040): |
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| 672 | * |
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| 673 | * "When used with the M68040FPSP, the MC68040 FPU is fully |
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| 674 | * compliant with IEEE floating-point standards." |
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| 675 | * |
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| 676 | * M68KFPSPInstallExceptionHandlers is in libcpu/m68k/MODEL/fpsp and |
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[ece004d] | 677 | * is invoked early in the application code to ensure that proper FP |
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[7908ba5b] | 678 | * behavior is installed. This is not left to the BSP to call, since |
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| 679 | * this would force all applications using that BSP to use FPSP which |
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| 680 | * is not necessarily desirable. |
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| 681 | * |
---|
| 682 | * There is a similar package for the 68060 but RTEMS does not yet |
---|
| 683 | * support the 68060. |
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| 684 | */ |
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| 685 | |
---|
| 686 | void M68KFPSPInstallExceptionHandlers (void); |
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| 687 | |
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[18a5db2] | 688 | extern int (*_FPSP_install_raw_handler)( |
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[d86bae8] | 689 | uint32_t vector, |
---|
[7908ba5b] | 690 | proc_ptr new_handler, |
---|
| 691 | proc_ptr *old_handler |
---|
| 692 | ); |
---|
| 693 | |
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| 694 | #endif |
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| 695 | |
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[8d96b46] | 696 | /** Type that can store a 32-bit integer or a pointer. */ |
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| 697 | typedef uintptr_t CPU_Uint32ptr; |
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[7908ba5b] | 698 | |
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| 699 | #endif |
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| 700 | |
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| 701 | #ifdef __cplusplus |
---|
| 702 | } |
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| 703 | #endif |
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| 704 | |
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| 705 | #endif |
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