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source: rtems/cpukit/score/cpu/m68k/include/rtems/m68k/m68360.h

Last change on this file was 628bd9b, checked in by Joel Sherrill <joel@…>, on 03/22/22 at 19:40:34
cpukit/: Update Eric Norum contact info and normalize file headers
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1	/**
2	* @file
3	*
4	* @brief Definitions for Motorola MC68360 Processor
5	*
6	* Motorola MC68360 Quad Integrated Communications Controller (QUICC)
7	*/
8
9	/*
10	* Copyright (c) 1996 Eric Norum <eric@norum.ca>
11	*
12	* Redistribution and use in source and binary forms, with or without
13	* modification, are permitted provided that the following conditions
14	* are met:
15	* 1. Redistributions of source code must retain the above copyright
16	* notice, this list of conditions and the following disclaimer.
17	* 2. Redistributions in binary form must reproduce the above copyright
18	* notice, this list of conditions and the following disclaimer in the
19	* documentation and/or other materials provided with the distribution.
20	*
21	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24	* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25	* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30	* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31	* POSSIBILITY OF SUCH DAMAGE.
32	*/
33
34	#ifndef _RTEMS_M68K_M68360_H
35	#define _RTEMS_M68K_M68360_H
36
37	/*
38	*************************************************************************
39	* REGISTER SUBBLOCKS *
40	*************************************************************************
41	*/
42
43	/*
44	* Memory controller registers
45	*/
46	typedef struct m360MEMCRegisters_ {
47	unsigned long br;
48	unsigned long or;
49	unsigned long _pad[2];
50	} m360MEMCRegisters_t;
51
52	/*
53	* Serial Communications Controller registers
54	*/
55	typedef struct m360SCCRegisters_ {
56	unsigned long gsmr_l;
57	unsigned long gsmr_h;
58	unsigned short psmr;
59	unsigned short _pad0;
60	unsigned short todr;
61	unsigned short dsr;
62	unsigned short scce;
63	unsigned short _pad1;
64	unsigned short sccm;
65	unsigned char _pad2;
66	unsigned char sccs;
67	unsigned long _pad3[2];
68	} m360SCCRegisters_t;
69
70	/*
71	* Serial Management Controller registers
72	*/
73	typedef struct m360SMCRegisters_ {
74	unsigned short _pad0;
75	unsigned short smcmr;
76	unsigned short _pad1;
77	unsigned char smce;
78	unsigned char _pad2;
79	unsigned short _pad3;
80	unsigned char smcm;
81	unsigned char _pad4;
82	unsigned long _pad5;
83	} m360SMCRegisters_t;
84
85
86	/*
87	*************************************************************************
88	* Miscellaneous Parameters *
89	*************************************************************************
90	*/
91	typedef struct m360MiscParms_ {
92	unsigned short rev_num;
93	unsigned short _res1;
94	unsigned long _res2;
95	unsigned long _res3;
96	} m360MiscParms_t;
97
98	/*
99	*************************************************************************
100	* RISC Timers *
101	*************************************************************************
102	*/
103	typedef struct m360TimerParms_ {
104	unsigned short tm_base;
105	unsigned short _tm_ptr;
106	unsigned short _r_tmr;
107	unsigned short _r_tmv;
108	unsigned long tm_cmd;
109	unsigned long tm_cnt;
110	} m360TimerParms_t;
111
112	/*
113	* RISC Controller Configuration Register (RCCR)
114	* All other bits in this register are either reserved or
115	* used only with a Motorola-supplied RAM microcode packge.
116	*/
117	#define M360_RCCR_TIME (1<<15) /* Enable timer */
118	#define M360_RCCR_TIMEP(x) ((x)<<8) /* Timer period */
119
120	/*
121	* Command register
122	* Set up this register before issuing a M360_CR_OP_SET_TIMER command.
123	*/
124	#define M360_TM_CMD_V (1<<31) /* Set to enable timer */
125	#define M360_TM_CMD_R (1<<30) /* Set for automatic restart */
126	#define M360_TM_CMD_TIMER(x) ((x)<<16) /* Select timer */
127	#define M360_TM_CMD_PERIOD(x) (x) /* Timer period (16 bits) */
128
129	/*
130	*************************************************************************
131	* DMA Controllers *
132	*************************************************************************
133	*/
134	typedef struct m360IDMAparms_ {
135	unsigned short ibase;
136	unsigned short ibptr;
137	unsigned long _istate;
138	unsigned long _itemp;
139	} m360IDMAparms_t;
140
141	/*
142	*************************************************************************
143	* Serial Communication Controllers *
144	*************************************************************************
145	*/
146	typedef struct m360SCCparms_ {
147	unsigned short rbase;
148	unsigned short tbase;
149	unsigned char rfcr;
150	unsigned char tfcr;
151	unsigned short mrblr;
152	unsigned long _rstate;
153	unsigned long _pad0;
154	unsigned short _rbptr;
155	unsigned short _pad1;
156	unsigned long _pad2;
157	unsigned long _tstate;
158	unsigned long _pad3;
159	unsigned short _tbptr;
160	unsigned short _pad4;
161	unsigned long _pad5;
162	unsigned long _rcrc;
163	unsigned long _tcrc;
164	union {
165	struct {
166	unsigned long _res0;
167	unsigned long _res1;
168	unsigned short max_idl;
169	unsigned short _idlc;
170	unsigned short brkcr;
171	unsigned short parec;
172	unsigned short frmec;
173	unsigned short nosec;
174	unsigned short brkec;
175	unsigned short brklen;
176	unsigned short uaddr[2];
177	unsigned short _rtemp;
178	unsigned short toseq;
179	unsigned short character[8];
180	unsigned short rccm;
181	unsigned short rccr;
182	unsigned short rlbc;
183	} uart;
184	struct {
185	unsigned long crc_p;
186	unsigned long crc_c;
187	} transparent;
188
189	} un;
190	} m360SCCparms_t;
191
192	typedef struct m360SCCENparms_ {
193	unsigned short rbase;
194	unsigned short tbase;
195	unsigned char rfcr;
196	unsigned char tfcr;
197	unsigned short mrblr;
198	unsigned long _rstate;
199	unsigned long _pad0;
200	unsigned short _rbptr;
201	unsigned short _pad1;
202	unsigned long _pad2;
203	unsigned long _tstate;
204	unsigned long _pad3;
205	unsigned short _tbptr;
206	unsigned short _pad4;
207	unsigned long _pad5;
208	unsigned long _rcrc;
209	unsigned long _tcrc;
210	union {
211	struct {
212	unsigned long _res0;
213	unsigned long _res1;
214	unsigned short max_idl;
215	unsigned short _idlc;
216	unsigned short brkcr;
217	unsigned short parec;
218	unsigned short frmec;
219	unsigned short nosec;
220	unsigned short brkec;
221	unsigned short brklen;
222	unsigned short uaddr[2];
223	unsigned short _rtemp;
224	unsigned short toseq;
225	unsigned short character[8];
226	unsigned short rccm;
227	unsigned short rccr;
228	unsigned short rlbc;
229	} uart;
230	struct {
231	unsigned long c_pres;
232	unsigned long c_mask;
233	unsigned long crcec;
234	unsigned long alec;
235	unsigned long disfc;
236	unsigned short pads;
237	unsigned short ret_lim;
238	unsigned short _ret_cnt;
239	unsigned short mflr;
240	unsigned short minflr;
241	unsigned short maxd1;
242	unsigned short maxd2;
243	unsigned short _maxd;
244	unsigned short dma_cnt;
245	unsigned short _max_b;
246	unsigned short gaddr1;
247	unsigned short gaddr2;
248	unsigned short gaddr3;
249	unsigned short gaddr4;
250	unsigned long _tbuf0data0;
251	unsigned long _tbuf0data1;
252	unsigned long _tbuf0rba0;
253	unsigned long _tbuf0crc;
254	unsigned short _tbuf0bcnt;
255	unsigned short paddr_h;
256	unsigned short paddr_m;
257	unsigned short paddr_l;
258	unsigned short p_per;
259	unsigned short _rfbd_ptr;
260	unsigned short _tfbd_ptr;
261	unsigned short _tlbd_ptr;
262	unsigned long _tbuf1data0;
263	unsigned long _tbuf1data1;
264	unsigned long _tbuf1rba0;
265	unsigned long _tbuf1crc;
266	unsigned short _tbuf1bcnt;
267	unsigned short _tx_len;
268	unsigned short iaddr1;
269	unsigned short iaddr2;
270	unsigned short iaddr3;
271	unsigned short iaddr4;
272	unsigned short _boff_cnt;
273	unsigned short taddr_h;
274	unsigned short taddr_m;
275	unsigned short taddr_l;
276	} ethernet;
277	struct {
278	unsigned long crc_p;
279	unsigned long crc_c;
280	} transparent;
281	} un;
282	} m360SCCENparms_t;
283
284	/*
285	* Receive and transmit function code register bits
286	* These apply to the function code registers of all devices, not just SCC.
287	*/
288	#define M360_RFCR_MOT (1<<4)
289	#define M360_RFCR_DMA_SPACE 0x8
290	#define M360_TFCR_MOT (1<<4)
291	#define M360_TFCR_DMA_SPACE 0x8
292
293	/*
294	*************************************************************************
295	* Serial Management Controllers *
296	*************************************************************************
297	*/
298	typedef struct m360SMCparms_ {
299	unsigned short rbase;
300	unsigned short tbase;
301	unsigned char rfcr;
302	unsigned char tfcr;
303	unsigned short mrblr;
304	unsigned long _rstate;
305	unsigned long _pad0;
306	unsigned short _rbptr;
307	unsigned short _pad1;
308	unsigned long _pad2;
309	unsigned long _tstate;
310	unsigned long _pad3;
311	unsigned short _tbptr;
312	unsigned short _pad4;
313	unsigned long _pad5;
314	union {
315	struct {
316	unsigned short max_idl;
317	unsigned short _pad0;
318	unsigned short brklen;
319	unsigned short brkec;
320	unsigned short brkcr;
321	unsigned short _r_mask;
322	} uart;
323	struct {
324	unsigned short _pad0[5];
325	} transparent;
326	} un;
327	} m360SMCparms_t;
328
329	/*
330	* Mode register
331	*/
332	#define M360_SMCMR_CLEN(x) ((x)<<11) /* Character length */
333	#define M360_SMCMR_2STOP (1<<10) /* 2 stop bits */
334	#define M360_SMCMR_PARITY (1<<9) /* Enable parity */
335	#define M360_SMCMR_EVEN (1<<8) /* Even parity */
336	#define M360_SMCMR_SM_GCI (0<<4) /* GCI Mode */
337	#define M360_SMCMR_SM_UART (2<<4) /* UART Mode */
338	#define M360_SMCMR_SM_TRANSPARENT (3<<4) /* Transparent Mode */
339	#define M360_SMCMR_DM_LOOPBACK (1<<2) /* Local loopback mode */
340	#define M360_SMCMR_DM_ECHO (2<<2) /* Echo mode */
341	#define M360_SMCMR_TEN (1<<1) /* Enable transmitter */
342	#define M360_SMCMR_REN (1<<0) /* Enable receiver */
343
344	/*
345	* Event and mask registers (SMCE, SMCM)
346	*/
347	#define M360_SMCE_BRK (1<<4)
348	#define M360_SMCE_BSY (1<<2)
349	#define M360_SMCE_TX (1<<1)
350	#define M360_SMCE_RX (1<<0)
351
352	/*
353	*************************************************************************
354	* Serial Peripheral Interface *
355	*************************************************************************
356	*/
357	typedef struct m360SPIparms_ {
358	unsigned short rbase;
359	unsigned short tbase;
360	unsigned char rfcr;
361	unsigned char tfcr;
362	unsigned short mrblr;
363	unsigned long _rstate;
364	unsigned long _pad0;
365	unsigned short _rbptr;
366	unsigned short _pad1;
367	unsigned long _pad2;
368	unsigned long _tstate;
369	unsigned long _pad3;
370	unsigned short _tbptr;
371	unsigned short _pad4;
372	unsigned long _pad5;
373	} m360SPIparms_t;
374
375	/*
376	* Mode register (SPMODE)
377	*/
378	#define M360_SPMODE_LOOP (1<<14) /* Local loopback mode */
379	#define M360_SPMODE_CI (1<<13) /* Clock invert */
380	#define M360_SPMODE_CP (1<<12) /* Clock phase */
381	#define M360_SPMODE_DIV16 (1<<11) /* Divide BRGCLK by 16 */
382	#define M360_SPMODE_REV (1<<10) /* Reverse data */
383	#define M360_SPMODE_MASTER (1<<9) /* SPI is master */
384	#define M360_SPMODE_EN (1<<8) /* Enable SPI */
385	#define M360_SPMODE_CLEN(x) ((x)<<4) /* Character length */
386	#define M360_SPMODE_PM(x) (x) /* Prescaler modulus */
387
388	/*
389	* Mode register (SPCOM)
390	*/
391	#define M360_SPCOM_STR (1<<7) /* Start transmit */
392
393	/*
394	* Event and mask registers (SPIE, SPIM)
395	*/
396	#define M360_SPIE_MME (1<<5) /* Multi-master error */
397	#define M360_SPIE_TXE (1<<4) /* Tx error */
398	#define M360_SPIE_BSY (1<<2) /* Busy condition*/
399	#define M360_SPIE_TXB (1<<1) /* Tx buffer */
400	#define M360_SPIE_RXB (1<<0) /* Rx buffer */
401
402	/*
403	*************************************************************************
404	* SDMA (SCC, SMC, SPI) Buffer Descriptors *
405	*************************************************************************
406	*/
407	typedef struct m360BufferDescriptor_ {
408	unsigned short status;
409	unsigned short length;
410	volatile void *buffer;
411	} m360BufferDescriptor_t;
412
413	/*
414	* Bits in receive buffer descriptor status word
415	*/
416	#define M360_BD_EMPTY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
417	#define M360_BD_WRAP (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */
418	#define M360_BD_INTERRUPT (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */
419	#define M360_BD_LAST (1<<11) /* Ethernet, SPI */
420	#define M360_BD_CONTROL_CHAR (1<<11) /* SCC UART */
421	#define M360_BD_FIRST_IN_FRAME (1<<10) /* Ethernet */
422	#define M360_BD_ADDRESS (1<<10) /* SCC UART */
423	#define M360_BD_CONTINUOUS (1<<9) /* SCC UART, SMC UART, SPI */
424	#define M360_BD_MISS (1<<8) /* Ethernet */
425	#define M360_BD_IDLE (1<<8) /* SCC UART, SMC UART */
426	#define M360_BD_ADDRSS_MATCH (1<<7) /* SCC UART */
427	#define M360_BD_LONG (1<<5) /* Ethernet */
428	#define M360_BD_BREAK (1<<5) /* SCC UART, SMC UART */
429	#define M360_BD_NONALIGNED (1<<4) /* Ethernet */
430	#define M360_BD_FRAMING_ERROR (1<<4) /* SCC UART, SMC UART */
431	#define M360_BD_SHORT (1<<3) /* Ethernet */
432	#define M360_BD_PARITY_ERROR (1<<3) /* SCC UART, SMC UART */
433	#define M360_BD_CRC_ERROR (1<<2) /* Ethernet */
434	#define M360_BD_OVERRUN (1<<1) /* Ethernet, SCC UART, SMC UART, SPI */
435	#define M360_BD_COLLISION (1<<0) /* Ethernet */
436	#define M360_BD_CARRIER_LOST (1<<0) /* SCC UART */
437	#define M360_BD_MASTER_ERROR (1<<0) /* SPI */
438
439	/*
440	* Bits in transmit buffer descriptor status word
441	* Many bits have the same meaning as those in receiver buffer descriptors.
442	*/
443	#define M360_BD_READY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
444	#define M360_BD_PAD (1<<14) /* Ethernet */
445	#define M360_BD_CTS_REPORT (1<<11) /* SCC UART */
446	#define M360_BD_TX_CRC (1<<10) /* Ethernet */
447	#define M360_BD_DEFER (1<<9) /* Ethernet */
448	#define M360_BD_HEARTBEAT (1<<8) /* Ethernet */
449	#define M360_BD_PREAMBLE (1<<8) /* SCC UART, SMC UART */
450	#define M360_BD_LATE_COLLISION (1<<7) /* Ethernet */
451	#define M360_BD_NO_STOP_BIT (1<<7) /* SCC UART */
452	#define M360_BD_RETRY_LIMIT (1<<6) /* Ethernet */
453	#define M360_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) /* Ethernet */
454	#define M360_BD_UNDERRUN (1<<1) /* Ethernet, SPI */
455	#define M360_BD_CARRIER_LOST (1<<0) /* Ethernet */
456	#define M360_BD_CTS_LOST (1<<0) /* SCC UART */
457
458	/*
459	*************************************************************************
460	* IDMA Buffer Descriptors *
461	*************************************************************************
462	*/
463	typedef struct m360IDMABufferDescriptor_ {
464	unsigned short status;
465	unsigned short _pad;
466	unsigned long length;
467	void *source;
468	void *destination;
469	} m360IDMABufferDescriptor_t;
470
471	/*
472	*************************************************************************
473	* RISC Communication Processor Module Command Register (CR) *
474	*************************************************************************
475	*/
476	#define M360_CR_RST (1<<15) /* Reset communication processor */
477	#define M360_CR_OP_INIT_RX_TX (0<<8) /* SCC, SMC UART, SMC GCI, SPI */
478	#define M360_CR_OP_INIT_RX (1<<8) /* SCC, SMC UART, SPI */
479	#define M360_CR_OP_INIT_TX (2<<8) /* SCC, SMC UART, SPI */
480	#define M360_CR_OP_INIT_HUNT (3<<8) /* SCC, SMC UART */
481	#define M360_CR_OP_STOP_TX (4<<8) /* SCC, SMC UART */
482	#define M360_CR_OP_GR_STOP_TX (5<<8) /* SCC */
483	#define M360_CR_OP_INIT_IDMA (5<<8) /* IDMA */
484	#define M360_CR_OP_RESTART_TX (6<<8) /* SCC, SMC UART */
485	#define M360_CR_OP_CLOSE_RX_BD (7<<8) /* SCC, SMC UART, SPI */
486	#define M360_CR_OP_SET_GRP_ADDR (8<<8) /* SCC */
487	#define M360_CR_OP_SET_TIMER (8<<8) /* Timer */
488	#define M360_CR_OP_GCI_TIMEOUT (9<<8) /* SMC GCI */
489	#define M360_CR_OP_RESERT_BCS (10<<8) /* SCC */
490	#define M360_CR_OP_GCI_ABORT (10<<8) /* SMC GCI */
491	#define M360_CR_CHAN_SCC1 (0<<4) /* Channel selection */
492	#define M360_CR_CHAN_SCC2 (4<<4)
493	#define M360_CR_CHAN_SPI (5<<4)
494	#define M360_CR_CHAN_TIMER (5<<4)
495	#define M360_CR_CHAN_SCC3 (8<<4)
496	#define M360_CR_CHAN_SMC1 (9<<4)
497	#define M360_CR_CHAN_IDMA1 (9<<4)
498	#define M360_CR_CHAN_SCC4 (12<<4)
499	#define M360_CR_CHAN_SMC2 (13<<4)
500	#define M360_CR_CHAN_IDMA2 (13<<4)
501	#define M360_CR_FLG (1<<0) /* Command flag */
502
503	/*
504	*************************************************************************
505	* System Protection Control Register (SYPCR) *
506	*************************************************************************
507	*/
508	#define M360_SYPCR_SWE (1<<7) /* Software watchdog enable */
509	#define M360_SYPCR_SWRI (1<<6) /* Software watchdog reset select */
510	#define M360_SYPCR_SWT1 (1<<5) /* Software watchdog timing bit 1 */
511	#define M360_SYPCR_SWT0 (1<<4) /* Software watchdog timing bit 0 */
512	#define M360_SYPCR_DBFE (1<<3) /* Double bus fault monitor enable */
513	#define M360_SYPCR_BME (1<<2) /* Bus monitor external enable */
514	#define M360_SYPCR_BMT1 (1<<1) /* Bus monitor timing bit 1 */
515	#define M360_SYPCR_BMT0 (1<<0) /* Bus monitor timing bit 0 */
516
517	/*
518	*************************************************************************
519	* Memory Control Registers *
520	*************************************************************************
521	*/
522	#define M360_GMR_RCNT(x) ((x)<<24) /* Refresh count */
523	#define M360_GMR_RFEN (1<<23) /* Refresh enable */
524	#define M360_GMR_RCYC(x) ((x)<<21) /* Refresh cycle length */
525	#define M360_GMR_PGS(x) ((x)<<18) /* Page size */
526	#define M360_GMR_DPS_32BIT (0<<16) /* DRAM port size */
527	#define M360_GMR_DPS_16BIT (1<<16)
528	#define M360_GMR_DPS_8BIT (2<<16)
529	#define M360_GMR_DPS_DSACK (3<<16)
530	#define M360_GMR_WBT40 (1<<15) /* Wait between 040 transfers */
531	#define M360_GMR_WBTQ (1<<14) /* Wait between 360 transfers */
532	#define M360_GMR_SYNC (1<<13) /* Synchronous external access */
533	#define M360_GMR_EMWS (1<<12) /* External master wait state */
534	#define M360_GMR_OPAR (1<<11) /* Odd parity */
535	#define M360_GMR_PBEE (1<<10) /* Parity bus error enable */
536	#define M360_GMR_TSS40 (1<<9) /* TS* sample for 040 */
537	#define M360_GMR_NCS (1<<8) /* No CPU space */
538	#define M360_GMR_DWQ (1<<7) /* Delay write for 360 */
539	#define M360_GMR_DW40 (1<<6) /* Delay write for 040 */
540	#define M360_GMR_GAMX (1<<5) /* Global address mux enable */
541
542	#define M360_MEMC_BR_FC(x) ((x)<<7) /* Function code limit */
543	#define M360_MEMC_BR_TRLXQ (1<<6) /* Relax timing requirements */
544	#define M360_MEMC_BR_BACK40 (1<<5) /* Burst acknowledge to 040 */
545	#define M360_MEMC_BR_CSNT40 (1<<4) /* CS* negate timing for 040 */
546	#define M360_MEMC_BR_CSNTQ (1<<3) /* CS* negate timing for 360 */
547	#define M360_MEMC_BR_PAREN (1<<2) /* Enable parity checking */
548	#define M360_MEMC_BR_WP (1<<1) /* Write Protect */
549	#define M360_MEMC_BR_V (1<<0) /* Base/Option register are valid */
550
551	#define M360_MEMC_OR_TCYC(x) ((x)<<28) /* Cycle length (clocks) */
552	#define M360_MEMC_OR_WAITS(x) M360_MEMC_OR_TCYC((x)+1)
553	#define M360_MEMC_OR_2KB 0x0FFFF800 /* Address range */
554	#define M360_MEMC_OR_4KB 0x0FFFF000
555	#define M360_MEMC_OR_8KB 0x0FFFE000
556	#define M360_MEMC_OR_16KB 0x0FFFC000
557	#define M360_MEMC_OR_32KB 0x0FFF8000
558	#define M360_MEMC_OR_64KB 0x0FFF0000
559	#define M360_MEMC_OR_128KB 0x0FFE0000
560	#define M360_MEMC_OR_256KB 0x0FFC0000
561	#define M360_MEMC_OR_512KB 0x0FF80000
562	#define M360_MEMC_OR_1MB 0x0FF00000
563	#define M360_MEMC_OR_2MB 0x0FE00000
564	#define M360_MEMC_OR_4MB 0x0FC00000
565	#define M360_MEMC_OR_8MB 0x0F800000
566	#define M360_MEMC_OR_16MB 0x0F000000
567	#define M360_MEMC_OR_32MB 0x0E000000
568	#define M360_MEMC_OR_64MB 0x0C000000
569	#define M360_MEMC_OR_128MB 0x08000000
570	#define M360_MEMC_OR_256MB 0x00000000
571	#define M360_MEMC_OR_FCMC(x) ((x)<<7) /* Function code mask */
572	#define M360_MEMC_OR_BCYC(x) ((x)<<5) /* Burst cycle length (clocks) */
573	#define M360_MEMC_OR_PGME (1<<3) /* Page mode enable */
574	#define M360_MEMC_OR_32BIT (0<<1) /* Port size */
575	#define M360_MEMC_OR_16BIT (1<<1)
576	#define M360_MEMC_OR_8BIT (2<<1)
577	#define M360_MEMC_OR_DSACK (3<<1)
578	#define M360_MEMC_OR_DRAM (1<<0) /* Dynamic RAM select */
579
580	/*
581	*************************************************************************
582	* SI Mode Register (SIMODE) *
583	*************************************************************************
584	*/
585	#define M360_SI_SMC2_BITS 0xFFFF0000 /* All SMC2 bits */
586	#define M360_SI_SMC2_TDM (1<<31) /* Multiplexed SMC2 */
587	#define M360_SI_SMC2_BRG1 (0<<28) /* SMC2 clock souce */
588	#define M360_SI_SMC2_BRG2 (1<<28)
589	#define M360_SI_SMC2_BRG3 (2<<28)
590	#define M360_SI_SMC2_BRG4 (3<<28)
591	#define M360_SI_SMC2_CLK5 (0<<28)
592	#define M360_SI_SMC2_CLK6 (1<<28)
593	#define M360_SI_SMC2_CLK7 (2<<28)
594	#define M360_SI_SMC2_CLK8 (3<<28)
595	#define M360_SI_SMC1_BITS 0x0000FFFF /* All SMC1 bits */
596	#define M360_SI_SMC1_TDM (1<<15) /* Multiplexed SMC1 */
597	#define M360_SI_SMC1_BRG1 (0<<12) /* SMC1 clock souce */
598	#define M360_SI_SMC1_BRG2 (1<<12)
599	#define M360_SI_SMC1_BRG3 (2<<12)
600	#define M360_SI_SMC1_BRG4 (3<<12)
601	#define M360_SI_SMC1_CLK1 (0<<12)
602	#define M360_SI_SMC1_CLK2 (1<<12)
603	#define M360_SI_SMC1_CLK3 (2<<12)
604	#define M360_SI_SMC1_CLK4 (3<<12)
605
606	/*
607	*************************************************************************
608	* SDMA Configuration Register (SDMA) *
609	*************************************************************************
610	*/
611	#define M360_SDMA_FREEZE (2<<13) /* Freeze on next bus cycle */
612	#define M360_SDMA_SISM_7 (7<<8) /* Normal interrupt service mask */
613	#define M360_SDMA_SAID_4 (4<<4) /* Normal arbitration ID */
614	#define M360_SDMA_INTE (1<<1) /* SBER interrupt enable */
615	#define M360_SDMA_INTB (1<<0) /* SBKP interrupt enable */
616
617	/*
618	*************************************************************************
619	* Baud (sic) Rate Generators *
620	*************************************************************************
621	*/
622	#define M360_BRG_RST (1<<17) /* Reset generator */
623	#define M360_BRG_EN (1<<16) /* Enable generator */
624	#define M360_BRG_EXTC_BRGCLK (0<<14) /* Source is BRGCLK */
625	#define M360_BRG_EXTC_CLK2 (1<<14) /* Source is CLK2 pin */
626	#define M360_BRG_EXTC_CLK6 (2<<14) /* Source is CLK6 pin */
627	#define M360_BRG_ATB (1<<13) /* Autobaud */
628	#define M360_BRG_115200 (13<<1) /* Assume 25 MHz clock */
629	#define M360_BRG_57600 (26<<1)
630	#define M360_BRG_38400 (40<<1)
631	#define M360_BRG_19200 (80<<1)
632	#define M360_BRG_9600 (162<<1)
633	#define M360_BRG_4800 (324<<1)
634	#define M360_BRG_2400 (650<<1)
635	#define M360_BRG_1200 (1301<<1)
636	#define M360_BRG_600 (2603<<1)
637	#define M360_BRG_300 ((324<<1) \| 1)
638	#define M360_BRG_150 ((650<<1) \| 1)
639	#define M360_BRG_75 ((1301<<1) \| 1)
640
641	/*
642	*************************************************************************
643	* MC68360 DUAL-PORT RAM AND REGISTERS *
644	*************************************************************************
645	*/
646	typedef struct m360_ {
647	/*
648	* Dual-port RAM
649	*/
650	unsigned char dpram0[0x400]; /* Microcode program */
651	unsigned char dpram1[0x200];
652	unsigned char dpram2[0x100]; /* Microcode scratch */
653	unsigned char dpram3[0x100]; /* Not on REV A or B masks */
654	unsigned char _rsv0[0xC00-0x800];
655	m360SCCENparms_t scc1p;
656	unsigned char _rsv1[0xCB0-0xC00-sizeof(m360SCCENparms_t)];
657	m360MiscParms_t miscp;
658	unsigned char _rsv2[0xD00-0xCB0-sizeof(m360MiscParms_t)];
659	m360SCCparms_t scc2p;
660	unsigned char _rsv3[0xD80-0xD00-sizeof(m360SCCparms_t)];
661	m360SPIparms_t spip;
662	unsigned char _rsv4[0xDB0-0xD80-sizeof(m360SPIparms_t)];
663	m360TimerParms_t tmp;
664	unsigned char _rsv5[0xE00-0xDB0-sizeof(m360TimerParms_t)];
665	m360SCCparms_t scc3p;
666	unsigned char _rsv6[0xE70-0xE00-sizeof(m360SCCparms_t)];
667	m360IDMAparms_t idma1p;
668	unsigned char _rsv7[0xE80-0xE70-sizeof(m360IDMAparms_t)];
669	m360SMCparms_t smc1p;
670	unsigned char _rsv8[0xF00-0xE80-sizeof(m360SMCparms_t)];
671	m360SCCparms_t scc4p;
672	unsigned char _rsv9[0xF70-0xF00-sizeof(m360SCCparms_t)];
673	m360IDMAparms_t idma2p;
674	unsigned char _rsv10[0xF80-0xF70-sizeof(m360IDMAparms_t)];
675	m360SMCparms_t smc2p;
676	unsigned char _rsv11[0x1000-0xF80-sizeof(m360SMCparms_t)];
677
678	/*
679	* SIM Block
680	*/
681	unsigned long mcr;
682	unsigned long _pad00;
683	unsigned char avr;
684	unsigned char rsr;
685	unsigned short _pad01;
686	unsigned char clkocr;
687	unsigned char _pad02;
688	unsigned short _pad03;
689	unsigned short pllcr;
690	unsigned short _pad04;
691	unsigned short cdvcr;
692	unsigned short pepar;
693	unsigned long _pad05[2];
694	unsigned short _pad06;
695	unsigned char sypcr;
696	unsigned char swiv;
697	unsigned short _pad07;
698	unsigned short picr;
699	unsigned short _pad08;
700	unsigned short pitr;
701	unsigned short _pad09;
702	unsigned char _pad10;
703	unsigned char swsr;
704	unsigned long bkar;
705	unsigned long bcar;
706	unsigned long _pad11[2];
707
708	/*
709	* MEMC Block
710	*/
711	unsigned long gmr;
712	unsigned short mstat;
713	unsigned short _pad12;
714	unsigned long _pad13[2];
715	m360MEMCRegisters_t memc[8];
716	unsigned char _pad14[0xF0-0xD0];
717	unsigned char _pad15[0x100-0xF0];
718	unsigned char _pad16[0x500-0x100];
719
720	/*
721	* IDMA1 Block
722	*/
723	unsigned short iccr;
724	unsigned short _pad17;
725	unsigned short cmr1;
726	unsigned short _pad18;
727	unsigned long sapr1;
728	unsigned long dapr1;
729	unsigned long bcr1;
730	unsigned char fcr1;
731	unsigned char _pad19;
732	unsigned char cmar1;
733	unsigned char _pad20;
734	unsigned char csr1;
735	unsigned char _pad21;
736	unsigned short _pad22;
737
738	/*
739	* SDMA Block
740	*/
741	unsigned char sdsr;
742	unsigned char _pad23;
743	unsigned short sdcr;
744	unsigned long sdar;
745
746	/*
747	* IDMA2 Block
748	*/
749	unsigned short _pad24;
750	unsigned short cmr2;
751	unsigned long sapr2;
752	unsigned long dapr2;
753	unsigned long bcr2;
754	unsigned char fcr2;
755	unsigned char _pad26;
756	unsigned char cmar2;
757	unsigned char _pad27;
758	unsigned char csr2;
759	unsigned char _pad28;
760	unsigned short _pad29;
761	unsigned long _pad30;
762
763	/*
764	* CPIC Block
765	*/
766	unsigned long cicr;
767	unsigned long cipr;
768	unsigned long cimr;
769	unsigned long cisr;
770
771	/*
772	* Parallel I/O Block
773	*/
774	unsigned short padir;
775	unsigned short papar;
776	unsigned short paodr;
777	unsigned short padat;
778	unsigned long _pad31[2];
779	unsigned short pcdir;
780	unsigned short pcpar;
781	unsigned short pcso;
782	unsigned short pcdat;
783	unsigned short pcint;
784	unsigned short _pad32;
785	unsigned long _pad33[5];
786
787	/*
788	* TIMER Block
789	*/
790	unsigned short tgcr;
791	unsigned short _pad34;
792	unsigned long _pad35[3];
793	unsigned short tmr1;
794	unsigned short tmr2;
795	unsigned short trr1;
796	unsigned short trr2;
797	unsigned short tcr1;
798	unsigned short tcr2;
799	unsigned short tcn1;
800	unsigned short tcn2;
801	unsigned short tmr3;
802	unsigned short tmr4;
803	unsigned short trr3;
804	unsigned short trr4;
805	unsigned short tcr3;
806	unsigned short tcr4;
807	unsigned short tcn3;
808	unsigned short tcn4;
809	unsigned short ter1;
810	unsigned short ter2;
811	unsigned short ter3;
812	unsigned short ter4;
813	unsigned long _pad36[2];
814
815	/*
816	* CP Block
817	*/
818	unsigned short cr;
819	unsigned short _pad37;
820	unsigned short rccr;
821	unsigned short _pad38;
822	unsigned long _pad39[3];
823	unsigned short _pad40;
824	unsigned short rter;
825	unsigned short _pad41;
826	unsigned short rtmr;
827	unsigned long _pad42[5];
828
829	/*
830	* BRG Block
831	*/
832	unsigned long brgc1;
833	unsigned long brgc2;
834	unsigned long brgc3;
835	unsigned long brgc4;
836
837	/*
838	* SCC Block
839	*/
840	m360SCCRegisters_t scc1;
841	m360SCCRegisters_t scc2;
842	m360SCCRegisters_t scc3;
843	m360SCCRegisters_t scc4;
844
845	/*
846	* SMC Block
847	*/
848	m360SMCRegisters_t smc1;
849	m360SMCRegisters_t smc2;
850
851	/*
852	* SPI Block
853	*/
854	unsigned short spmode;
855	unsigned short _pad43[2];
856	unsigned char spie;
857	unsigned char _pad44;
858	unsigned short _pad45;
859	unsigned char spim;
860	unsigned char _pad46[2];
861	unsigned char spcom;
862	unsigned short _pad47[2];
863
864	/*
865	* PIP Block
866	*/
867	unsigned short pipc;
868	unsigned short _pad48;
869	unsigned short ptpr;
870	unsigned long pbdir;
871	unsigned long pbpar;
872	unsigned short _pad49;
873	unsigned short pbodr;
874	unsigned long pbdat;
875	unsigned long _pad50[6];
876
877	/*
878	* SI Block
879	*/
880	unsigned long simode;
881	unsigned char sigmr;
882	unsigned char _pad51;
883	unsigned char sistr;
884	unsigned char sicmr;
885	unsigned long _pad52;
886	unsigned long sicr;
887	unsigned short _pad53;
888	unsigned short sirp[2];
889	unsigned short _pad54;
890	unsigned long _pad55[2];
891	unsigned char siram[256];
892	} m360_t;
893
894	extern volatile m360_t m360;
895
896	/*
897	* definitions for the port b SPI pin bits
898	*/
899	#define M360_PB_SPI_MISO_MSK (1<< 3)
900	#define M360_PB_SPI_MOSI_MSK (1<< 2)
901	#define M360_PB_SPI_CLK_MSK (1<< 1)
902
903	#endif /* _RTEMS_M68K_M68360_H */

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