1 | /* cpu_asm.s |
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2 | * |
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3 | * This file contains all assembly code for the MC68020 implementation |
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4 | * of RTEMS. |
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5 | * |
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6 | * COPYRIGHT (c) 1989-2001. |
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7 | * On-Line Applications Research Corporation (OAR). |
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8 | * |
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9 | * The license and distribution terms for this file may be |
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10 | * found in the file LICENSE in this distribution or at |
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11 | * http://www.rtems.com/license/LICENSE. |
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12 | * |
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13 | * $Id$ |
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14 | */ |
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15 | |
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16 | |
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17 | #include <rtems/asm.h> |
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18 | |
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19 | .text |
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20 | |
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21 | /* void _CPU_Context_switch( run_context, heir_context ) |
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22 | * |
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23 | * This routine performs a normal non-FP context. |
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24 | */ |
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25 | |
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26 | .align 4 |
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27 | .global SYM (_CPU_Context_switch) |
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28 | |
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29 | .set RUNCONTEXT_ARG, 4 | save context argument |
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30 | .set HEIRCONTEXT_ARG, 8 | restore context argument |
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31 | |
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32 | SYM (_CPU_Context_switch): |
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33 | moval a7@(RUNCONTEXT_ARG),a0| a0 = running thread context |
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34 | movw sr,d1 | d1 = status register |
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35 | movml d1-d7/a2-a7,a0@ | save context |
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36 | |
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37 | moval a7@(HEIRCONTEXT_ARG),a0| a0 = heir thread context |
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38 | restore: movml a0@,d1-d7/a2-a7 | restore context |
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39 | movw d1,sr | restore status register |
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40 | rts |
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41 | |
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42 | /*PAGE |
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43 | * void __CPU_Context_save_fp_context( &fp_context_ptr ) |
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44 | * void __CPU_Context_restore_fp_context( &fp_context_ptr ) |
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45 | * |
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46 | * These routines are used to context switch a MC68881 or MC68882. |
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47 | * |
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48 | * NOTE: Context save and restore code is based upon the code shown |
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49 | * on page 6-38 of the MC68881/68882 Users Manual (rev 1). |
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50 | * |
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51 | * CPU_FP_CONTEXT_SIZE is higher than expected to account for the |
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52 | * -1 pushed at end of this sequence. |
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53 | * |
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54 | * Neither of these entries is required if we have software FPU |
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55 | * emulation. But if we don't have an FPU or emulation, then |
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56 | * we need the stub versions of these routines. |
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57 | */ |
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58 | |
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59 | #if (CPU_SOFTWARE_FP == FALSE) |
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60 | |
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61 | .set FPCONTEXT_ARG, 4 | save FP context argument |
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62 | |
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63 | .align 4 |
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64 | .global SYM (_CPU_Context_save_fp) |
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65 | SYM (_CPU_Context_save_fp): |
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66 | #if ( M68K_HAS_FPU == 1 ) |
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67 | moval a7@(FPCONTEXT_ARG),a1 | a1 = &ptr to context area |
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68 | moval a1@,a0 | a0 = Save context area |
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69 | fsave a0@- | save 68881/68882 state frame |
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70 | tstb a0@ | check for a null frame |
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71 | beq.b nosv | Yes, skip save of user model |
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72 | fmovem fp0-fp7,a0@- | save data registers (fp0-fp7) |
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73 | fmovem fpc/fps/fpi,a0@- | and save control registers |
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74 | movl #-1,a0@- | place not-null flag on stack |
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75 | nosv: movl a0,a1@ | save pointer to saved context |
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76 | #endif |
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77 | rts |
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78 | |
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79 | .align 4 |
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80 | .global SYM (_CPU_Context_restore_fp) |
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81 | SYM (_CPU_Context_restore_fp): |
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82 | #if ( M68K_HAS_FPU == 1 ) |
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83 | moval a7@(FPCONTEXT_ARG),a1 | a1 = &ptr to context area |
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84 | moval a1@,a0 | a0 = address of saved context |
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85 | tstb a0@ | Null context frame? |
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86 | beq.b norst | Yes, skip fp restore |
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87 | addql #4,a0 | throwaway non-null flag |
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88 | fmovem a0@+,fpc/fps/fpi | restore control registers |
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89 | fmovem a0@+,fp0-fp7 | restore data regs (fp0-fp7) |
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90 | norst: frestore a0@+ | restore the fp state frame |
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91 | movl a0,a1@ | save pointer to saved context |
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92 | #endif |
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93 | rts |
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94 | #endif |
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95 | |
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96 | /*PAGE |
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97 | * void _ISR_Handler() |
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98 | * |
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99 | * This routine provides the RTEMS interrupt management. |
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100 | * |
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101 | * NOTE: |
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102 | * Upon entry, the master stack will contain an interrupt stack frame |
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103 | * back to the interrupted thread and the interrupt stack will contain |
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104 | * a throwaway interrupt stack frame. If dispatching is enabled, and this |
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105 | * is the outer most interrupt, and a context switch is necessary or |
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106 | * the current thread has pending signals, then set up the master stack to |
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107 | * transfer control to the interrupt dispatcher. |
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108 | */ |
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109 | |
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110 | #if ( M68K_COLDFIRE_ARCH == 1 ) |
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111 | .set SR_OFFSET, 2 | Status register offset |
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112 | .set PC_OFFSET, 4 | Program Counter offset |
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113 | .set FVO_OFFSET, 0 | Format/vector offset |
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114 | #elif ( M68K_HAS_VBR == 1) |
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115 | .set SR_OFFSET, 0 | Status register offset |
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116 | .set PC_OFFSET, 2 | Program Counter offset |
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117 | .set FVO_OFFSET, 6 | Format/vector offset |
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118 | #else |
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119 | .set SR_OFFSET, 2 | Status register offset |
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120 | .set PC_OFFSET, 4 | Program Counter offset |
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121 | .set FVO_OFFSET, 0 | Format/vector offset placed in the stack |
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122 | #endif /* M68K_HAS_VBR */ |
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123 | |
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124 | .set SAVED, 16 | space for saved registers |
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125 | |
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126 | .align 4 |
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127 | .global SYM (_ISR_Handler) |
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128 | |
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129 | SYM (_ISR_Handler): |
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130 | addql #1,SYM (_Thread_Dispatch_disable_level) | disable multitasking |
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131 | #if ( M68K_COLDFIRE_ARCH == 0 ) |
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132 | moveml d0-d1/a0-a1,a7@- | save d0-d1,a0-a1 |
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133 | #else |
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134 | lea a7@(-SAVED),a7 |
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135 | movm.l d0-d1/a0-a1,a7@ | save d0-d1,a0-a1 |
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136 | #endif |
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137 | movew a7@(SAVED+FVO_OFFSET),d0 | d0 = F/VO |
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138 | andl #0x0ffc,d0 | d0 = vector offset in vbr |
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139 | |
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140 | |
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141 | #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 ) |
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142 | movel _CPU_Interrupt_stack_high,a0 | a0 now point just above interrupt stack |
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143 | cmpl _CPU_Interrupt_stack_low,a7 | stack below interrupt stack? |
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144 | bcs.b 1f | yes, switch to interrupt stack |
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145 | cmpl a0,a7 | stack above interrupt stack? |
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146 | bcs.b 2f | no, do not switch stacks |
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147 | 1: |
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148 | movel a7,a1 | copy task stack pointer |
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149 | movel a0,a7 | switch to interrupt stack |
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150 | movel a1,a7@- | store task stack pointer on interrupt stack |
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151 | 2: |
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152 | #endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */ |
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153 | |
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154 | addql #1,SYM(_ISR_Nest_level) | one nest level deeper |
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155 | |
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156 | movel SYM (_ISR_Vector_table),a0 | a0= base of RTEMS table |
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157 | #if ( M68K_HAS_PREINDEXING == 1 ) |
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158 | movel (a0,d0:w:1),a0 | a0 = address of user routine |
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159 | #else |
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160 | addal d0,a0 | a0 = address of vector |
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161 | movel (a0),a0 | a0 = address of user routine |
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162 | #endif |
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163 | |
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164 | lsrl #2,d0 | d0 = vector number |
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165 | movel d0,a7@- | push vector number |
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166 | jbsr a0@ | invoke the user ISR |
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167 | addql #4,a7 | remove vector number |
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168 | subql #1,SYM(_ISR_Nest_level) | Reduce interrupt-nesting count |
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169 | |
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170 | #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 ) |
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171 | movel _CPU_Interrupt_stack_high,a0 |
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172 | subql #4,a0 |
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173 | cmpl a0,a7 | At top of interrupt stack? |
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174 | bne.b 1f | No, do not restore task stack pointer |
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175 | movel (a7),a7 | Restore task stack pointer |
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176 | 1: |
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177 | #endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */ |
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178 | subql #1,SYM (_Thread_Dispatch_disable_level) |
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179 | | unnest multitasking |
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180 | bne.b exit | If dispatch disabled, exit |
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181 | |
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182 | #if ( M68K_HAS_SEPARATE_STACKS == 1 ) |
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183 | movew #0xf000,d0 | isolate format nibble |
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184 | andw a7@(SAVED+FVO_OFFSET),d0 | get F/VO |
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185 | cmpiw #0x1000,d0 | is it a throwaway isf? |
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186 | bne.b exit | NOT outer level, so branch |
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187 | #else |
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188 | /* |
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189 | * If we have a CPU which allows a higher-priority interrupt to preempt a |
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190 | * lower priority handler before the lower-priority handler can increment |
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191 | * _Thread_Dispatch_disable_level then we must check the PC on the stack to |
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192 | * see if it is _ISR_Handler. If it is we have the case of nesting interrupts |
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193 | * without the dispatch level being incremented. |
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194 | */ |
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195 | #if ( M68K_COLDFIRE_ARCH == 0 && M68K_MC68060_ARCH == 0 ) |
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196 | cmpl #_ISR_Handler,a7@(SAVED+PC_OFFSET) |
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197 | beq.b exit |
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198 | #endif |
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199 | #endif |
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200 | tstl SYM (_Context_Switch_necessary) |
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201 | | Is thread switch necessary? |
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202 | bne.b bframe | Yes, invoke dispatcher |
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203 | |
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204 | tstl SYM (_ISR_Signals_to_thread_executing) |
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205 | | signals sent to Run_thread |
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206 | | while in interrupt handler? |
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207 | beq.b exit | No, then exit |
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208 | |
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209 | bframe: clrl SYM (_ISR_Signals_to_thread_executing) |
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210 | | If sent, will be processed |
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211 | #if ( M68K_HAS_SEPARATE_STACKS == 1 ) |
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212 | movec msp,a0 | a0 = master stack pointer |
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213 | movew #0,a0@- | push format word |
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214 | movel #SYM(_ISR_Dispatch),a0@- | push return addr |
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215 | movew a0@(6),a0@- | push saved sr |
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216 | movec a0,msp | set master stack pointer |
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217 | #else |
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218 | jsr SYM (_Thread_Dispatch) | Perform context switch |
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219 | #endif |
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220 | |
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221 | #if ( M68K_COLDFIRE_ARCH == 0 ) |
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222 | exit: moveml a7@+,d0-d1/a0-a1 | restore d0-d1,a0-a1 |
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223 | #else |
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224 | exit: moveml a7@,d0-d1/a0-a1 | restore d0-d1,a0-a1 |
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225 | lea a7@(SAVED),a7 |
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226 | #endif |
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227 | |
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228 | #if ( M68K_HAS_VBR == 0 ) |
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229 | addql #2,a7 | pop format/id |
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230 | #endif /* M68K_HAS_VBR */ |
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231 | rte | return to thread |
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232 | | OR _Isr_dispatch |
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233 | |
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234 | /*PAGE |
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235 | * void _ISR_Dispatch() |
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236 | * |
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237 | * Entry point from the outermost interrupt service routine exit. |
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238 | * The current stack is the supervisor mode stack if this processor |
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239 | * has separate stacks. |
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240 | * |
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241 | * 1. save all registers not preserved across C calls. |
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242 | * 2. invoke the _Thread_Dispatch routine to switch tasks |
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243 | * or a signal to the currently executing task. |
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244 | * 3. restore all registers not preserved across C calls. |
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245 | * 4. return from interrupt |
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246 | */ |
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247 | |
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248 | .global SYM (_ISR_Dispatch) |
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249 | SYM (_ISR_Dispatch): |
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250 | #if ( M68K_COLDFIRE_ARCH == 0 ) |
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251 | movml d0-d1/a0-a1,a7@- |
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252 | jsr SYM (_Thread_Dispatch) |
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253 | movml a7@+,d0-d1/a0-a1 |
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254 | #else |
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255 | lea a7@(-SAVED),a7 |
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256 | movml d0-d1/a0-a1,a7@ |
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257 | jsr SYM (_Thread_Dispatch) |
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258 | movml a7@,d0-d1/a0-a1 |
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259 | lea a7@(SAVED),a7 |
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260 | #endif |
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261 | |
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262 | #if ( M68K_HAS_VBR == 0 ) |
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263 | addql #2,a7 | pop format/id |
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264 | #endif /* M68K_HAS_VBR */ |
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265 | rte |
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