source: rtems/cpukit/score/cpu/m68k/cpu_asm.S @ 44ad1151

4.104.114.84.95
Last change on this file since 44ad1151 was 97c73ed, checked in by Ralf Corsepius <ralf.corsepius@…>, on Jul 31, 2007 at 4:48:38 PM

Replace M68K_COLDFIRE_ARCH with mcoldfire.

  • Property mode set to 100644
File size: 9.8 KB
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1/*  cpu_asm.s
2 *
3 *  This file contains all assembly code for the MC68020 implementation
4 *  of RTEMS.
5 *
6 *  COPYRIGHT (c) 1989-2001.
7 *  On-Line Applications Research Corporation (OAR).
8 *
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.rtems.com/license/LICENSE.
12 *
13 *  $Id$
14 */
15
16
17#include <rtems/asm.h>
18
19        .text
20
21/*  void _CPU_Context_switch( run_context, heir_context )
22 *
23 *  This routine performs a normal non-FP context.
24 */
25
26        .align  4
27        .global SYM (_CPU_Context_switch)
28
29.set RUNCONTEXT_ARG,   4                   | save context argument
30.set HEIRCONTEXT_ARG,  8                   | restore context argument
31
32SYM (_CPU_Context_switch):
33          moval    a7@(RUNCONTEXT_ARG),a0| a0 = running thread context
34          movw     sr,d1                 | d1 = status register
35          movml    d1-d7/a2-a7,a0@       | save context
36
37          moval    a7@(HEIRCONTEXT_ARG),a0| a0 = heir thread context
38restore:  movml    a0@,d1-d7/a2-a7     | restore context
39          movw     d1,sr                  | restore status register
40          rts
41
42/*PAGE
43 *  void __CPU_Context_save_fp_context( &fp_context_ptr )
44 *  void __CPU_Context_restore_fp_context( &fp_context_ptr )
45 *
46 *  These routines are used to context switch a MC68881 or MC68882.
47 *
48 *  NOTE:  Context save and restore code is based upon the code shown
49 *         on page 6-38 of the MC68881/68882 Users Manual (rev 1).
50 *
51 *         CPU_FP_CONTEXT_SIZE is higher than expected to account for the
52 *         -1 pushed at end of this sequence.
53 *
54 *         Neither of these entries is required if we have software FPU
55 *         emulation.  But if we don't have an FPU or emulation, then
56 *         we need the stub versions of these routines.
57 */
58
59#if (CPU_SOFTWARE_FP == FALSE)
60
61.set FPCONTEXT_ARG,   4                    | save FP context argument
62
63        .align  4
64        .global SYM (_CPU_Context_save_fp)
65SYM (_CPU_Context_save_fp):
66#if ( M68K_HAS_FPU == 1 )
67        moval    a7@(FPCONTEXT_ARG),a1    | a1 = &ptr to context area
68        moval    a1@,a0                   | a0 = Save context area
69        fsave    a0@-                     | save 68881/68882 state frame
70        tstb     a0@                      | check for a null frame
71        beq.b    nosv                     | Yes, skip save of user model
72        fmovem   fp0-fp7,a0@-             | save data registers (fp0-fp7)
73        fmovem   fpc/fps/fpi,a0@-         | and save control registers
74        movl     #-1,a0@-                 | place not-null flag on stack
75nosv:   movl     a0,a1@                   | save pointer to saved context
76#endif
77        rts
78
79        .align  4
80        .global SYM (_CPU_Context_restore_fp)
81SYM (_CPU_Context_restore_fp):
82#if ( M68K_HAS_FPU == 1 )
83        moval    a7@(FPCONTEXT_ARG),a1    | a1 = &ptr to context area
84        moval    a1@,a0                   | a0 = address of saved context
85        tstb     a0@                      | Null context frame?
86        beq.b    norst                    | Yes, skip fp restore
87        addql    #4,a0                    | throwaway non-null flag
88        fmovem   a0@+,fpc/fps/fpi         | restore control registers
89        fmovem   a0@+,fp0-fp7             | restore data regs (fp0-fp7)
90norst:  frestore a0@+                     | restore the fp state frame
91        movl     a0,a1@                   | save pointer to saved context
92#endif
93        rts
94#endif
95
96/*PAGE
97 *  void _ISR_Handler()
98 *
99 *  This routine provides the RTEMS interrupt management.
100 *
101 *  NOTE:
102 *    Upon entry, the master stack will contain an interrupt stack frame
103 *    back to the interrupted thread and the interrupt stack will contain
104 *    a throwaway interrupt stack frame.  If dispatching is enabled, and this
105 *    is the outer most interrupt, and a context switch is necessary or
106 *    the current thread has pending signals, then set up the master stack to
107 *    transfer control to the interrupt dispatcher.
108 */
109
110#if ( defined(__mcoldfire__) )
111.set SR_OFFSET,    2                     | Status register offset
112.set PC_OFFSET,    4                     | Program Counter offset
113.set FVO_OFFSET,   0                     | Format/vector offset
114#elif ( M68K_HAS_VBR == 1)
115.set SR_OFFSET,    0                     | Status register offset
116.set PC_OFFSET,    2                     | Program Counter offset
117.set FVO_OFFSET,   6                     | Format/vector offset
118#else
119.set SR_OFFSET,    2                     | Status register offset
120.set PC_OFFSET,    4                     | Program Counter offset
121.set FVO_OFFSET,   0                     | Format/vector offset placed in the stack
122#endif /* M68K_HAS_VBR */
123 
124.set SAVED,        16                    | space for saved registers
125
126        .align  4
127        .global SYM (_ISR_Handler)
128
129SYM (_ISR_Handler):
130        addql   #1,SYM (_Thread_Dispatch_disable_level) | disable multitasking
131#if ( !defined(__mcoldfire__) )
132        moveml  d0-d1/a0-a1,a7@-         | save d0-d1,a0-a1
133#else
134        lea     a7@(-SAVED),a7
135        movm.l  d0-d1/a0-a1,a7@          | save d0-d1,a0-a1
136#endif
137        movew   a7@(SAVED+FVO_OFFSET),d0 | d0 = F/VO
138        andl    #0x03fc,d0               | d0 = vector offset in vbr
139
140
141#if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 )
142        movel   _CPU_Interrupt_stack_high,a0    | a0 now point just above interrupt stack
143        cmpl    _CPU_Interrupt_stack_low,a7     | stack below interrupt stack?
144        bcs.b   1f                      | yes, switch to interrupt stack
145        cmpl    a0,a7                   | stack above interrupt stack?
146        bcs.b   2f                      | no, do not switch stacks
1471:
148        movel   a7,a1                   | copy task stack pointer
149        movel   a0,a7                   | switch to interrupt stack
150        movel   a1,a7@-                 | store task stack pointer on interrupt stack
1512:
152#endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */
153
154        addql   #1,SYM(_ISR_Nest_level) | one nest level deeper
155       
156        movel   SYM (_ISR_Vector_table),a0 | a0= base of RTEMS table
157#if ( M68K_HAS_PREINDEXING == 1 )
158        movel   (a0,d0:w:1),a0           | a0 = address of user routine
159#else
160        addal   d0,a0                    | a0 = address of vector
161        movel   (a0),a0                  | a0 = address of user routine
162#endif
163
164        lsrl    #2,d0                    | d0 = vector number
165        movel   d0,a7@-                  | push vector number
166        jbsr    a0@                      | invoke the user ISR
167        addql   #4,a7                    | remove vector number
168        subql   #1,SYM(_ISR_Nest_level) | Reduce interrupt-nesting count
169
170#if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 )
171        movel   _CPU_Interrupt_stack_high,a0
172        subql   #4,a0
173        cmpl    a0,a7                   | At top of interrupt stack?
174        bne.b   1f                      | No, do not restore task stack pointer
175        movel   (a7),a7                 | Restore task stack pointer
1761:
177#endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */
178        subql   #1,SYM (_Thread_Dispatch_disable_level)
179                                         | unnest multitasking
180        bne.b    exit                    | If dispatch disabled, exit
181
182#if ( M68K_HAS_SEPARATE_STACKS == 1 )
183        movew   #0xf000,d0               | isolate format nibble
184        andw    a7@(SAVED+FVO_OFFSET),d0 | get F/VO
185        cmpiw   #0x1000,d0               | is it a throwaway isf?
186        bne.b   exit                     | NOT outer level, so branch
187#else
188/*
189 * If we have a CPU which allows a higher-priority interrupt to preempt a
190 * lower priority handler before the lower-priority handler can increment
191 * _Thread_Dispatch_disable_level then we must check the PC on the stack to
192 * see if it is _ISR_Handler.  If it is we have the case of nesting interrupts
193 * without the dispatch level being incremented.
194 */
195  #if ( !defined(__mcoldfire__) && M68K_MC68060_ARCH == 0 )
196        cmpl    #_ISR_Handler,a7@(SAVED+PC_OFFSET)
197        beq.b   exit       
198  #endif
199#endif
200        tstl    SYM (_Context_Switch_necessary)
201                                         | Is thread switch necessary?
202        bne.b   bframe                   | Yes, invoke dispatcher
203
204        tstl    SYM (_ISR_Signals_to_thread_executing)
205                                         | signals sent to Run_thread
206                                         |   while in interrupt handler?
207        beq.b   exit                     | No, then exit
208
209bframe: clrl    SYM (_ISR_Signals_to_thread_executing)
210                                         | If sent, will be processed
211#if ( M68K_HAS_SEPARATE_STACKS == 1 )
212        movec   msp,a0                   | a0 = master stack pointer
213        movew   #0,a0@-                  | push format word
214        movel   #SYM(_ISR_Dispatch),a0@- | push return addr
215        movew   a0@(6),a0@-              | push saved sr
216        movec   a0,msp                   | set master stack pointer
217#else
218        jsr SYM (_Thread_Dispatch)       | Perform context switch
219#endif
220
221#if ( !defined(__mcoldfire__) )
222exit:   moveml  a7@+,d0-d1/a0-a1         | restore d0-d1,a0-a1
223#else
224exit:   moveml  a7@,d0-d1/a0-a1          | restore d0-d1,a0-a1
225        lea     a7@(SAVED),a7
226#endif
227
228#if ( M68K_HAS_VBR == 0 )
229        addql   #2,a7                    | pop format/id
230#endif /* M68K_HAS_VBR */
231        rte                              | return to thread
232                                         |   OR _Isr_dispatch
233
234/*PAGE
235 *  void _ISR_Dispatch()
236 *
237 *  Entry point from the outermost interrupt service routine exit.
238 *  The current stack is the supervisor mode stack if this processor
239 *  has separate stacks.
240 *
241 *    1.  save all registers not preserved across C calls.
242 *    2.  invoke the _Thread_Dispatch routine to switch tasks
243 *        or a signal to the currently executing task.
244 *    3.  restore all registers not preserved across C calls.
245 *    4.  return from interrupt
246 */
247
248        .global SYM (_ISR_Dispatch)
249SYM (_ISR_Dispatch):
250#if ( !defined(__mcoldfire__) )
251        movml   d0-d1/a0-a1,a7@-
252        jsr     SYM (_Thread_Dispatch)
253        movml   a7@+,d0-d1/a0-a1
254#else
255        lea     a7@(-SAVED),a7
256        movml   d0-d1/a0-a1,a7@
257        jsr     SYM (_Thread_Dispatch)
258        movml   a7@,d0-d1/a0-a1
259        lea     a7@(SAVED),a7
260#endif
261
262#if ( M68K_HAS_VBR == 0 )
263        addql   #2,a7                    | pop format/id
264#endif /* M68K_HAS_VBR */
265        rte
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