| 1 | /* cpu_asm.s |
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| 2 | * |
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| 3 | * This file contains all assembly code for the MC68020 implementation |
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| 4 | * of RTEMS. |
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| 5 | * |
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| 6 | * COPYRIGHT (c) 1989-2008. |
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| 7 | * On-Line Applications Research Corporation (OAR). |
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| 8 | * |
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| 9 | * The license and distribution terms for this file may be |
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| 10 | * found in the file LICENSE in this distribution or at |
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| 11 | * http://www.rtems.com/license/LICENSE. |
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| 12 | */ |
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| 13 | |
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| 14 | |
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| 15 | #ifdef HAVE_CONFIG_H |
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| 16 | #include "config.h" |
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| 17 | #endif |
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| 18 | |
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| 19 | #include <rtems/asm.h> |
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| 20 | #include <rtems/score/percpu.h> |
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| 21 | |
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| 22 | /* void _CPU_Context_switch( run_context, heir_context ) |
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| 23 | * |
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| 24 | * This routine performs a normal non-FP context. |
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| 25 | */ |
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| 26 | |
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| 27 | .align 4 |
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| 28 | .global SYM (_CPU_Context_switch) |
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| 29 | |
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| 30 | .set RUNCONTEXT_ARG, 4 | save context argument |
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| 31 | .set HEIRCONTEXT_ARG, 8 | restore context argument |
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| 32 | |
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| 33 | SYM (_CPU_Context_switch): |
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| 34 | moval a7@(RUNCONTEXT_ARG),a0| a0 = running thread context |
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| 35 | movw sr,d1 | d1 = status register |
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| 36 | movml d1-d7/a2-a7,a0@ | save context |
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| 37 | |
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| 38 | moval a7@(HEIRCONTEXT_ARG),a0| a0 = heir thread context |
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| 39 | |
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| 40 | #if defined( __mcoldfire__ ) && ( M68K_HAS_FPU == 1 ) |
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| 41 | moveb a0@(13*4),d0 | get context specific DF bit info in d0 |
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| 42 | btstb #4,d0 | test context specific DF bit info |
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| 43 | beq fpu_on | branch if FPU needs to be switched on |
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| 44 | |
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| 45 | fpu_off: movl _CPU_cacr_shadow,d0 | get content of _CPU_cacr_shadow in d0 |
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| 46 | btstl #4,d0 | test DF bit info in d0 |
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| 47 | bne restore | branch if FPU is already switched off |
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| 48 | bsetl #4,d0 | set DF bit in d0 |
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| 49 | bra cacr_set | branch to set the new FPU setting in cacr and _CPU_cacr_shadow |
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| 50 | |
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| 51 | fpu_on: movl _CPU_cacr_shadow,d0 | get content of _CPU_cacr_shadow in d1 |
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| 52 | btstl #4,d0 | test context specific DF bit info |
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| 53 | beq restore | branch if FPU is already switched on |
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| 54 | bclrl #4,d0 | clear DF bit info in d0 |
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| 55 | |
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| 56 | cacr_set: movew sr,d1 | get content of sr in d1 |
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| 57 | oril #0x00000700,d1 | mask d1 |
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| 58 | movew d1,sr | disable all interrupts |
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| 59 | movl d0,_CPU_cacr_shadow | move _CPU_cacr_shadow to d1 |
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| 60 | movec d0,cacr | enable FPU in cacr |
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| 61 | #endif |
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| 62 | |
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| 63 | |
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| 64 | restore: movml a0@,d1-d7/a2-a7 | restore context |
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| 65 | movw d1,sr | restore status register |
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| 66 | rts |
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| 67 | |
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| 68 | .global SYM (_CPU_Context_Restart_self) |
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| 69 | .set CONTEXT_ARG, 4 | context arg |
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| 70 | |
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| 71 | #if defined( __mcoldfire__ ) && ( M68K_HAS_FPU == 1 ) |
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| 72 | /* XXX _CPU_Context_switch maintains FPU context -- do we have to restore |
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| 73 | * that, too?? |
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| 74 | */ |
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| 75 | #warning "_CPU_Context_Restart_self restoring FPU context not implemented" |
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| 76 | #endif |
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| 77 | SYM(_CPU_Context_Restart_self): |
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| 78 | moval a7@(CONTEXT_ARG),a0 |
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| 79 | bra restore |
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| 80 | /* |
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| 81 | * Floating point context save and restore. |
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| 82 | * |
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| 83 | * The code for the MC68881 or MC68882 is based upon the code shown on pages |
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| 84 | * 6-38 of the MC68881/68882 Users Manual (rev 1). CPU_FP_CONTEXT_SIZE is |
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| 85 | * higher than expected to account for the -1 pushed at end of this sequence. |
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| 86 | */ |
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| 87 | |
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| 88 | #if ( CPU_HARDWARE_FP == TRUE ) |
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| 89 | |
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| 90 | .set FPCONTEXT_ARG, 4 | save FP context argument |
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| 91 | |
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| 92 | .align 4 |
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| 93 | .global SYM (_CPU_Context_save_fp) |
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| 94 | SYM (_CPU_Context_save_fp): |
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| 95 | |
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| 96 | /* Get context save area pointer argument from the stack */ |
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| 97 | moval a7@(FPCONTEXT_ARG), a1 |
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| 98 | moval a1@, a0 |
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| 99 | |
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| 100 | #if defined( __mcoldfire__ ) |
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| 101 | /* Move MACSR to data register and disable rounding */ |
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| 102 | movel macsr, d0 |
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| 103 | clrl d1 |
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| 104 | movl d1, macsr |
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| 105 | |
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| 106 | /* Save MACSR and ACC0 */ |
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| 107 | movl acc0, d1 |
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| 108 | moveml d0-d1, a0@(0) |
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| 109 | |
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| 110 | /* Save ACC1 and ACC2 */ |
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| 111 | movl acc1, d0 |
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| 112 | movl acc2, d1 |
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| 113 | moveml d0-d1, a0@(8) |
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| 114 | |
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| 115 | /* Save ACC3 and ACCEXT01 */ |
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| 116 | movl acc3, d0 |
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| 117 | movl accext01, d1 |
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| 118 | moveml d0-d1, a0@(16) |
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| 119 | |
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| 120 | /* Save ACCEXT23 and MASK */ |
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| 121 | movl accext23, d0 |
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| 122 | movl mask, d1 |
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| 123 | moveml d0-d1, a0@(24) |
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| 124 | |
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| 125 | #if ( M68K_HAS_FPU == 1 ) |
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| 126 | /* Save FP state */ |
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| 127 | fsave a0@(32) |
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| 128 | |
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| 129 | /* Save FP instruction address */ |
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| 130 | fmovel fpi, a0@(48) |
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| 131 | |
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| 132 | /* Save FP data */ |
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| 133 | fmovem fp0-fp7, a0@(52) |
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| 134 | #endif |
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| 135 | #else |
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| 136 | #if defined( __mc68060__ ) |
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| 137 | lea a0@(-M68K_FP_STATE_SIZE), a0 |
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| 138 | fsave a0@ | save 68060 state frame |
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| 139 | #else |
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| 140 | fsave a0@- | save 68881/68882 state frame |
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| 141 | #endif |
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| 142 | tstb a0@ | check for a null frame |
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| 143 | beq.b nosv | Yes, skip save of user model |
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| 144 | fmovem fp0-fp7, a0@- | save data registers (fp0-fp7) |
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| 145 | fmovem fpc/fps/fpi, a0@- | and save control registers |
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| 146 | movl #-1, a0@- | place not-null flag on stack |
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| 147 | nosv: |
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| 148 | movl a0, a1@ | save pointer to saved context |
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| 149 | #endif |
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| 150 | |
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| 151 | /* Return */ |
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| 152 | rts |
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| 153 | |
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| 154 | .align 4 |
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| 155 | .global SYM (_CPU_Context_restore_fp) |
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| 156 | SYM (_CPU_Context_restore_fp): |
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| 157 | |
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| 158 | /* Get context save area pointer argument from the stack */ |
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| 159 | moval a7@(FPCONTEXT_ARG), a1 |
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| 160 | moval a1@, a0 |
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| 161 | |
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| 162 | #if defined( __mcoldfire__ ) |
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| 163 | #if ( M68K_HAS_FPU == 1 ) |
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| 164 | /* Restore FP data */ |
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| 165 | fmovem a0@(52), fp0-fp7 |
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| 166 | |
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| 167 | /* Restore FP instruction address */ |
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| 168 | fmovel a0@(48), fpi |
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| 169 | |
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| 170 | /* Restore FP state */ |
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| 171 | frestore a0@(32) |
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| 172 | #endif |
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| 173 | |
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| 174 | /* Disable rounding */ |
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| 175 | clrl d0 |
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| 176 | movl d0, macsr |
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| 177 | |
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| 178 | /* Restore MASK and ACCEXT23 */ |
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| 179 | moveml a0@(24), d0-d1 |
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| 180 | movl d0, mask |
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| 181 | movl d1, accext23 |
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| 182 | |
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| 183 | /* Restore ACCEXT01 and ACC3 */ |
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| 184 | moveml a0@(16), d0-d1 |
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| 185 | movl d0, accext01 |
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| 186 | movl d1, acc3 |
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| 187 | |
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| 188 | /* Restore ACC2 and ACC1 */ |
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| 189 | moveml a0@(8), d0-d1 |
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| 190 | movl d0, acc2 |
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| 191 | movl d1, acc1 |
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| 192 | |
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| 193 | /* Restore ACC0 and MACSR */ |
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| 194 | moveml a0@(0), d0-d1 |
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| 195 | movl d0, acc0 |
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| 196 | movl d1, macsr |
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| 197 | #else |
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| 198 | tstb a0@ | Null context frame? |
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| 199 | beq.b norst | Yes, skip fp restore |
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| 200 | addql #4, a0 | throwaway non-null flag |
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| 201 | fmovem a0@+, fpc/fps/fpi | restore control registers |
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| 202 | fmovem a0@+, fp0-fp7 | restore data regs (fp0-fp7) |
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| 203 | norst: |
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| 204 | #if defined( __mc68060__ ) |
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| 205 | frestore a0@ | restore 68060 state frame |
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| 206 | lea a0@(M68K_FP_STATE_SIZE), a0 |
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| 207 | #else |
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| 208 | frestore a0@+ | restore 68881/68882 state frame |
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| 209 | #endif |
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| 210 | movl a0, a1@ | save pointer to saved context |
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| 211 | #endif |
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| 212 | |
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| 213 | /* Return */ |
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| 214 | rts |
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| 215 | #endif |
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| 216 | |
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| 217 | /*void _ISR_Handler() |
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| 218 | * |
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| 219 | * This routine provides the RTEMS interrupt management. |
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| 220 | * |
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| 221 | * NOTE: |
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| 222 | * Upon entry, the master stack will contain an interrupt stack frame |
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| 223 | * back to the interrupted thread and the interrupt stack will contain |
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| 224 | * a throwaway interrupt stack frame. If dispatching is enabled, and this |
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| 225 | * is the outer most interrupt, and a context switch is necessary or |
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| 226 | * the current thread has pending signals, then set up the master stack to |
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| 227 | * transfer control to the interrupt dispatcher. |
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| 228 | */ |
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| 229 | |
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| 230 | #if ( defined(__mcoldfire__) ) |
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| 231 | .set SR_OFFSET, 2 | Status register offset |
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| 232 | .set PC_OFFSET, 4 | Program Counter offset |
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| 233 | .set FVO_OFFSET, 0 | Format/vector offset |
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| 234 | #elif ( M68K_HAS_VBR == 1) |
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| 235 | .set SR_OFFSET, 0 | Status register offset |
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| 236 | .set PC_OFFSET, 2 | Program Counter offset |
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| 237 | .set FVO_OFFSET, 6 | Format/vector offset |
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| 238 | #else |
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| 239 | .set SR_OFFSET, 2 | Status register offset |
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| 240 | .set PC_OFFSET, 4 | Program Counter offset |
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| 241 | .set FVO_OFFSET, 0 | Format/vector offset placed in the stack |
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| 242 | #endif /* M68K_HAS_VBR */ |
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| 243 | |
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| 244 | .set SAVED, 16 | space for saved registers |
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| 245 | |
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| 246 | .align 4 |
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| 247 | .global SYM (_ISR_Handler) |
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| 248 | |
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| 249 | SYM (_ISR_Handler): |
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| 250 | | disable multitasking |
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| 251 | addql #1,SYM (_Thread_Dispatch_disable_level) |
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| 252 | #if ( !defined(__mcoldfire__) ) |
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| 253 | moveml d0-d1/a0-a1,a7@- | save d0-d1,a0-a1 |
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| 254 | #else |
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| 255 | lea a7@(-SAVED),a7 |
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| 256 | movm.l d0-d1/a0-a1,a7@ | save d0-d1,a0-a1 |
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| 257 | #endif |
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| 258 | movew a7@(SAVED+FVO_OFFSET),d0 | d0 = F/VO |
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| 259 | andl #0x03fc,d0 | d0 = vector offset in vbr |
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| 260 | |
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| 261 | |
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| 262 | #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 ) |
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| 263 | | Make a0 point just above interrupt stack |
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| 264 | movel INTERRUPT_STACK_HIGH,a0 |
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| 265 | cmpl INTERRUPT_STACK_LOW,a7 | stack below interrupt stack? |
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| 266 | bcs.b 1f | yes, switch to interrupt stack |
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| 267 | cmpl a0,a7 | stack above interrupt stack? |
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| 268 | bcs.b 2f | no, do not switch stacks |
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| 269 | 1: |
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| 270 | movel a7,a1 | copy task stack pointer |
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| 271 | movel a0,a7 | switch to interrupt stack |
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| 272 | movel a1,a7@- | store task stack pointer |
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| 273 | | on interrupt stack |
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| 274 | 2: |
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| 275 | #endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */ |
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| 276 | |
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| 277 | addql #1,ISR_NEST_LEVEL | one nest level deeper |
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| 278 | |
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| 279 | movel SYM (_ISR_Vector_table),a0 | a0= base of RTEMS table |
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| 280 | #if ( M68K_HAS_PREINDEXING == 1 ) |
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| 281 | movel (a0,d0:w:1),a0 | a0 = address of user routine |
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| 282 | #else |
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| 283 | addal d0,a0 | a0 = address of vector |
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| 284 | movel (a0),a0 | a0 = address of user routine |
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| 285 | #endif |
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| 286 | |
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| 287 | lsrl #2,d0 | d0 = vector number |
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| 288 | movel d0,a7@- | push vector number |
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| 289 | jbsr a0@ | invoke the user ISR |
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| 290 | addql #4,a7 | remove vector number |
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| 291 | subql #1,ISR_NEST_LEVEL | Reduce interrupt-nesting count |
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| 292 | |
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| 293 | #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 ) |
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| 294 | movel INTERRUPT_STACK_HIGH,a0 |
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| 295 | subql #4,a0 |
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| 296 | cmpl a0,a7 | At top of interrupt stack? |
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| 297 | bne.b 1f | No, do not restore task stack pointer |
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| 298 | movel (a7),a7 | Restore task stack pointer |
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| 299 | 1: |
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| 300 | #endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */ |
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| 301 | subql #1,SYM (_Thread_Dispatch_disable_level) |
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| 302 | | unnest multitasking |
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| 303 | bne.b exit | If dispatch disabled, exit |
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| 304 | |
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| 305 | #if ( M68K_HAS_SEPARATE_STACKS == 1 ) |
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| 306 | movew #0xf000,d0 | isolate format nibble |
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| 307 | andw a7@(SAVED+FVO_OFFSET),d0 | get F/VO |
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| 308 | cmpiw #0x1000,d0 | is it a throwaway isf? |
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| 309 | bne.b exit | NOT outer level, so branch |
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| 310 | #else |
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| 311 | /* |
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| 312 | * If we have a CPU which allows a higher-priority interrupt to preempt a |
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| 313 | * lower priority handler before the lower-priority handler can increment |
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| 314 | * _Thread_Dispatch_disable_level then we must check the PC on the stack to |
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| 315 | * see if it is _ISR_Handler. If it is we have the case of nesting interrupts |
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| 316 | * without the dispatch level being incremented. |
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| 317 | */ |
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| 318 | #if ( !defined(__mcoldfire__) && !__mc68060__ ) |
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| 319 | cmpl #_ISR_Handler,a7@(SAVED+PC_OFFSET) |
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| 320 | beq.b exit |
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| 321 | #endif |
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| 322 | #endif |
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| 323 | tstb DISPATCH_NEEDED |
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| 324 | | Is thread switch necessary? |
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| 325 | beq.b exit | No, then exit |
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| 326 | |
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| 327 | bframe: |
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| 328 | | If sent, will be processed |
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| 329 | #if ( M68K_HAS_SEPARATE_STACKS == 1 ) |
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| 330 | movec msp,a0 | a0 = master stack pointer |
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| 331 | movew #0,a0@- | push format word |
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| 332 | movel #SYM(_ISR_Dispatch),a0@- | push return addr |
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| 333 | movew a0@(6),a0@- | push saved sr |
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| 334 | movec a0,msp | set master stack pointer |
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| 335 | #else |
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| 336 | jsr SYM (_Thread_Dispatch) | Perform context switch |
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| 337 | #endif |
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| 338 | |
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| 339 | #if ( !defined(__mcoldfire__) ) |
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| 340 | exit: moveml a7@+,d0-d1/a0-a1 | restore d0-d1,a0-a1 |
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| 341 | #else |
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| 342 | exit: moveml a7@,d0-d1/a0-a1 | restore d0-d1,a0-a1 |
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| 343 | lea a7@(SAVED),a7 |
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| 344 | #endif |
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| 345 | |
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| 346 | #if ( M68K_HAS_VBR == 0 ) |
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| 347 | addql #2,a7 | pop format/id |
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| 348 | #endif /* M68K_HAS_VBR */ |
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| 349 | rte | return to thread |
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| 350 | | OR _Isr_dispatch |
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| 351 | |
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| 352 | /*void _ISR_Dispatch() |
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| 353 | * |
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| 354 | * Entry point from the outermost interrupt service routine exit. |
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| 355 | * The current stack is the supervisor mode stack if this processor |
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| 356 | * has separate stacks. |
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| 357 | * |
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| 358 | * 1. save all registers not preserved across C calls. |
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| 359 | * 2. invoke the _Thread_Dispatch routine to switch tasks |
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| 360 | * or a signal to the currently executing task. |
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| 361 | * 3. restore all registers not preserved across C calls. |
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| 362 | * 4. return from interrupt |
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| 363 | */ |
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| 364 | |
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| 365 | .global SYM (_ISR_Dispatch) |
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| 366 | SYM (_ISR_Dispatch): |
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| 367 | #if ( !defined(__mcoldfire__) ) |
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| 368 | movml d0-d1/a0-a1,a7@- |
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| 369 | jsr SYM (_Thread_Dispatch) |
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| 370 | movml a7@+,d0-d1/a0-a1 |
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| 371 | #else |
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| 372 | lea a7@(-SAVED),a7 |
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| 373 | movml d0-d1/a0-a1,a7@ |
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| 374 | jsr SYM (_Thread_Dispatch) |
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| 375 | movml a7@,d0-d1/a0-a1 |
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| 376 | lea a7@(SAVED),a7 |
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| 377 | #endif |
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| 378 | |
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| 379 | #if ( M68K_HAS_VBR == 0 ) |
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| 380 | addql #2,a7 | pop format/id |
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| 381 | #endif /* M68K_HAS_VBR */ |
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| 382 | rte |
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