source: rtems/cpukit/score/cpu/m68k/cpu.c @ c03e2bc

4.104.115
Last change on this file since c03e2bc was c03e2bc, checked in by Joel Sherrill <joel.sherrill@…>, on 02/11/09 at 21:45:05

2009-02-11 Joel Sherrill <joel.sherrill@…>

  • cpu.c, rtems/score/cpu.h: Eliminate _CPU_Thread_dispatch_pointer and passing address of _Thread_Dispatch to _CPU_Initialize. Clean up comments.
  • Property mode set to 100644
File size: 4.9 KB
Line 
1/*
2 *  Motorola MC68xxx Dependent Source
3 *
4 *  COPYRIGHT (c) 1989-1999.
5 *  On-Line Applications Research Corporation (OAR).
6 *
7 *  The license and distribution terms for this file may be
8 *  found in the file LICENSE in this distribution or at
9 *  http://www.rtems.com/license/LICENSE.
10 *
11 *  $Id$
12 */
13
14#include <rtems/system.h>
15#include <rtems/score/isr.h>
16
17/*  _CPU_Initialize
18 *
19 *  This routine performs processor dependent initialization.
20 *
21 *  INPUT PARAMETERS: NONE
22 *
23 *  OUTPUT PARAMETERS: NONE
24 */
25
26void _CPU_Initialize(void)
27{
28#if ( M68K_HAS_VBR == 0 )
29  /* fill the isr redirect table with the code to place the format/id
30     onto the stack */
31
32  uint32_t   slot;
33
34  for (slot = 0; slot < CPU_INTERRUPT_NUMBER_OF_VECTORS; slot++)
35  {
36    _CPU_ISR_jump_table[slot].move_a7 = M68K_MOVE_A7;
37    _CPU_ISR_jump_table[slot].format_id = slot << 2;
38    _CPU_ISR_jump_table[slot].jmp = M68K_JMP;
39    _CPU_ISR_jump_table[slot].isr_handler = (uint32_t) 0xDEADDEAD;
40  }
41#endif /* M68K_HAS_VBR */
42}
43
44/*PAGE
45 *
46 *  _CPU_ISR_Get_level
47 */
48 
49uint32_t   _CPU_ISR_Get_level( void )
50{
51  uint32_t   level;
52
53  m68k_get_interrupt_level( level );
54
55  return level;
56}
57
58/*PAGE
59 *
60 *  _CPU_ISR_install_raw_handler
61 */
62 
63void _CPU_ISR_install_raw_handler(
64  uint32_t    vector,
65  proc_ptr    new_handler,
66  proc_ptr   *old_handler
67)
68{
69  proc_ptr *interrupt_table = NULL;
70
71#if (M68K_HAS_FPSP_PACKAGE == 1)
72  /*
73   *  If this vector being installed is one related to FP, then the
74   *  FPSP will install the handler itself and handle it completely
75   *  with no intervention from RTEMS.
76   */
77
78  if (*_FPSP_install_raw_handler &&
79      (*_FPSP_install_raw_handler)(vector, new_handler, *old_handler))
80        return;
81#endif
82
83
84  /*
85   *  On CPU models without a VBR, it is necessary for there to be some
86   *  header code for each ISR which saves a register, loads the vector
87   *  number, and jumps to _ISR_Handler.
88   */
89
90  m68k_get_vbr( interrupt_table );
91#if ( M68K_HAS_VBR == 1 )
92  *old_handler = interrupt_table[ vector ];
93  interrupt_table[ vector ] = new_handler;
94#else
95
96  /*
97   *  Install handler into RTEMS jump table and if VBR table is in
98   *  RAM, install the pointer to the appropriate jump table slot.
99   *  If the VBR table is in ROM, it is the BSP's responsibility to
100   *  load it appropriately to vector to the RTEMS jump table.
101   */
102
103  *old_handler = (proc_ptr) _CPU_ISR_jump_table[vector].isr_handler;
104  _CPU_ISR_jump_table[vector].isr_handler = (uint32_t) new_handler;
105  if ( (uint32_t) interrupt_table != 0xFFFFFFFF )
106    interrupt_table[ vector ] = (proc_ptr) &_CPU_ISR_jump_table[vector];
107#endif /* M68K_HAS_VBR */
108}
109
110/*PAGE
111 *
112 *  _CPU_ISR_install_vector
113 *
114 *  This kernel routine installs the RTEMS handler for the
115 *  specified vector.
116 *
117 *  Input parameters:
118 *    vector      - interrupt vector number
119 *    new_handler - replacement ISR for this vector number
120 *    old_handler - former ISR for this vector number
121 *
122 *  Output parameters:  NONE
123 */
124
125void _CPU_ISR_install_vector(
126  uint32_t    vector,
127  proc_ptr    new_handler,
128  proc_ptr   *old_handler
129)
130{
131  proc_ptr ignored = 0;  /* to avoid warning */
132
133  *old_handler = _ISR_Vector_table[ vector ];
134
135  _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
136
137  _ISR_Vector_table[ vector ] = new_handler;
138}
139
140
141/*PAGE
142 *
143 *  _CPU_Install_interrupt_stack
144 */
145
146void _CPU_Install_interrupt_stack( void )
147{
148#if ( M68K_HAS_SEPARATE_STACKS == 1 )
149  void *isp = _CPU_Interrupt_stack_high;
150
151  asm volatile ( "movec %0,%%isp" : "=r" (isp) : "0" (isp) );
152#endif
153}
154
155#if ( M68K_HAS_BFFFO != 1 )
156/*
157 * Returns table for duplication of the BFFFO instruction (16 bits only)
158 */
159const unsigned char _CPU_m68k_BFFFO_table[256] = {
160    8, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4,
161    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
162    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
163    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
164    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
165    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
166    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
167    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
168    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
169    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
170    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
171    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
172    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
173    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
174    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
175    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
176};
177#endif
178
179/*PAGE
180 *
181 *  The following code context switches the software FPU emulation
182 *  code provided with GCC.
183 */
184
185#if (CPU_SOFTWARE_FP == TRUE)
186extern Context_Control_fp _fpCCR;
187
188void CPU_Context_save_fp (Context_Control_fp **fp_context_ptr)
189{
190  Context_Control_fp *fp;
191
192  fp = *fp_context_ptr;
193
194  *fp = _fpCCR;
195}
196
197void CPU_Context_restore_fp (Context_Control_fp **fp_context_ptr)
198{
199  Context_Control_fp *fp;
200
201  fp = *fp_context_ptr;
202
203  _fpCCR = *fp;
204}
205#endif
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