source: rtems/cpukit/score/cpu/m68k/cpu.c @ b7185613

4.115
Last change on this file since b7185613 was b7185613, checked in by Alex Ivanov <alexivanov97@…>, on 12/07/12 at 14:57:04

score misc: Clean up Doxygen GCI Task #12

http://www.google-melange.com/gci/task/view/google/gci2012/7983217

  • Property mode set to 100644
File size: 4.5 KB
Line 
1/**
2 *  @file
3 *
4 *  @brief Motorola MC68xxx Dependent Source
5 */
6
7/*
8 *  COPYRIGHT (c) 1989-1999.
9 *  On-Line Applications Research Corporation (OAR).
10 *
11 *  The license and distribution terms for this file may be
12 *  found in the file LICENSE in this distribution or at
13 *  http://www.rtems.com/license/LICENSE.
14 */
15
16#ifdef HAVE_CONFIG_H
17#include "config.h"
18#endif
19
20#include <rtems/system.h>
21#include <rtems/score/isr.h>
22
23#if defined( __mcoldfire__ ) && ( M68K_HAS_FPU == 1 )
24  uint32_t _CPU_cacr_shadow;
25#endif
26
27void _CPU_Initialize(void)
28{
29#if ( M68K_HAS_VBR == 0 )
30  /* fill the isr redirect table with the code to place the format/id
31     onto the stack */
32
33  uint32_t   slot;
34
35  for (slot = 0; slot < CPU_INTERRUPT_NUMBER_OF_VECTORS; slot++)
36  {
37    _CPU_ISR_jump_table[slot].move_a7 = M68K_MOVE_A7;
38    _CPU_ISR_jump_table[slot].format_id = slot << 2;
39    _CPU_ISR_jump_table[slot].jmp = M68K_JMP;
40    _CPU_ISR_jump_table[slot].isr_handler = (uint32_t) 0xDEADDEAD;
41  }
42#endif /* M68K_HAS_VBR */
43}
44
45uint32_t   _CPU_ISR_Get_level( void )
46{
47  uint32_t   level;
48
49  m68k_get_interrupt_level( level );
50
51  return level;
52}
53
54/*
55 *  _CPU_ISR_install_raw_handler
56 */
57
58void _CPU_ISR_install_raw_handler(
59  uint32_t    vector,
60  proc_ptr    new_handler,
61  proc_ptr   *old_handler
62)
63{
64  proc_ptr *interrupt_table = NULL;
65
66#if (M68K_HAS_FPSP_PACKAGE == 1)
67  /*
68   *  If this vector being installed is one related to FP, then the
69   *  FPSP will install the handler itself and handle it completely
70   *  with no intervention from RTEMS.
71   */
72
73  if (*_FPSP_install_raw_handler &&
74      (*_FPSP_install_raw_handler)(vector, new_handler, *old_handler))
75        return;
76#endif
77
78
79  /*
80   *  On CPU models without a VBR, it is necessary for there to be some
81   *  header code for each ISR which saves a register, loads the vector
82   *  number, and jumps to _ISR_Handler.
83   */
84
85  m68k_get_vbr( interrupt_table );
86#if ( M68K_HAS_VBR == 1 )
87  *old_handler = interrupt_table[ vector ];
88  interrupt_table[ vector ] = new_handler;
89#else
90
91  /*
92   *  Install handler into RTEMS jump table and if VBR table is in
93   *  RAM, install the pointer to the appropriate jump table slot.
94   *  If the VBR table is in ROM, it is the BSP's responsibility to
95   *  load it appropriately to vector to the RTEMS jump table.
96   */
97
98  *old_handler = (proc_ptr) _CPU_ISR_jump_table[vector].isr_handler;
99  _CPU_ISR_jump_table[vector].isr_handler = (uint32_t) new_handler;
100  if ( (uint32_t) interrupt_table != 0xFFFFFFFF )
101    interrupt_table[ vector ] = (proc_ptr) &_CPU_ISR_jump_table[vector];
102#endif /* M68K_HAS_VBR */
103}
104
105void _CPU_ISR_install_vector(
106  uint32_t    vector,
107  proc_ptr    new_handler,
108  proc_ptr   *old_handler
109)
110{
111  proc_ptr ignored = 0;  /* to avoid warning */
112
113  *old_handler = _ISR_Vector_table[ vector ];
114
115  _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
116
117  _ISR_Vector_table[ vector ] = new_handler;
118}
119
120
121/*
122 *  _CPU_Install_interrupt_stack
123 */
124
125void _CPU_Install_interrupt_stack( void )
126{
127#if ( M68K_HAS_SEPARATE_STACKS == 1 )
128  void *isp = _CPU_Interrupt_stack_high;
129
130  __asm__ volatile ( "movec %0,%%isp" : "=r" (isp) : "0" (isp) );
131#endif
132}
133
134#if ( M68K_HAS_BFFFO != 1 )
135/*
136 * Returns table for duplication of the BFFFO instruction (16 bits only)
137 */
138const unsigned char _CPU_m68k_BFFFO_table[256] = {
139    8, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4,
140    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
141    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
142    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
143    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
144    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
145    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
146    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
147    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
148    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
149    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
150    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
151    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
152    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
153    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
154    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
155};
156#endif
157
158/*
159 *  The following code context switches the software FPU emulation
160 *  code provided with GCC.
161 */
162
163#if (CPU_SOFTWARE_FP == TRUE)
164extern Context_Control_fp _fpCCR;
165
166void _CPU_Context_save_fp (Context_Control_fp **fp_context_ptr)
167{
168  Context_Control_fp *fp;
169
170  fp = *fp_context_ptr;
171
172  *fp = _fpCCR;
173}
174
175void _CPU_Context_restore_fp (Context_Control_fp **fp_context_ptr)
176{
177  Context_Control_fp *fp;
178
179  fp = *fp_context_ptr;
180
181  _fpCCR = *fp;
182}
183#endif
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