source: rtems/cpukit/score/cpu/m68k/cpu.c @ 2bc236ba

4.104.114.84.95
Last change on this file since 2bc236ba was 3239698, checked in by Ralf Corsepius <ralf.corsepius@…>, on 04/15/04 at 13:26:21

Remove stray white spaces.

  • Property mode set to 100644
File size: 5.1 KB
Line 
1/*
2 *  Motorola MC68xxx Dependent Source
3 *
4 *  COPYRIGHT (c) 1989-1999.
5 *  On-Line Applications Research Corporation (OAR).
6 *
7 *  The license and distribution terms for this file may be
8 *  found in the file LICENSE in this distribution or at
9 *  http://www.rtems.com/license/LICENSE.
10 *
11 *  $Id$
12 */
13
14#include <rtems/system.h>
15#include <rtems/score/isr.h>
16
17/*  _CPU_Initialize
18 *
19 *  This routine performs processor dependent initialization.
20 *
21 *  INPUT PARAMETERS:
22 *    cpu_table       - CPU table to initialize
23 *    thread_dispatch - entry pointer to thread dispatcher
24 *
25 *  OUTPUT PARAMETERS: NONE
26 */
27
28void _CPU_Initialize(
29  rtems_cpu_table  *cpu_table,
30  void      (*thread_dispatch)      /* ignored on this CPU */
31)
32{
33#if ( M68K_HAS_VBR == 0 )
34  /* fill the isr redirect table with the code to place the format/id
35     onto the stack */
36
37  uint32_t   slot;
38
39  for (slot = 0; slot < CPU_INTERRUPT_NUMBER_OF_VECTORS; slot++)
40  {
41    _CPU_ISR_jump_table[slot].move_a7 = M68K_MOVE_A7;
42    _CPU_ISR_jump_table[slot].format_id = slot << 2;
43    _CPU_ISR_jump_table[slot].jmp = M68K_JMP;
44    _CPU_ISR_jump_table[slot].isr_handler = (uint32_t  ) 0xDEADDEAD;
45  }
46#endif /* M68K_HAS_VBR */
47
48  _CPU_Table = *cpu_table;
49}
50
51/*PAGE
52 *
53 *  _CPU_ISR_Get_level
54 */
55 
56uint32_t   _CPU_ISR_Get_level( void )
57{
58  uint32_t   level;
59
60  m68k_get_interrupt_level( level );
61
62  return level;
63}
64
65/*PAGE
66 *
67 *  _CPU_ISR_install_raw_handler
68 */
69 
70void _CPU_ISR_install_raw_handler(
71  uint32_t    vector,
72  proc_ptr    new_handler,
73  proc_ptr   *old_handler
74)
75{
76  proc_ptr *interrupt_table = NULL;
77
78#if (M68K_HAS_FPSP_PACKAGE == 1)
79  /*
80   *  If this vector being installed is one related to FP, then the
81   *  FPSP will install the handler itself and handle it completely
82   *  with no intervention from RTEMS.
83   */
84
85  if (*_FPSP_install_raw_handler &&
86      (*_FPSP_install_raw_handler)(vector, new_handler, *old_handler))
87        return;
88#endif
89
90
91  /*
92   *  On CPU models without a VBR, it is necessary for there to be some
93   *  header code for each ISR which saves a register, loads the vector
94   *  number, and jumps to _ISR_Handler.
95   */
96
97  m68k_get_vbr( interrupt_table );
98#if ( M68K_HAS_VBR == 1 )
99  *old_handler = interrupt_table[ vector ];
100  interrupt_table[ vector ] = new_handler;
101#else
102
103  /*
104   *  Install handler into RTEMS jump table and if VBR table is in
105   *  RAM, install the pointer to the appropriate jump table slot.
106   *  If the VBR table is in ROM, it is the BSP's responsibility to
107   *  load it appropriately to vector to the RTEMS jump table.
108   */
109
110  *old_handler = (proc_ptr) _CPU_ISR_jump_table[vector].isr_handler;
111  _CPU_ISR_jump_table[vector].isr_handler = (uint32_t  ) new_handler;
112  if ( (uint32_t  ) interrupt_table != 0xFFFFFFFF )
113    interrupt_table[ vector ] = (proc_ptr) &_CPU_ISR_jump_table[vector];
114#endif /* M68K_HAS_VBR */
115}
116
117/*PAGE
118 *
119 *  _CPU_ISR_install_vector
120 *
121 *  This kernel routine installs the RTEMS handler for the
122 *  specified vector.
123 *
124 *  Input parameters:
125 *    vector      - interrupt vector number
126 *    new_handler - replacement ISR for this vector number
127 *    old_handler - former ISR for this vector number
128 *
129 *  Output parameters:  NONE
130 */
131
132void _CPU_ISR_install_vector(
133  uint32_t    vector,
134  proc_ptr    new_handler,
135  proc_ptr   *old_handler
136)
137{
138  proc_ptr ignored;
139
140  *old_handler = _ISR_Vector_table[ vector ];
141
142  _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
143
144  _ISR_Vector_table[ vector ] = new_handler;
145}
146
147
148/*PAGE
149 *
150 *  _CPU_Install_interrupt_stack
151 */
152
153void _CPU_Install_interrupt_stack( void )
154{
155#if ( M68K_HAS_SEPARATE_STACKS == 1 )
156  void *isp = _CPU_Interrupt_stack_high;
157
158  asm volatile ( "movec %0,%%isp" : "=r" (isp) : "0" (isp) );
159#endif
160}
161
162#if ( M68K_HAS_BFFFO != 1 )
163/*
164 * Returns table for duplication of the BFFFO instruction (16 bits only)
165 */
166const unsigned char __BFFFOtable[256] = {
167    8, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4,
168    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
169    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
170    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
171    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
172    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
173    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
174    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
175    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
176    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
177    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
178    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
179    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
180    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
181    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
182    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
183};
184#endif
185
186/*PAGE
187 *
188 *  The following code context switches the software FPU emulation
189 *  code provided with GCC.
190 */
191
192#if (CPU_SOFTWARE_FP == TRUE)
193extern Context_Control_fp _fpCCR;
194
195void CPU_Context_save_fp (void **fp_context_ptr)
196{
197  Context_Control_fp *fp;
198
199  fp = (Context_Control_fp *) *fp_context_ptr;
200
201  *fp = _fpCCR;
202}
203
204void CPU_Context_restore_fp (void **fp_context_ptr)
205{
206  Context_Control_fp *fp;
207
208  fp = (Context_Control_fp *) *fp_context_ptr;
209
210  _fpCCR = *fp;
211}
212#endif
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