1 | /** |
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2 | * @file |
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3 | * |
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4 | * @brief Motorola MC68xxx Dependent Source |
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5 | */ |
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6 | |
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7 | /* |
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8 | * COPYRIGHT (c) 1989-1999. |
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9 | * On-Line Applications Research Corporation (OAR). |
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10 | * |
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11 | * The license and distribution terms for this file may be |
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12 | * found in the file LICENSE in this distribution or at |
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13 | * http://www.rtems.org/license/LICENSE. |
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14 | */ |
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15 | |
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16 | #ifdef HAVE_CONFIG_H |
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17 | #include "config.h" |
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18 | #endif |
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19 | |
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20 | #include <rtems/score/isr.h> |
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21 | #include <rtems/score/percpu.h> |
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22 | #include <rtems/score/tls.h> |
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23 | |
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24 | #if ( M68K_HAS_VBR == 0 ) |
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25 | |
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26 | /* |
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27 | * Table of ISR handler entries that resides in RAM. The FORMAT/ID is |
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28 | * pushed onto the stack. This is not is the same order as VBR processors. |
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29 | * The ISR handler takes the format and uses it for dispatching the user |
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30 | * handler. |
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31 | */ |
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32 | |
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33 | typedef struct { |
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34 | uint16_t move_a7; /* move #FORMAT_ID,%a7@- */ |
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35 | uint16_t format_id; |
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36 | uint16_t jmp; /* jmp _ISR_Handlers */ |
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37 | uint32_t isr_handler; |
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38 | } _CPU_ISR_handler_entry; |
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39 | |
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40 | #define M68K_MOVE_A7 0x3F3C |
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41 | #define M68K_JMP 0x4EF9 |
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42 | |
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43 | /* points to jsr-exception-table in targets wo/ VBR register */ |
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44 | static _CPU_ISR_handler_entry |
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45 | _CPU_ISR_jump_table[ CPU_INTERRUPT_NUMBER_OF_VECTORS ]; |
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46 | |
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47 | #endif /* M68K_HAS_VBR */ |
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48 | |
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49 | #if (M68K_HAS_FPSP_PACKAGE == 1) |
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50 | int (*_FPSP_install_raw_handler)( |
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51 | uint32_t vector, |
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52 | proc_ptr new_handler, |
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53 | proc_ptr *old_handler |
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54 | ); |
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55 | #endif |
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56 | |
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57 | #if defined( __mcoldfire__ ) && ( M68K_HAS_FPU == 1 ) |
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58 | uint32_t _CPU_cacr_shadow; |
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59 | #endif |
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60 | |
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61 | void _CPU_Initialize(void) |
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62 | { |
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63 | #if ( M68K_HAS_VBR == 0 ) |
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64 | /* fill the isr redirect table with the code to place the format/id |
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65 | onto the stack */ |
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66 | |
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67 | uint32_t slot; |
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68 | |
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69 | for (slot = 0; slot < CPU_INTERRUPT_NUMBER_OF_VECTORS; slot++) |
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70 | { |
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71 | _CPU_ISR_jump_table[slot].move_a7 = M68K_MOVE_A7; |
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72 | _CPU_ISR_jump_table[slot].format_id = slot << 2; |
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73 | _CPU_ISR_jump_table[slot].jmp = M68K_JMP; |
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74 | _CPU_ISR_jump_table[slot].isr_handler = (uint32_t) 0xDEADDEAD; |
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75 | } |
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76 | #endif /* M68K_HAS_VBR */ |
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77 | } |
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78 | |
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79 | uint32_t _CPU_ISR_Get_level( void ) |
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80 | { |
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81 | uint32_t level; |
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82 | |
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83 | m68k_get_interrupt_level( level ); |
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84 | |
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85 | return level; |
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86 | } |
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87 | |
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88 | /* |
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89 | * _CPU_ISR_install_raw_handler |
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90 | */ |
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91 | |
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92 | void _CPU_ISR_install_raw_handler( |
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93 | uint32_t vector, |
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94 | proc_ptr new_handler, |
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95 | proc_ptr *old_handler |
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96 | ) |
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97 | { |
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98 | proc_ptr *interrupt_table = NULL; |
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99 | |
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100 | #if (M68K_HAS_FPSP_PACKAGE == 1) |
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101 | /* |
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102 | * If this vector being installed is one related to FP, then the |
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103 | * FPSP will install the handler itself and handle it completely |
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104 | * with no intervention from RTEMS. |
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105 | */ |
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106 | |
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107 | if (*_FPSP_install_raw_handler && |
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108 | (*_FPSP_install_raw_handler)(vector, new_handler, *old_handler)) |
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109 | return; |
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110 | #endif |
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111 | |
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112 | |
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113 | /* |
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114 | * On CPU models without a VBR, it is necessary for there to be some |
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115 | * header code for each ISR which saves a register, loads the vector |
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116 | * number, and jumps to _ISR_Handler. |
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117 | */ |
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118 | |
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119 | m68k_get_vbr( interrupt_table ); |
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120 | #if ( M68K_HAS_VBR == 1 ) |
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121 | *old_handler = interrupt_table[ vector ]; |
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122 | interrupt_table[ vector ] = new_handler; |
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123 | #else |
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124 | |
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125 | /* |
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126 | * Install handler into RTEMS jump table and if VBR table is in |
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127 | * RAM, install the pointer to the appropriate jump table slot. |
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128 | * If the VBR table is in ROM, it is the BSP's responsibility to |
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129 | * load it appropriately to vector to the RTEMS jump table. |
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130 | */ |
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131 | |
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132 | *old_handler = (proc_ptr) _CPU_ISR_jump_table[vector].isr_handler; |
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133 | _CPU_ISR_jump_table[vector].isr_handler = (uint32_t) new_handler; |
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134 | if ( (uint32_t) interrupt_table != 0xFFFFFFFF ) |
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135 | interrupt_table[ vector ] = (proc_ptr) &_CPU_ISR_jump_table[vector]; |
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136 | #endif /* M68K_HAS_VBR */ |
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137 | } |
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138 | |
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139 | void _CPU_ISR_install_vector( |
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140 | uint32_t vector, |
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141 | proc_ptr new_handler, |
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142 | proc_ptr *old_handler |
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143 | ) |
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144 | { |
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145 | proc_ptr ignored = 0; /* to avoid warning */ |
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146 | |
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147 | *old_handler = _ISR_Vector_table[ vector ]; |
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148 | |
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149 | _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored ); |
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150 | |
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151 | _ISR_Vector_table[ vector ] = new_handler; |
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152 | } |
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153 | |
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154 | |
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155 | /* |
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156 | * _CPU_Install_interrupt_stack |
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157 | */ |
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158 | |
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159 | void _CPU_Install_interrupt_stack( void ) |
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160 | { |
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161 | #if ( M68K_HAS_SEPARATE_STACKS == 1 ) |
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162 | void *isp = _CPU_Interrupt_stack_high; |
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163 | |
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164 | __asm__ volatile ( "movec %0,%%isp" : "=r" (isp) : "0" (isp) ); |
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165 | #endif |
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166 | } |
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167 | |
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168 | #if ( M68K_HAS_BFFFO != 1 ) |
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169 | /* |
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170 | * Returns table for duplication of the BFFFO instruction (16 bits only) |
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171 | */ |
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172 | const unsigned char _CPU_m68k_BFFFO_table[256] = { |
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173 | 8, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, |
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174 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
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175 | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, |
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176 | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, |
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177 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, |
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178 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, |
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179 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, |
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180 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, |
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181 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
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182 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
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183 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
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184 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
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185 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
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186 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
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187 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
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188 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 |
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189 | }; |
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190 | #endif |
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191 | |
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192 | /* |
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193 | * The following code context switches the software FPU emulation |
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194 | * code provided with GCC. |
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195 | */ |
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196 | |
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197 | #if (CPU_SOFTWARE_FP == TRUE) |
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198 | extern Context_Control_fp _fpCCR; |
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199 | |
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200 | void _CPU_Context_save_fp (Context_Control_fp **fp_context_ptr) |
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201 | { |
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202 | Context_Control_fp *fp; |
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203 | |
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204 | fp = *fp_context_ptr; |
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205 | |
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206 | *fp = _fpCCR; |
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207 | } |
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208 | |
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209 | void _CPU_Context_restore_fp (Context_Control_fp **fp_context_ptr) |
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210 | { |
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211 | Context_Control_fp *fp; |
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212 | |
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213 | fp = *fp_context_ptr; |
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214 | |
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215 | _fpCCR = *fp; |
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216 | } |
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217 | #endif |
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218 | |
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219 | void _CPU_Context_Initialize( |
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220 | Context_Control *the_context, |
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221 | void *stack_area_begin, |
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222 | size_t stack_area_size, |
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223 | uint32_t new_level, |
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224 | void (*entry_point)( void ), |
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225 | bool is_fp, |
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226 | void *tls_area |
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227 | ) |
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228 | { |
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229 | uint32_t stack; |
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230 | |
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231 | the_context->sr = 0x3000 | (new_level << 8); |
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232 | stack = (uint32_t)stack_area_begin + stack_area_size - 4; |
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233 | the_context->a7_msp = (void *)stack; |
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234 | *(void **)stack = (void *)entry_point; |
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235 | |
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236 | #if (defined(__mcoldfire__) && ( M68K_HAS_FPU == 1 )) |
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237 | the_context->fpu_dis = is_fp ? 0x00 : 0x10; |
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238 | #endif |
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239 | |
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240 | if ( tls_area != NULL ) { |
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241 | _TLS_TCB_before_TLS_block_initialize( tls_area ); |
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242 | } |
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243 | } |
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