source: rtems/cpukit/score/cpu/m68k/cpu.c @ 059dbcf

4.104.114.84.95
Last change on this file since 059dbcf was 60b791ad, checked in by Joel Sherrill <joel.sherrill@…>, on 02/17/98 at 23:46:28

updated copyright to 1998

  • Property mode set to 100644
File size: 4.9 KB
Line 
1/*
2 *  Motorola MC68xxx Dependent Source
3 *
4 *  COPYRIGHT (c) 1989-1998.
5 *  On-Line Applications Research Corporation (OAR).
6 *  Copyright assigned to U.S. Government, 1994.
7 *
8 *  The license and distribution terms for this file may be
9 *  found in the file LICENSE in this distribution or at
10 *  http://www.OARcorp.com/rtems/license.html.
11 *
12 *  $Id$
13 */
14
15#include <rtems/system.h>
16#include <rtems/score/isr.h>
17
18/*  _CPU_Initialize
19 *
20 *  This routine performs processor dependent initialization.
21 *
22 *  INPUT PARAMETERS:
23 *    cpu_table       - CPU table to initialize
24 *    thread_dispatch - entry pointer to thread dispatcher
25 *
26 *  OUTPUT PARAMETERS: NONE
27 */
28
29void _CPU_Initialize(
30  rtems_cpu_table  *cpu_table,
31  void      (*thread_dispatch)      /* ignored on this CPU */
32)
33{
34#if ( M68K_HAS_VBR == 0 )
35  /* fill the isr redirect table with the code to place the format/id
36     onto the stack */
37
38  unsigned32 slot;
39
40  for (slot = 0; slot < CPU_INTERRUPT_NUMBER_OF_VECTORS; slot++)
41  {
42    _CPU_ISR_jump_table[slot].move_a7 = M68K_MOVE_A7;
43    _CPU_ISR_jump_table[slot].format_id = slot << 2;
44    _CPU_ISR_jump_table[slot].jmp = M68K_JMP;
45    _CPU_ISR_jump_table[slot].isr_handler = (unsigned32) 0xDEADDEAD;
46  }
47#endif /* M68K_HAS_VBR */
48
49  _CPU_Table = *cpu_table;
50}
51
52/*PAGE
53 *
54 *  _CPU_ISR_Get_level
55 */
56 
57unsigned32 _CPU_ISR_Get_level( void )
58{
59  unsigned32 level;
60
61  m68k_get_interrupt_level( level );
62
63  return level;
64}
65
66/*PAGE
67 *
68 *  _CPU_ISR_install_raw_handler
69 */
70 
71void _CPU_ISR_install_raw_handler(
72  unsigned32  vector,
73  proc_ptr    new_handler,
74  proc_ptr   *old_handler
75)
76{
77  proc_ptr *interrupt_table = NULL;
78
79#if (M68K_HAS_FPSP_PACKAGE == 1)
80  /*
81   *  If this vector being installed is one related to FP, then the
82   *  FPSP will install the handler itself and handle it completely
83   *  with no intervention from RTEMS.
84   */
85
86  if (*_FPSP_install_raw_handler &&
87      (*_FPSP_install_raw_handler)(vector, new_handler, *old_handler))
88        return;
89#endif
90
91
92  /*
93   *  On CPU models without a VBR, it is necessary for there to be some
94   *  header code for each ISR which saves a register, loads the vector
95   *  number, and jumps to _ISR_Handler.
96   */
97
98  m68k_get_vbr( interrupt_table );
99  *old_handler = interrupt_table[ vector ];
100#if ( M68K_HAS_VBR == 1 )
101  interrupt_table[ vector ] = new_handler;
102#else
103  _CPU_ISR_jump_table[vector].isr_handler = (unsigned32) new_handler;
104  interrupt_table[ vector ] = (proc_ptr) &_CPU_ISR_jump_table[vector];
105#endif /* M68K_HAS_VBR */
106}
107
108/*PAGE
109 *
110 *  _CPU_ISR_install_vector
111 *
112 *  This kernel routine installs the RTEMS handler for the
113 *  specified vector.
114 *
115 *  Input parameters:
116 *    vector      - interrupt vector number
117 *    new_handler - replacement ISR for this vector number
118 *    old_handler - former ISR for this vector number
119 *
120 *  Output parameters:  NONE
121 */
122
123void _CPU_ISR_install_vector(
124  unsigned32  vector,
125  proc_ptr    new_handler,
126  proc_ptr   *old_handler
127)
128{
129  proc_ptr ignored;
130
131  *old_handler = _ISR_Vector_table[ vector ];
132
133  _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
134
135  _ISR_Vector_table[ vector ] = new_handler;
136}
137
138
139/*PAGE
140 *
141 *  _CPU_Install_interrupt_stack
142 */
143
144void _CPU_Install_interrupt_stack( void )
145{
146#if ( M68K_HAS_SEPARATE_STACKS == 1 )
147  void *isp = _CPU_Interrupt_stack_high;
148
149  asm volatile ( "movec %0,%%isp" : "=r" (isp) : "0" (isp) );
150#else
151#warning "PLEASE IMPLEMENT ME... There is NO dedicated interrupt stack"
152#warning "on CPUs without a dedicated hardware interrupt stack!!!"
153#warning "INTERRUPTS RUN ON A TASK STACK!!!"
154#endif
155}
156
157#if ( M68K_HAS_BFFFO != 1 )
158/*
159 * Returns table for duplication of the BFFFO instruction (16 bits only)
160 */
161const unsigned char __BFFFOtable[256] = {
162    8, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4,
163    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
164    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
165    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
166    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
167    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
168    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
169    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
170    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
171    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
172    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
173    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
174    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
175    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
176    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
177    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
178};
179#endif
180
181/*PAGE
182 *
183 *  The following code context switches the software FPU emulation
184 *  code provided with GCC.
185 */
186
187#if (CPU_SOFTWARE_FP == TRUE)
188extern Context_Control_fp _fpCCR;
189
190void CPU_Context_save_fp (void **fp_context_ptr)
191{
192  Context_Control_fp *fp;
193
194  fp = (Context_Control_fp *) *fp_context_ptr;
195
196  *fp = _fpCCR;
197}
198
199void CPU_Context_restore_fp (void **fp_context_ptr)
200{
201  Context_Control_fp *fp;
202
203  fp = (Context_Control_fp *) *fp_context_ptr;
204
205  _fpCCR = *fp;
206}
207#endif
208
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