1 | /* |
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2 | * Motorola MC68xxx Dependent Source |
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3 | * |
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4 | * COPYRIGHT (c) 1989-1997. |
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5 | * On-Line Applications Research Corporation (OAR). |
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6 | * Copyright assigned to U.S. Government, 1994. |
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7 | * |
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8 | * The license and distribution terms for this file may in |
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9 | * the file LICENSE in this distribution or at |
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10 | * http://www.OARcorp.com/rtems/license.html. |
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11 | * |
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12 | * $Id$ |
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13 | */ |
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14 | |
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15 | #include <rtems/system.h> |
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16 | #include <rtems/score/isr.h> |
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17 | |
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18 | /* _CPU_Initialize |
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19 | * |
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20 | * This routine performs processor dependent initialization. |
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21 | * |
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22 | * INPUT PARAMETERS: |
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23 | * cpu_table - CPU table to initialize |
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24 | * thread_dispatch - entry pointer to thread dispatcher |
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25 | * |
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26 | * OUTPUT PARAMETERS: NONE |
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27 | */ |
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28 | |
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29 | void _CPU_Initialize( |
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30 | rtems_cpu_table *cpu_table, |
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31 | void (*thread_dispatch) /* ignored on this CPU */ |
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32 | ) |
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33 | { |
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34 | #if ( M68K_HAS_VBR == 0 ) |
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35 | /* fill the isr redirect table with the code to place the format/id |
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36 | onto the stack */ |
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37 | |
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38 | unsigned32 slot; |
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39 | |
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40 | for (slot = 0; slot < CPU_INTERRUPT_NUMBER_OF_VECTORS; slot++) |
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41 | { |
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42 | _CPU_ISR_jump_table[slot].move_a7 = M68K_MOVE_A7; |
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43 | _CPU_ISR_jump_table[slot].format_id = slot << 2; |
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44 | _CPU_ISR_jump_table[slot].jmp = M68K_JMP; |
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45 | _CPU_ISR_jump_table[slot].isr_handler = (unsigned32) 0xDEADDEAD; |
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46 | } |
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47 | #endif /* M68K_HAS_VBR */ |
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48 | |
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49 | _CPU_Table = *cpu_table; |
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50 | } |
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51 | |
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52 | /*PAGE |
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53 | * |
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54 | * _CPU_ISR_Get_level |
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55 | */ |
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56 | |
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57 | unsigned32 _CPU_ISR_Get_level( void ) |
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58 | { |
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59 | unsigned32 level; |
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60 | |
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61 | m68k_get_interrupt_level( level ); |
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62 | |
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63 | return level; |
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64 | } |
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65 | |
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66 | /*PAGE |
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67 | * |
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68 | * _CPU_ISR_install_raw_handler |
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69 | */ |
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70 | |
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71 | void _CPU_ISR_install_raw_handler( |
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72 | unsigned32 vector, |
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73 | proc_ptr new_handler, |
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74 | proc_ptr *old_handler |
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75 | ) |
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76 | { |
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77 | proc_ptr *interrupt_table = NULL; |
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78 | |
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79 | #if (M68K_HAS_FPSP_PACKAGE == 1) |
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80 | /* |
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81 | * If this vector being installed is one related to FP, then the |
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82 | * FPSP will install the handler itself and handle it completely |
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83 | * with no intervention from RTEMS. |
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84 | */ |
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85 | |
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86 | if (*_FPSP_install_raw_handler && |
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87 | (*_FPSP_install_raw_handler)(vector, new_handler, *old_handler)) |
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88 | return; |
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89 | #endif |
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90 | |
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91 | |
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92 | /* |
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93 | * On CPU models without a VBR, it is necessary for there to be some |
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94 | * header code for each ISR which saves a register, loads the vector |
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95 | * number, and jumps to _ISR_Handler. |
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96 | */ |
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97 | |
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98 | m68k_get_vbr( interrupt_table ); |
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99 | *old_handler = interrupt_table[ vector ]; |
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100 | #if ( M68K_HAS_VBR == 1 ) |
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101 | interrupt_table[ vector ] = new_handler; |
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102 | #else |
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103 | _CPU_ISR_jump_table[vector].isr_handler = (unsigned32) new_handler; |
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104 | interrupt_table[ vector ] = (proc_ptr) &_CPU_ISR_jump_table[vector]; |
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105 | #endif /* M68K_HAS_VBR */ |
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106 | } |
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107 | |
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108 | /*PAGE |
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109 | * |
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110 | * _CPU_ISR_install_vector |
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111 | * |
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112 | * This kernel routine installs the RTEMS handler for the |
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113 | * specified vector. |
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114 | * |
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115 | * Input parameters: |
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116 | * vector - interrupt vector number |
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117 | * new_handler - replacement ISR for this vector number |
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118 | * old_handler - former ISR for this vector number |
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119 | * |
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120 | * Output parameters: NONE |
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121 | */ |
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122 | |
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123 | void _CPU_ISR_install_vector( |
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124 | unsigned32 vector, |
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125 | proc_ptr new_handler, |
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126 | proc_ptr *old_handler |
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127 | ) |
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128 | { |
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129 | proc_ptr ignored; |
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130 | |
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131 | *old_handler = _ISR_Vector_table[ vector ]; |
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132 | |
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133 | _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored ); |
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134 | |
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135 | _ISR_Vector_table[ vector ] = new_handler; |
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136 | } |
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137 | |
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138 | |
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139 | /*PAGE |
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140 | * |
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141 | * _CPU_Install_interrupt_stack |
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142 | */ |
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143 | |
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144 | void _CPU_Install_interrupt_stack( void ) |
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145 | { |
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146 | #if ( M68K_HAS_SEPARATE_STACKS == 1 ) |
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147 | void *isp = _CPU_Interrupt_stack_high; |
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148 | |
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149 | asm volatile ( "movec %0,%%isp" : "=r" (isp) : "0" (isp) ); |
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150 | #else |
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151 | #warning "PLEASE IMPLEMENT ME... There is NO dedicated interrupt stack" |
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152 | #warning "on CPUs without a dedicated hardware interrupt stack!!!" |
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153 | #warning "INTERRUPTS RUN ON A TASK STACK!!!" |
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154 | #endif |
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155 | } |
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156 | |
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157 | #if ( M68K_HAS_BFFFO != 1 ) |
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158 | /* |
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159 | * Returns table for duplication of the BFFFO instruction (16 bits only) |
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160 | */ |
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161 | const unsigned char __BFFFOtable[256] = { |
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162 | 8, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, |
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163 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
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164 | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, |
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165 | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, |
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166 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, |
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167 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, |
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168 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, |
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169 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, |
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170 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
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171 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
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172 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
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173 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
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174 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
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175 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
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176 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
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177 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 |
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178 | }; |
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179 | #endif |
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