[ac7d5ef0] | 1 | /* |
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[38ffa0c] | 2 | * Motorola MC68xxx Dependent Source |
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[ac7d5ef0] | 3 | * |
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[08311cc3] | 4 | * COPYRIGHT (c) 1989-1999. |
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[ac7d5ef0] | 5 | * On-Line Applications Research Corporation (OAR). |
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| 6 | * |
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[98e4ebf5] | 7 | * The license and distribution terms for this file may be |
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| 8 | * found in the file LICENSE in this distribution or at |
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[05a98b7] | 9 | * http://www.rtems.com/license/LICENSE. |
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[ac7d5ef0] | 10 | * |
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| 11 | * $Id$ |
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| 12 | */ |
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| 13 | |
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| 14 | #include <rtems/system.h> |
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[5e9b32b] | 15 | #include <rtems/score/isr.h> |
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[ac7d5ef0] | 16 | |
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| 17 | /* _CPU_Initialize |
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| 18 | * |
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| 19 | * This routine performs processor dependent initialization. |
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| 20 | * |
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| 21 | * INPUT PARAMETERS: |
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| 22 | * cpu_table - CPU table to initialize |
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| 23 | * thread_dispatch - entry pointer to thread dispatcher |
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| 24 | * |
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| 25 | * OUTPUT PARAMETERS: NONE |
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| 26 | */ |
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| 27 | |
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| 28 | void _CPU_Initialize( |
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| 29 | rtems_cpu_table *cpu_table, |
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| 30 | void (*thread_dispatch) /* ignored on this CPU */ |
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| 31 | ) |
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| 32 | { |
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[f4b7e297] | 33 | #if ( M68K_HAS_VBR == 0 ) |
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| 34 | /* fill the isr redirect table with the code to place the format/id |
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| 35 | onto the stack */ |
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| 36 | |
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[d86bae8] | 37 | uint32_t slot; |
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[f4b7e297] | 38 | |
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| 39 | for (slot = 0; slot < CPU_INTERRUPT_NUMBER_OF_VECTORS; slot++) |
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| 40 | { |
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| 41 | _CPU_ISR_jump_table[slot].move_a7 = M68K_MOVE_A7; |
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| 42 | _CPU_ISR_jump_table[slot].format_id = slot << 2; |
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| 43 | _CPU_ISR_jump_table[slot].jmp = M68K_JMP; |
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[d86bae8] | 44 | _CPU_ISR_jump_table[slot].isr_handler = (uint32_t ) 0xDEADDEAD; |
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[f4b7e297] | 45 | } |
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| 46 | #endif /* M68K_HAS_VBR */ |
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| 47 | |
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[ac7d5ef0] | 48 | _CPU_Table = *cpu_table; |
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| 49 | } |
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| 50 | |
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[3a4ae6c] | 51 | /*PAGE |
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| 52 | * |
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| 53 | * _CPU_ISR_Get_level |
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| 54 | */ |
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| 55 | |
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[d86bae8] | 56 | uint32_t _CPU_ISR_Get_level( void ) |
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[3a4ae6c] | 57 | { |
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[d86bae8] | 58 | uint32_t level; |
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[3a4ae6c] | 59 | |
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| 60 | m68k_get_interrupt_level( level ); |
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| 61 | |
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| 62 | return level; |
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| 63 | } |
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| 64 | |
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[637df35] | 65 | /*PAGE |
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| 66 | * |
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| 67 | * _CPU_ISR_install_raw_handler |
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| 68 | */ |
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| 69 | |
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| 70 | void _CPU_ISR_install_raw_handler( |
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[d86bae8] | 71 | uint32_t vector, |
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[637df35] | 72 | proc_ptr new_handler, |
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| 73 | proc_ptr *old_handler |
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| 74 | ) |
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| 75 | { |
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| 76 | proc_ptr *interrupt_table = NULL; |
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| 77 | |
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[5bf6ffb] | 78 | #if (M68K_HAS_FPSP_PACKAGE == 1) |
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| 79 | /* |
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| 80 | * If this vector being installed is one related to FP, then the |
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| 81 | * FPSP will install the handler itself and handle it completely |
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| 82 | * with no intervention from RTEMS. |
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| 83 | */ |
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| 84 | |
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| 85 | if (*_FPSP_install_raw_handler && |
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| 86 | (*_FPSP_install_raw_handler)(vector, new_handler, *old_handler)) |
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| 87 | return; |
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| 88 | #endif |
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[637df35] | 89 | |
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[f4b7e297] | 90 | |
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[5bf6ffb] | 91 | /* |
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| 92 | * On CPU models without a VBR, it is necessary for there to be some |
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| 93 | * header code for each ISR which saves a register, loads the vector |
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| 94 | * number, and jumps to _ISR_Handler. |
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| 95 | */ |
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| 96 | |
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| 97 | m68k_get_vbr( interrupt_table ); |
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[f4b7e297] | 98 | #if ( M68K_HAS_VBR == 1 ) |
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[c533372] | 99 | *old_handler = interrupt_table[ vector ]; |
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[637df35] | 100 | interrupt_table[ vector ] = new_handler; |
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[38ffa0c] | 101 | #else |
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[5ede9706] | 102 | |
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| 103 | /* |
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| 104 | * Install handler into RTEMS jump table and if VBR table is in |
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| 105 | * RAM, install the pointer to the appropriate jump table slot. |
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| 106 | * If the VBR table is in ROM, it is the BSP's responsibility to |
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| 107 | * load it appropriately to vector to the RTEMS jump table. |
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| 108 | */ |
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| 109 | |
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[86e1c26] | 110 | *old_handler = (proc_ptr) _CPU_ISR_jump_table[vector].isr_handler; |
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[d86bae8] | 111 | _CPU_ISR_jump_table[vector].isr_handler = (uint32_t ) new_handler; |
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| 112 | if ( (uint32_t ) interrupt_table != 0xFFFFFFFF ) |
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[5ede9706] | 113 | interrupt_table[ vector ] = (proc_ptr) &_CPU_ISR_jump_table[vector]; |
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[38ffa0c] | 114 | #endif /* M68K_HAS_VBR */ |
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[637df35] | 115 | } |
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| 116 | |
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| 117 | /*PAGE |
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| 118 | * |
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| 119 | * _CPU_ISR_install_vector |
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[ac7d5ef0] | 120 | * |
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| 121 | * This kernel routine installs the RTEMS handler for the |
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| 122 | * specified vector. |
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| 123 | * |
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| 124 | * Input parameters: |
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| 125 | * vector - interrupt vector number |
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| 126 | * new_handler - replacement ISR for this vector number |
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| 127 | * old_handler - former ISR for this vector number |
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| 128 | * |
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| 129 | * Output parameters: NONE |
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| 130 | */ |
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| 131 | |
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| 132 | void _CPU_ISR_install_vector( |
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[d86bae8] | 133 | uint32_t vector, |
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[ac7d5ef0] | 134 | proc_ptr new_handler, |
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| 135 | proc_ptr *old_handler |
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| 136 | ) |
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| 137 | { |
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[926a05e] | 138 | proc_ptr ignored = 0; /* to avoid warning */ |
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[ac7d5ef0] | 139 | |
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| 140 | *old_handler = _ISR_Vector_table[ vector ]; |
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| 141 | |
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[637df35] | 142 | _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored ); |
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| 143 | |
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[ac7d5ef0] | 144 | _ISR_Vector_table[ vector ] = new_handler; |
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| 145 | } |
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| 146 | |
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| 147 | |
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| 148 | /*PAGE |
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| 149 | * |
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| 150 | * _CPU_Install_interrupt_stack |
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| 151 | */ |
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| 152 | |
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| 153 | void _CPU_Install_interrupt_stack( void ) |
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| 154 | { |
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| 155 | #if ( M68K_HAS_SEPARATE_STACKS == 1 ) |
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| 156 | void *isp = _CPU_Interrupt_stack_high; |
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| 157 | |
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| 158 | asm volatile ( "movec %0,%%isp" : "=r" (isp) : "0" (isp) ); |
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| 159 | #endif |
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| 160 | } |
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| 161 | |
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[9e86dd7d] | 162 | #if ( M68K_HAS_BFFFO != 1 ) |
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| 163 | /* |
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[38ffa0c] | 164 | * Returns table for duplication of the BFFFO instruction (16 bits only) |
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[9e86dd7d] | 165 | */ |
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[38ffa0c] | 166 | const unsigned char __BFFFOtable[256] = { |
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| 167 | 8, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, |
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| 168 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
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| 169 | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, |
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| 170 | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, |
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| 171 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, |
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| 172 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, |
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| 173 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, |
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| 174 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, |
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| 175 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
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| 176 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
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| 177 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
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| 178 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
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| 179 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
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| 180 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
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| 181 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
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| 182 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 |
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[9e86dd7d] | 183 | }; |
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| 184 | #endif |
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[00d2a828] | 185 | |
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| 186 | /*PAGE |
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| 187 | * |
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| 188 | * The following code context switches the software FPU emulation |
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| 189 | * code provided with GCC. |
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| 190 | */ |
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| 191 | |
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| 192 | #if (CPU_SOFTWARE_FP == TRUE) |
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| 193 | extern Context_Control_fp _fpCCR; |
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| 194 | |
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| 195 | void CPU_Context_save_fp (void **fp_context_ptr) |
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| 196 | { |
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| 197 | Context_Control_fp *fp; |
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| 198 | |
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| 199 | fp = (Context_Control_fp *) *fp_context_ptr; |
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| 200 | |
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| 201 | *fp = _fpCCR; |
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| 202 | } |
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| 203 | |
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| 204 | void CPU_Context_restore_fp (void **fp_context_ptr) |
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| 205 | { |
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| 206 | Context_Control_fp *fp; |
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| 207 | |
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| 208 | fp = (Context_Control_fp *) *fp_context_ptr; |
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| 209 | |
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| 210 | _fpCCR = *fp; |
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| 211 | } |
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| 212 | #endif |
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