source: rtems/cpukit/score/cpu/m32r/rtems/score/cpu.h @ f82752a4

4.115
Last change on this file since f82752a4 was f82752a4, checked in by Daniel Hellstrom <daniel@…>, on Jun 4, 2014 at 9:23:34 AM

Let CPU/BSP Fatal handler have access to source

Without the source the error code does not say that much.
Let it be up to the CPU/BSP to determine the error code
reported on fatal shutdown.

This patch does not change the current behaviour, just
adds the option to handle the source of the fatal halt.

  • Property mode set to 100644
File size: 40.6 KB
Line 
1/**
2 * @file
3 *
4 * @brief Intel M32R CPU Dependent Source
5 *
6 * This include file contains information pertaining to the XXX
7 * processor.
8 *
9 * NOTE: This file is part of a porting template that is intended
10 * to be used as the starting point when porting RTEMS to a new
11 * CPU family.  The following needs to be done when using this as
12 * the starting point for a new port:
13 *
14 * + Anywhere there is an XXX, it should be replaced
15 *   with information about the CPU family being ported to.
16 *
17 * + At the end of each comment section, there is a heading which
18 *   says "Port Specific Information:".  When porting to RTEMS,
19 *   add CPU family specific information in this section
20 */
21
22/*
23 *  COPYRIGHT (c) 1989-2008.
24 *  On-Line Applications Research Corporation (OAR).
25 *
26 *  The license and distribution terms for this file may be
27 *  found in the file LICENSE in this distribution or at
28 *  http://www.rtems.org/license/LICENSE.
29 */
30
31#ifndef _RTEMS_SCORE_CPU_H
32#define _RTEMS_SCORE_CPU_H
33
34#ifdef __cplusplus
35extern "C" {
36#endif
37
38#include <rtems/score/types.h>
39#include <rtems/score/m32r.h>
40
41/* conditional compilation parameters */
42
43/**
44 * Should the calls to @ref _Thread_Enable_dispatch be inlined?
45 *
46 * If TRUE, then they are inlined.
47 * If FALSE, then a subroutine call is made.
48 *
49 * This conditional is an example of the classic trade-off of size
50 * versus speed.  Inlining the call (TRUE) typically increases the
51 * size of RTEMS while speeding up the enabling of dispatching.
52 *
53 * NOTE: In general, the @ref _Thread_Dispatch_disable_level will
54 * only be 0 or 1 unless you are in an interrupt handler and that
55 * interrupt handler invokes the executive.]  When not inlined
56 * something calls @ref _Thread_Enable_dispatch which in turns calls
57 * @ref _Thread_Dispatch.  If the enable dispatch is inlined, then
58 * one subroutine call is avoided entirely.
59 *
60 * Port Specific Information:
61 *
62 * XXX document implementation including references if appropriate
63 */
64#define CPU_INLINE_ENABLE_DISPATCH       FALSE
65
66/**
67 * Should the body of the search loops in _Thread_queue_Enqueue_priority
68 * be unrolled one time?  In unrolled each iteration of the loop examines
69 * two "nodes" on the chain being searched.  Otherwise, only one node
70 * is examined per iteration.
71 *
72 * If TRUE, then the loops are unrolled.
73 * If FALSE, then the loops are not unrolled.
74 *
75 * The primary factor in making this decision is the cost of disabling
76 * and enabling interrupts (_ISR_Flash) versus the cost of rest of the
77 * body of the loop.  On some CPUs, the flash is more expensive than
78 * one iteration of the loop body.  In this case, it might be desirable
79 * to unroll the loop.  It is important to note that on some CPUs, this
80 * code is the longest interrupt disable period in RTEMS.  So it is
81 * necessary to strike a balance when setting this parameter.
82 *
83 * Port Specific Information:
84 *
85 * XXX document implementation including references if appropriate
86 */
87#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
88
89/**
90 * Does RTEMS manage a dedicated interrupt stack in software?
91 *
92 * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
93 * If FALSE, nothing is done.
94 *
95 * If the CPU supports a dedicated interrupt stack in hardware,
96 * then it is generally the responsibility of the BSP to allocate it
97 * and set it up.
98 *
99 * If the CPU does not support a dedicated interrupt stack, then
100 * the porter has two options: (1) execute interrupts on the
101 * stack of the interrupted task, and (2) have RTEMS manage a dedicated
102 * interrupt stack.
103 *
104 * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
105 *
106 * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
107 * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
108 * possible that both are FALSE for a particular CPU.  Although it
109 * is unclear what that would imply about the interrupt processing
110 * procedure on that CPU.
111 *
112 * Port Specific Information:
113 *
114 * XXX document implementation including references if appropriate
115 */
116#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
117
118/**
119 * Does the CPU follow the simple vectored interrupt model?
120 *
121 * If TRUE, then RTEMS allocates the vector table it internally manages.
122 * If FALSE, then the BSP is assumed to allocate and manage the vector
123 * table
124 *
125 * Port Specific Information:
126 *
127 * XXX document implementation including references if appropriate
128 */
129#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
130
131/**
132 * Does this CPU have hardware support for a dedicated interrupt stack?
133 *
134 * If TRUE, then it must be installed during initialization.
135 * If FALSE, then no installation is performed.
136 *
137 * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
138 *
139 * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
140 * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
141 * possible that both are FALSE for a particular CPU.  Although it
142 * is unclear what that would imply about the interrupt processing
143 * procedure on that CPU.
144 *
145 * Port Specific Information:
146 *
147 * XXX document implementation including references if appropriate
148 */
149#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
150
151/**
152 * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
153 *
154 * If TRUE, then the memory is allocated during initialization.
155 * If FALSE, then the memory is allocated during initialization.
156 *
157 * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
158 *
159 * Port Specific Information:
160 *
161 * XXX document implementation including references if appropriate
162 */
163#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
164
165/**
166 * Does the RTEMS invoke the user's ISR with the vector number and
167 * a pointer to the saved interrupt frame (1) or just the vector
168 * number (0)?
169 *
170 * Port Specific Information:
171 *
172 * XXX document implementation including references if appropriate
173 */
174#define CPU_ISR_PASSES_FRAME_POINTER 0
175
176/**
177 * @def CPU_HARDWARE_FP
178 *
179 * Does the CPU have hardware floating point?
180 *
181 * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
182 * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
183 *
184 * If there is a FP coprocessor such as the i387 or mc68881, then
185 * the answer is TRUE.
186 *
187 * The macro name "M32R_HAS_FPU" should be made CPU specific.
188 * It indicates whether or not this CPU model has FP support.  For
189 * example, it would be possible to have an i386_nofp CPU model
190 * which set this to false to indicate that you have an i386 without
191 * an i387 and wish to leave floating point support out of RTEMS.
192 */
193
194/**
195 * @def CPU_SOFTWARE_FP
196 *
197 * Does the CPU have no hardware floating point and GCC provides a
198 * software floating point implementation which must be context
199 * switched?
200 *
201 * This feature conditional is used to indicate whether or not there
202 * is software implemented floating point that must be context
203 * switched.  The determination of whether or not this applies
204 * is very tool specific and the state saved/restored is also
205 * compiler specific.
206 *
207 * Port Specific Information:
208 *
209 * XXX document implementation including references if appropriate
210 */
211#if ( M32R_HAS_FPU == 1 )
212#define CPU_HARDWARE_FP     TRUE
213#else
214#define CPU_HARDWARE_FP     FALSE
215#endif
216#define CPU_SOFTWARE_FP     FALSE
217
218/**
219 * Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
220 *
221 * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
222 * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
223 *
224 * So far, the only CPUs in which this option has been used are the
225 * HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
226 * gcc both implicitly used the floating point registers to perform
227 * integer multiplies.  Similarly, the PowerPC port of gcc has been
228 * seen to allocate floating point local variables and touch the FPU
229 * even when the flow through a subroutine (like vfprintf()) might
230 * not use floating point formats.
231 *
232 * If a function which you would not think utilize the FP unit DOES,
233 * then one can not easily predict which tasks will use the FP hardware.
234 * In this case, this option should be TRUE.
235 *
236 * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
237 *
238 * Port Specific Information:
239 *
240 * XXX document implementation including references if appropriate
241 */
242#define CPU_ALL_TASKS_ARE_FP     TRUE
243
244/**
245 * Should the IDLE task have a floating point context?
246 *
247 * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
248 * and it has a floating point context which is switched in and out.
249 * If FALSE, then the IDLE task does not have a floating point context.
250 *
251 * Setting this to TRUE negatively impacts the time required to preempt
252 * the IDLE task from an interrupt because the floating point context
253 * must be saved as part of the preemption.
254 *
255 * Port Specific Information:
256 *
257 * XXX document implementation including references if appropriate
258 */
259#define CPU_IDLE_TASK_IS_FP      FALSE
260
261/**
262 * Should the saving of the floating point registers be deferred
263 * until a context switch is made to another different floating point
264 * task?
265 *
266 * If TRUE, then the floating point context will not be stored until
267 * necessary.  It will remain in the floating point registers and not
268 * disturned until another floating point task is switched to.
269 *
270 * If FALSE, then the floating point context is saved when a floating
271 * point task is switched out and restored when the next floating point
272 * task is restored.  The state of the floating point registers between
273 * those two operations is not specified.
274 *
275 * If the floating point context does NOT have to be saved as part of
276 * interrupt dispatching, then it should be safe to set this to TRUE.
277 *
278 * Setting this flag to TRUE results in using a different algorithm
279 * for deciding when to save and restore the floating point context.
280 * The deferred FP switch algorithm minimizes the number of times
281 * the FP context is saved and restored.  The FP context is not saved
282 * until a context switch is made to another, different FP task.
283 * Thus in a system with only one FP task, the FP context will never
284 * be saved or restored.
285 *
286 * Port Specific Information:
287 *
288 * XXX document implementation including references if appropriate
289 */
290#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
291
292/**
293 * Does this port provide a CPU dependent IDLE task implementation?
294 *
295 * If TRUE, then the routine @ref _CPU_Thread_Idle_body
296 * must be provided and is the default IDLE thread body instead of
297 * @ref _CPU_Thread_Idle_body.
298 *
299 * If FALSE, then use the generic IDLE thread body if the BSP does
300 * not provide one.
301 *
302 * This is intended to allow for supporting processors which have
303 * a low power or idle mode.  When the IDLE thread is executed, then
304 * the CPU can be powered down.
305 *
306 * The order of precedence for selecting the IDLE thread body is:
307 *
308 *   -#  BSP provided
309 *   -#  CPU dependent (if provided)
310 *   -#  generic (if no BSP and no CPU dependent)
311 *
312 * Port Specific Information:
313 *
314 * XXX document implementation including references if appropriate
315 */
316#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
317
318/**
319 * Does the stack grow up (toward higher addresses) or down
320 * (toward lower addresses)?
321 *
322 * If TRUE, then the grows upward.
323 * If FALSE, then the grows toward smaller addresses.
324 *
325 * Port Specific Information:
326 *
327 * XXX document implementation including references if appropriate
328 */
329#define CPU_STACK_GROWS_UP               TRUE
330
331/**
332 * The following is the variable attribute used to force alignment
333 * of critical RTEMS structures.  On some processors it may make
334 * sense to have these aligned on tighter boundaries than
335 * the minimum requirements of the compiler in order to have as
336 * much of the critical data area as possible in a cache line.
337 *
338 * The placement of this macro in the declaration of the variables
339 * is based on the syntactically requirements of the GNU C
340 * "__attribute__" extension.  For example with GNU C, use
341 * the following to force a structures to a 32 byte boundary.
342 *
343 *     __attribute__ ((aligned (32)))
344 *
345 * NOTE: Currently only the Priority Bit Map table uses this feature.
346 *       To benefit from using this, the data must be heavily
347 *       used so it will stay in the cache and used frequently enough
348 *       in the executive to justify turning this on.
349 *
350 * Port Specific Information:
351 *
352 * XXX document implementation including references if appropriate
353 */
354#define CPU_STRUCTURE_ALIGNMENT
355
356#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE
357
358/**
359 * @defgroup CPUEndian Processor Dependent Endianness Support
360 *
361 * This group assists in issues related to processor endianness.
362 *
363 */
364/**@{**/
365
366/**
367 * Define what is required to specify how the network to host conversion
368 * routines are handled.
369 *
370 * NOTE: @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
371 * same values.
372 *
373 * @see CPU_LITTLE_ENDIAN
374 *
375 * Port Specific Information:
376 *
377 * XXX document implementation including references if appropriate
378 */
379#define CPU_BIG_ENDIAN                           TRUE
380
381/**
382 * Define what is required to specify how the network to host conversion
383 * routines are handled.
384 *
385 * NOTE: @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
386 * same values.
387 *
388 * @see CPU_BIG_ENDIAN
389 *
390 * Port Specific Information:
391 *
392 * XXX document implementation including references if appropriate
393 */
394#define CPU_LITTLE_ENDIAN                        FALSE
395
396/** @} */
397
398/**
399 * @ingroup CPUInterrupt
400 * The following defines the number of bits actually used in the
401 * interrupt field of the task mode.  How those bits map to the
402 * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
403 *
404 * Port Specific Information:
405 *
406 * XXX document implementation including references if appropriate
407 */
408#define CPU_MODES_INTERRUPT_MASK   0x00000001
409
410#define CPU_PER_CPU_CONTROL_SIZE 0
411
412/*
413 * Processor defined structures required for cpukit/score.
414 *
415 * Port Specific Information:
416 *
417 * XXX document implementation including references if appropriate
418 */
419
420/* may need to put some structures here.  */
421
422typedef struct {
423  /* There is no CPU specific per-CPU state */
424} CPU_Per_CPU_control;
425
426/**
427 * @defgroup CPUContext Processor Dependent Context Management
428 *
429 * From the highest level viewpoint, there are 2 types of context to save.
430 *
431 *    -# Interrupt registers to save
432 *    -# Task level registers to save
433 *
434 * Since RTEMS handles integer and floating point contexts separately, this
435 * means we have the following 3 context items:
436 *
437 *    -# task level context stuff::  Context_Control
438 *    -# floating point task stuff:: Context_Control_fp
439 *    -# special interrupt level context :: CPU_Interrupt_frame
440 *
441 * On some processors, it is cost-effective to save only the callee
442 * preserved registers during a task context switch.  This means
443 * that the ISR code needs to save those registers which do not
444 * persist across function calls.  It is not mandatory to make this
445 * distinctions between the caller/callee saves registers for the
446 * purpose of minimizing context saved during task switch and on interrupts.
447 * If the cost of saving extra registers is minimal, simplicity is the
448 * choice.  Save the same context on interrupt entry as for tasks in
449 * this case.
450 *
451 * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
452 * care should be used in designing the context area.
453 *
454 * On some CPUs with hardware floating point support, the Context_Control_fp
455 * structure will not be used or it simply consist of an array of a
456 * fixed number of bytes.   This is done when the floating point context
457 * is dumped by a "FP save context" type instruction and the format
458 * is not really defined by the CPU.  In this case, there is no need
459 * to figure out the exact format -- only the size.  Of course, although
460 * this is enough information for RTEMS, it is probably not enough for
461 * a debugger such as gdb.  But that is another problem.
462 *
463 * Port Specific Information:
464 *
465 * XXX document implementation including references if appropriate
466 */
467/**@{**/
468
469/**
470 * This defines the minimal set of integer and processor state registers
471 * that must be saved during a voluntary context switch from one thread
472 * to another.
473 */
474typedef struct {
475  /** r8 -- temporary register */
476  uint32_t r8;
477  /** r9 -- temporary register */
478  uint32_t r9;
479  /** r10 -- temporary register */
480  uint32_t r10;
481  /** r11 -- temporary register */
482  uint32_t r11;
483  /** r12 -- may be global pointer */
484  uint32_t r12;
485  /** r13 -- frame pointer */
486  uint32_t r13_fp;
487  /** r14 -- link register (aka return pointer */
488  uint32_t r14_lr;
489  /** r15 -- stack pointer */
490  uint32_t r15_sp;
491  /** dsp accumulator low order 32-bits */
492  uint32_t acc_low;
493  /** dsp accumulator high order 32-bits */
494  uint32_t acc_high;
495} Context_Control;
496
497/**
498 * This macro returns the stack pointer associated with @a _context.
499 *
500 * @param[in] _context is the thread context area to access
501 *
502 * @return This method returns the stack pointer.
503 */
504#define _CPU_Context_Get_SP( _context ) \
505  (_context)->r15_sp
506
507/**
508 * This defines the complete set of floating point registers that must
509 * be saved during any context switch from one thread to another.
510 */
511typedef struct {
512    /** FPU registers are listed here */
513    double      some_float_register;
514} Context_Control_fp;
515
516/**
517 * This defines the set of integer and processor state registers that must
518 * be saved during an interrupt.  This set does not include any which are
519 * in @ref Context_Control.
520 */
521typedef struct {
522    /** This field is a hint that a port will have a number of integer
523     * registers that need to be saved when an interrupt occurs or
524     * when a context switch occurs at the end of an ISR.
525     */
526    uint32_t   special_interrupt_register;
527} CPU_Interrupt_frame;
528
529/**
530 * This variable is optional.  It is used on CPUs on which it is difficult
531 * to generate an "uninitialized" FP context.  It is filled in by
532 * @ref _CPU_Initialize and copied into the task's FP context area during
533 * @ref _CPU_Context_Initialize.
534 *
535 * Port Specific Information:
536 *
537 * XXX document implementation including references if appropriate
538 */
539SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
540
541/** @} */
542
543/**
544 * @defgroup CPUInterrupt Processor Dependent Interrupt Management
545 *
546 * On some CPUs, RTEMS supports a software managed interrupt stack.
547 * This stack is allocated by the Interrupt Manager and the switch
548 * is performed in @ref _ISR_Handler.  These variables contain pointers
549 * to the lowest and highest addresses in the chunk of memory allocated
550 * for the interrupt stack.  Since it is unknown whether the stack
551 * grows up or down (in general), this give the CPU dependent
552 * code the option of picking the version it wants to use.
553 *
554 * NOTE: These two variables are required if the macro
555 *       @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
556 *
557 * Port Specific Information:
558 *
559 * XXX document implementation including references if appropriate
560 */
561/**@{**/
562
563/*
564 *  Nothing prevents the porter from declaring more CPU specific variables.
565 *
566 *  Port Specific Information:
567 *
568 *  XXX document implementation including references if appropriate
569 */
570
571/* XXX: if needed, put more variables here */
572
573/**
574 * @ingroup CPUContext
575 * The size of the floating point context area.  On some CPUs this
576 * will not be a "sizeof" because the format of the floating point
577 * area is not defined -- only the size is.  This is usually on
578 * CPUs with a "floating point save context" instruction.
579 *
580 * Port Specific Information:
581 *
582 * XXX document implementation including references if appropriate
583 */
584#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
585
586/**
587 * Amount of extra stack (above minimum stack size) required by
588 * MPCI receive server thread.  Remember that in a multiprocessor
589 * system this thread must exist and be able to process all directives.
590 *
591 * Port Specific Information:
592 *
593 * XXX document implementation including references if appropriate
594 */
595#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
596
597/**
598 * This defines the number of entries in the @ref _ISR_Vector_table managed
599 * by RTEMS.
600 *
601 * Port Specific Information:
602 *
603 * XXX document implementation including references if appropriate
604 */
605#define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
606
607/**
608 * This defines the highest interrupt vector number for this port.
609 */
610#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
611
612/**
613 * This is defined if the port has a special way to report the ISR nesting
614 * level.  Most ports maintain the variable @a _ISR_Nest_level.
615 */
616#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
617
618/** @} */
619
620/**
621 * @ingroup CPUContext
622 * Should be large enough to run all RTEMS tests.  This ensures
623 * that a "reasonable" small application should not have any problems.
624 *
625 * Port Specific Information:
626 *
627 * XXX document implementation including references if appropriate
628 */
629#define CPU_STACK_MINIMUM_SIZE          (1024)
630
631#define CPU_SIZEOF_POINTER 4
632
633/**
634 * CPU's worst alignment requirement for data types on a byte boundary.  This
635 * alignment does not take into account the requirements for the stack.
636 *
637 * Port Specific Information:
638 *
639 * XXX document implementation including references if appropriate
640 */
641#define CPU_ALIGNMENT              8
642
643/**
644 * This number corresponds to the byte alignment requirement for the
645 * heap handler.  This alignment requirement may be stricter than that
646 * for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
647 * common for the heap to follow the same alignment requirement as
648 * @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
649 * the heap, then this should be set to @ref CPU_ALIGNMENT.
650 *
651 * NOTE:  This does not have to be a power of 2 although it should be
652 *        a multiple of 2 greater than or equal to 2.  The requirement
653 *        to be a multiple of 2 is because the heap uses the least
654 *        significant field of the front and back flags to indicate
655 *        that a block is in use or free.  So you do not want any odd
656 *        length blocks really putting length data in that bit.
657 *
658 *        On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
659 *        have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
660 *        elements allocated from the heap meet all restrictions.
661 *
662 * Port Specific Information:
663 *
664 * XXX document implementation including references if appropriate
665 */
666#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
667
668/**
669 * This number corresponds to the byte alignment requirement for memory
670 * buffers allocated by the partition manager.  This alignment requirement
671 * may be stricter than that for the data types alignment specified by
672 * @ref CPU_ALIGNMENT.  It is common for the partition to follow the same
673 * alignment requirement as @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is
674 * strict enough for the partition, then this should be set to
675 * @ref CPU_ALIGNMENT.
676 *
677 * NOTE:  This does not have to be a power of 2.  It does have to
678 *        be greater or equal to than @ref CPU_ALIGNMENT.
679 *
680 * Port Specific Information:
681 *
682 * XXX document implementation including references if appropriate
683 */
684#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
685
686/**
687 * This number corresponds to the byte alignment requirement for the
688 * stack.  This alignment requirement may be stricter than that for the
689 * data types alignment specified by @ref CPU_ALIGNMENT.  If the
690 * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
691 * set to 0.
692 *
693 * NOTE: This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
694 *
695 * Port Specific Information:
696 *
697 * XXX document implementation including references if appropriate
698 */
699#define CPU_STACK_ALIGNMENT        0
700
701/*
702 *  ISR handler macros
703 */
704
705/**
706 * @addtogroup CPUInterrupt
707 */
708/**@{**/
709
710/**
711 * Support routine to initialize the RTEMS vector table after it is allocated.
712 *
713 * Port Specific Information:
714 *
715 * XXX document implementation including references if appropriate
716 */
717#define _CPU_Initialize_vectors()
718
719/**
720 * Disable all interrupts for an RTEMS critical section.  The previous
721 * level is returned in @a _isr_cookie.
722 *
723 * @param[out] _isr_cookie will contain the previous level cookie
724 *
725 * Port Specific Information:
726 *
727 * XXX document implementation including references if appropriate
728 */
729#define _CPU_ISR_Disable( _isr_cookie ) \
730  { \
731    (_isr_cookie) = 0;   /* do something to prevent warnings */ \
732  }
733
734/**
735 * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
736 * This indicates the end of an RTEMS critical section.  The parameter
737 * @a _isr_cookie is not modified.
738 *
739 * @param[in] _isr_cookie contain the previous level cookie
740 *
741 * Port Specific Information:
742 *
743 * XXX document implementation including references if appropriate
744 */
745#define _CPU_ISR_Enable( _isr_cookie )  \
746  { \
747    (_isr_cookie) = 0;   /* do something to prevent warnings */ \
748  }
749
750/**
751 * This temporarily restores the interrupt to @a _isr_cookie before immediately
752 * disabling them again.  This is used to divide long RTEMS critical
753 * sections into two or more parts.  The parameter @a _isr_cookie is not
754 * modified.
755 *
756 * @param[in] _isr_cookie contain the previous level cookie
757 *
758 * Port Specific Information:
759 *
760 * XXX document implementation including references if appropriate
761 */
762#define _CPU_ISR_Flash( _isr_cookie ) \
763  { \
764  }
765
766/**
767 * This routine and @ref _CPU_ISR_Get_level
768 * Map the interrupt level in task mode onto the hardware that the CPU
769 * actually provides.  Currently, interrupt levels which do not
770 * map onto the CPU in a generic fashion are undefined.  Someday,
771 * it would be nice if these were "mapped" by the application
772 * via a callout.  For example, m68k has 8 levels 0 - 7, levels
773 * 8 - 255 would be available for bsp/application specific meaning.
774 * This could be used to manage a programmable interrupt controller
775 * via the rtems_task_mode directive.
776 *
777 * Port Specific Information:
778 *
779 * XXX document implementation including references if appropriate
780 */
781#define _CPU_ISR_Set_level( new_level ) \
782  { \
783  }
784
785/**
786 * Return the current interrupt disable level for this task in
787 * the format used by the interrupt level portion of the task mode.
788 *
789 * NOTE: This routine usually must be implemented as a subroutine.
790 *
791 * Port Specific Information:
792 *
793 * XXX document implementation including references if appropriate
794 */
795uint32_t   _CPU_ISR_Get_level( void );
796
797/* end of ISR handler macros */
798
799/** @} */
800
801/* Context handler macros */
802
803/**
804 * @brief Initialize CPU context.
805 *
806 * @ingroup CPUContext
807 * Initialize the context to a state suitable for starting a
808 * task after a context restore operation.  Generally, this
809 * involves:
810 *
811 *    - setting a starting address
812 *    - preparing the stack
813 *    - preparing the stack and frame pointers
814 *    - setting the proper interrupt level in the context
815 *    - initializing the floating point context
816 *
817 * This routine generally does not set any unnecessary register
818 * in the context.  The state of the "general data" registers is
819 * undefined at task start time.
820 *
821 * @param[in] _the_context is the context structure to be initialized
822 * @param[in] _stack_base is the lowest physical address of this task's stack
823 * @param[in] _size is the size of this task's stack
824 * @param[in] _isr is the interrupt disable level
825 * @param[in] _entry_point is the thread's entry point.  This is
826 *        always @a _Thread_Handler
827 * @param[in] _is_fp is TRUE if the thread is to be a floating
828 *       point thread.  This is typically only used on CPUs where the
829 *       FPU may be easily disabled by software such as on the SPARC
830 *       where the PSR contains an enable FPU bit.
831 * @param[in] tls_area is the thread-local storage (TLS) area
832 *
833 * Port Specific Information:
834 *
835 * XXX document implementation including references if appropriate
836 */
837void _CPU_Context_Initialize(
838  Context_Control  *the_context,
839  uint32_t         *stack_base,
840  size_t            size,
841  uint32_t          new_level,
842  void             *entry_point,
843  bool              is_fp,
844  void             *tls_area
845);
846
847/**
848 * This routine is responsible for somehow restarting the currently
849 * executing task.  If you are lucky, then all that is necessary
850 * is restoring the context.  Otherwise, there will need to be
851 * a special assembly routine which does something special in this
852 * case.  For many ports, simply adding a label to the restore path
853 * of @ref _CPU_Context_switch will work.  On other ports, it may be
854 * possibly to load a few arguments and jump to the restore path. It will
855 * not work if restarting self conflicts with the stack frame
856 * assumptions of restoring a context.
857 *
858 * Port Specific Information:
859 *
860 * XXX document implementation including references if appropriate
861 */
862void _CPU_Context_Restart_self(
863  Context_Control  *the_context
864);
865
866/**
867 * @ingroup CPUContext
868 * The purpose of this macro is to allow the initial pointer into
869 * a floating point context area (used to save the floating point
870 * context) to be at an arbitrary place in the floating point
871 * context area.
872 *
873 * This is necessary because some FP units are designed to have
874 * their context saved as a stack which grows into lower addresses.
875 * Other FP units can be saved by simply moving registers into offsets
876 * from the base of the context area.  Finally some FP units provide
877 * a "dump context" instruction which could fill in from high to low
878 * or low to high based on the whim of the CPU designers.
879 *
880 * @param[in] _base is the lowest physical address of the floating point
881 *        context area
882 * @param[in] _offset is the offset into the floating point area
883 *
884 * Port Specific Information:
885 *
886 * XXX document implementation including references if appropriate
887 */
888#define _CPU_Context_Fp_start( _base, _offset ) \
889   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
890
891/**
892 * This routine initializes the FP context area passed to it to.
893 * There are a few standard ways in which to initialize the
894 * floating point context.  The code included for this macro assumes
895 * that this is a CPU in which a "initial" FP context was saved into
896 * @a _CPU_Null_fp_context and it simply copies it to the destination
897 * context passed to it.
898 *
899 * Other floating point context save/restore models include:
900 *   -# not doing anything, and
901 *   -# putting a "null FP status word" in the correct place in the FP context.
902 *
903 * @param[in] _destination is the floating point context area
904 *
905 * Port Specific Information:
906 *
907 * XXX document implementation including references if appropriate
908 */
909#define _CPU_Context_Initialize_fp( _destination ) \
910  { \
911   *(*(_destination)) = _CPU_Null_fp_context; \
912  }
913
914/* end of Context handler macros */
915
916/* Fatal Error manager macros */
917
918/**
919 * This routine copies _error into a known place -- typically a stack
920 * location or a register, optionally disables interrupts, and
921 * halts/stops the CPU.
922 *
923 * Port Specific Information:
924 *
925 * XXX document implementation including references if appropriate
926 */
927#define _CPU_Fatal_halt( _source, _error ) \
928  { \
929  }
930
931/* end of Fatal Error manager macros */
932
933/* Bitfield handler macros */
934
935/**
936 * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
937 *
938 * This set of routines are used to implement fast searches for
939 * the most important ready task.
940 */
941/**@{**/
942
943/**
944 * This definition is set to TRUE if the port uses the generic bitfield
945 * manipulation implementation.
946 */
947#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
948
949/**
950 * This definition is set to TRUE if the port uses the data tables provided
951 * by the generic bitfield manipulation implementation.
952 * This can occur when actually using the generic bitfield manipulation
953 * implementation or when implementing the same algorithm in assembly
954 * language for improved performance.  It is unlikely that a port will use
955 * the data if it has a bitfield scan instruction.
956 */
957#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
958
959/**
960 * This routine sets @a _output to the bit number of the first bit
961 * set in @a _value.  @a _value is of CPU dependent type
962 * @a Priority_bit_map_Word.  This type may be either 16 or 32 bits
963 * wide although only the 16 least significant bits will be used.
964 *
965 * There are a number of variables in using a "find first bit" type
966 * instruction.
967 *
968 *   -# What happens when run on a value of zero?
969 *   -# Bits may be numbered from MSB to LSB or vice-versa.
970 *   -# The numbering may be zero or one based.
971 *   -# The "find first bit" instruction may search from MSB or LSB.
972 *
973 * RTEMS guarantees that (1) will never happen so it is not a concern.
974 * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
975 * @ref _CPU_Priority_bits_index.  These three form a set of routines
976 * which must logically operate together.  Bits in the _value are
977 * set and cleared based on masks built by @ref _CPU_Priority_Mask.
978 * The basic major and minor values calculated by @ref _Priority_Major
979 * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
980 * to properly range between the values returned by the "find first bit"
981 * instruction.  This makes it possible for @ref _Priority_Get_highest to
982 * calculate the major and directly index into the minor table.
983 * This mapping is necessary to ensure that 0 (a high priority major/minor)
984 * is the first bit found.
985 *
986 * This entire "find first bit" and mapping process depends heavily
987 * on the manner in which a priority is broken into a major and minor
988 * components with the major being the 4 MSB of a priority and minor
989 * the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
990 * priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
991 * to the lowest priority.
992 *
993 * If your CPU does not have a "find first bit" instruction, then
994 * there are ways to make do without it.  Here are a handful of ways
995 * to implement this in software:
996 *
997@verbatim
998      - a series of 16 bit test instructions
999      - a "binary search using if's"
1000      - _number = 0
1001        if _value > 0x00ff
1002          _value >>=8
1003          _number = 8;
1004
1005        if _value > 0x0000f
1006          _value >=8
1007          _number += 4
1008
1009        _number += bit_set_table[ _value ]
1010@endverbatim
1011
1012 *   where bit_set_table[ 16 ] has values which indicate the first
1013 *     bit set
1014 *
1015 * @param[in] _value is the value to be scanned
1016 * @param[in] _output is the first bit set
1017 *
1018 * Port Specific Information:
1019 *
1020 * XXX document implementation including references if appropriate
1021 */
1022
1023#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1024#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
1025  { \
1026    (_output) = 0;   /* do something to prevent warnings */ \
1027  }
1028#endif
1029
1030/* end of Bitfield handler macros */
1031
1032/**
1033 * This routine builds the mask which corresponds to the bit fields
1034 * as searched by @ref _CPU_Bitfield_Find_first_bit.  See the discussion
1035 * for that routine.
1036 *
1037 * Port Specific Information:
1038 *
1039 * XXX document implementation including references if appropriate
1040 */
1041#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1042
1043#define _CPU_Priority_Mask( _bit_number ) \
1044  ( 1 << (_bit_number) )
1045
1046#endif
1047
1048/**
1049 * This routine translates the bit numbers returned by
1050 * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
1051 * a major or minor component of a priority.  See the discussion
1052 * for that routine.
1053 *
1054 * @param[in] _priority is the major or minor number to translate
1055 *
1056 * Port Specific Information:
1057 *
1058 * XXX document implementation including references if appropriate
1059 */
1060#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1061
1062#define _CPU_Priority_bits_index( _priority ) \
1063  (_priority)
1064
1065#endif
1066
1067/* end of Priority handler macros */
1068
1069/** @} */
1070
1071/* functions */
1072
1073/**
1074 * @brief CPU initialization.
1075 *
1076 * This routine performs CPU dependent initialization.
1077 *
1078 * Port Specific Information:
1079 *
1080 * XXX document implementation including references if appropriate
1081 */
1082void _CPU_Initialize(void);
1083
1084/**
1085 * @ingroup CPUInterrupt
1086 * This routine installs a "raw" interrupt handler directly into the
1087 * processor's vector table.
1088 *
1089 * @param[in] vector is the vector number
1090 * @param[in] new_handler is the raw ISR handler to install
1091 * @param[in] old_handler is the previously installed ISR Handler
1092 *
1093 * Port Specific Information:
1094 *
1095 * XXX document implementation including references if appropriate
1096 */
1097void _CPU_ISR_install_raw_handler(
1098  uint32_t    vector,
1099  proc_ptr    new_handler,
1100  proc_ptr   *old_handler
1101);
1102
1103/**
1104 * @ingroup CPUInterrupt
1105 * This routine installs an interrupt vector.
1106 *
1107 * @param[in] vector is the vector number
1108 * @param[in] new_handler is the RTEMS ISR handler to install
1109 * @param[in] old_handler is the previously installed ISR Handler
1110 *
1111 * Port Specific Information:
1112 *
1113 * XXX document implementation including references if appropriate
1114 */
1115void _CPU_ISR_install_vector(
1116  uint32_t    vector,
1117  proc_ptr    new_handler,
1118  proc_ptr   *old_handler
1119);
1120
1121/**
1122 * @ingroup CPUInterrupt
1123 * This routine installs the hardware interrupt stack pointer.
1124 *
1125 * NOTE:  It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
1126 *        is TRUE.
1127 *
1128 * Port Specific Information:
1129 *
1130 * XXX document implementation including references if appropriate
1131 */
1132void _CPU_Install_interrupt_stack( void );
1133
1134/**
1135 * @ingroup CPUContext
1136 * This routine switches from the run context to the heir context.
1137 *
1138 * @param[in] run points to the context of the currently executing task
1139 * @param[in] heir points to the context of the heir task
1140 *
1141 * Port Specific Information:
1142 *
1143 * XXX document implementation including references if appropriate
1144 */
1145void _CPU_Context_switch(
1146  Context_Control  *run,
1147  Context_Control  *heir
1148);
1149
1150/**
1151 * @addtogroup CPUContext
1152 */
1153/**@{**/
1154
1155/**
1156 * This routine is generally used only to restart self in an
1157 * efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
1158 *
1159 * @param[in] new_context points to the context to be restored.
1160 *
1161 * NOTE: May be unnecessary to reload some registers.
1162 *
1163 * Port Specific Information:
1164 *
1165 * XXX document implementation including references if appropriate
1166 */
1167void _CPU_Context_restore(
1168  Context_Control *new_context
1169) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
1170
1171/**
1172 * This routine saves the floating point context passed to it.
1173 *
1174 * @param[in] fp_context_ptr is a pointer to a pointer to a floating
1175 * point context area
1176 *
1177 * @return on output @a *fp_context_ptr will contain the address that
1178 * should be used with @ref _CPU_Context_restore_fp to restore this context.
1179 *
1180 * Port Specific Information:
1181 *
1182 * XXX document implementation including references if appropriate
1183 */
1184void _CPU_Context_save_fp(
1185  Context_Control_fp **fp_context_ptr
1186);
1187
1188/**
1189 * This routine restores the floating point context passed to it.
1190 *
1191 * @param[in] fp_context_ptr is a pointer to a pointer to a floating
1192 * point context area to restore
1193 *
1194 * @return on output @a *fp_context_ptr will contain the address that
1195 * should be used with @ref _CPU_Context_save_fp to save this context.
1196 *
1197 * Port Specific Information:
1198 *
1199 * XXX document implementation including references if appropriate
1200 */
1201void _CPU_Context_restore_fp(
1202  Context_Control_fp **fp_context_ptr
1203);
1204
1205static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
1206{
1207  /* TODO */
1208}
1209
1210static inline void _CPU_Context_validate( uintptr_t pattern )
1211{
1212  while (1) {
1213    /* TODO */
1214  }
1215}
1216
1217/** @} */
1218
1219/* FIXME */
1220typedef CPU_Interrupt_frame CPU_Exception_frame;
1221
1222void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
1223
1224/**
1225 * @ingroup CPUEndian
1226 * The following routine swaps the endian format of an unsigned int.
1227 * It must be static because it is referenced indirectly.
1228 *
1229 * This version will work on any processor, but if there is a better
1230 * way for your CPU PLEASE use it.  The most common way to do this is to:
1231 *
1232 *    swap least significant two bytes with 16-bit rotate
1233 *    swap upper and lower 16-bits
1234 *    swap most significant two bytes with 16-bit rotate
1235 *
1236 * Some CPUs have special instructions which swap a 32-bit quantity in
1237 * a single instruction (e.g. i486).  It is probably best to avoid
1238 * an "endian swapping control bit" in the CPU.  One good reason is
1239 * that interrupts would probably have to be disabled to ensure that
1240 * an interrupt does not try to access the same "chunk" with the wrong
1241 * endian.  Another good reason is that on some CPUs, the endian bit
1242 * endianness for ALL fetches -- both code and data -- so the code
1243 * will be fetched incorrectly.
1244 *
1245 * @param[in] value is the value to be swapped
1246 * @return the value after being endian swapped
1247 *
1248 * Port Specific Information:
1249 *
1250 * XXX document implementation including references if appropriate
1251 */
1252static inline uint32_t CPU_swap_u32(
1253  uint32_t value
1254)
1255{
1256  uint32_t byte1, byte2, byte3, byte4, swapped;
1257
1258  byte4 = (value >> 24) & 0xff;
1259  byte3 = (value >> 16) & 0xff;
1260  byte2 = (value >> 8)  & 0xff;
1261  byte1 =  value        & 0xff;
1262
1263  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1264  return swapped;
1265}
1266
1267/**
1268 * @ingroup CPUEndian
1269 * This routine swaps a 16 bir quantity.
1270 *
1271 * @param[in] value is the value to be swapped
1272 * @return the value after being endian swapped
1273 */
1274#define CPU_swap_u16( value ) \
1275  (((value&0xff) << 8) | ((value >> 8)&0xff))
1276
1277typedef uint32_t CPU_Counter_ticks;
1278
1279CPU_Counter_ticks _CPU_Counter_read( void );
1280
1281static inline CPU_Counter_ticks _CPU_Counter_difference(
1282  CPU_Counter_ticks second,
1283  CPU_Counter_ticks first
1284)
1285{
1286  return second - first;
1287}
1288
1289#ifdef __cplusplus
1290}
1291#endif
1292
1293#endif
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