source: rtems/cpukit/score/cpu/m32r/rtems/score/cpu.h @ 4ef13360

4.11
Last change on this file since 4ef13360 was 4ef13360, checked in by Joel Sherrill <joel.sherrill@…>, on Jul 29, 2010 at 5:51:56 PM

2010-07-29 Gedare Bloom <giddyup44@…>

PR 1635/cpukit

  • rtems/score/cpu.h, rtems/score/types.h: Refactoring of priority handling, to isolate the bitmap implementation of priorities in the supercore so that priority management is a little more modular. This change is in anticipation of scheduler implementations that can select how they manage tracking priority levels / finding the highest priority ready task. Note that most of the changes here are simple renaming, to clarify the use of the bitmap-based priority management.
  • Property mode set to 100644
File size: 40.6 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  This include file contains information pertaining to the XXX
7 *  processor.
8 *
9 *  @note This file is part of a porting template that is intended
10 *  to be used as the starting point when porting RTEMS to a new
11 *  CPU family.  The following needs to be done when using this as
12 *  the starting point for a new port:
13 *
14 *  + Anywhere there is an XXX, it should be replaced
15 *    with information about the CPU family being ported to.
16 *
17 *  + At the end of each comment section, there is a heading which
18 *    says "Port Specific Information:".  When porting to RTEMS,
19 *    add CPU family specific information in this section
20 */
21
22/*
23 *  COPYRIGHT (c) 1989-2008.
24 *  On-Line Applications Research Corporation (OAR).
25 *
26 *  The license and distribution terms for this file may be
27 *  found in the file LICENSE in this distribution or at
28 *  http://www.rtems.com/license/LICENSE.
29 *
30 *  $Id$
31 */
32
33#ifndef _RTEMS_SCORE_CPU_H
34#define _RTEMS_SCORE_CPU_H
35
36#ifdef __cplusplus
37extern "C" {
38#endif
39
40#include <rtems/score/types.h>
41#include <rtems/score/m32r.h>
42
43/* conditional compilation parameters */
44
45/**
46 *  Should the calls to @ref _Thread_Enable_dispatch be inlined?
47 *
48 *  If TRUE, then they are inlined.
49 *  If FALSE, then a subroutine call is made.
50 *
51 *  This conditional is an example of the classic trade-off of size
52 *  versus speed.  Inlining the call (TRUE) typically increases the
53 *  size of RTEMS while speeding up the enabling of dispatching.
54 *
55 *  @note In general, the @ref _Thread_Dispatch_disable_level will
56 *  only be 0 or 1 unless you are in an interrupt handler and that
57 *  interrupt handler invokes the executive.]  When not inlined
58 *  something calls @ref _Thread_Enable_dispatch which in turns calls
59 *  @ref _Thread_Dispatch.  If the enable dispatch is inlined, then
60 *  one subroutine call is avoided entirely.
61 *
62 *  Port Specific Information:
63 *
64 *  XXX document implementation including references if appropriate
65 */
66#define CPU_INLINE_ENABLE_DISPATCH       FALSE
67
68/**
69 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
70 *  be unrolled one time?  In unrolled each iteration of the loop examines
71 *  two "nodes" on the chain being searched.  Otherwise, only one node
72 *  is examined per iteration.
73 *
74 *  If TRUE, then the loops are unrolled.
75 *  If FALSE, then the loops are not unrolled.
76 *
77 *  The primary factor in making this decision is the cost of disabling
78 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
79 *  body of the loop.  On some CPUs, the flash is more expensive than
80 *  one iteration of the loop body.  In this case, it might be desirable
81 *  to unroll the loop.  It is important to note that on some CPUs, this
82 *  code is the longest interrupt disable period in RTEMS.  So it is
83 *  necessary to strike a balance when setting this parameter.
84 *
85 *  Port Specific Information:
86 *
87 *  XXX document implementation including references if appropriate
88 */
89#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
90
91/**
92 *  Does RTEMS manage a dedicated interrupt stack in software?
93 *
94 *  If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
95 *  If FALSE, nothing is done.
96 *
97 *  If the CPU supports a dedicated interrupt stack in hardware,
98 *  then it is generally the responsibility of the BSP to allocate it
99 *  and set it up.
100 *
101 *  If the CPU does not support a dedicated interrupt stack, then
102 *  the porter has two options: (1) execute interrupts on the
103 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
104 *  interrupt stack.
105 *
106 *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
107 *
108 *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
109 *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
110 *  possible that both are FALSE for a particular CPU.  Although it
111 *  is unclear what that would imply about the interrupt processing
112 *  procedure on that CPU.
113 *
114 *  Port Specific Information:
115 *
116 *  XXX document implementation including references if appropriate
117 */
118#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
119
120/**
121 *  Does the CPU follow the simple vectored interrupt model?
122 *
123 *  If TRUE, then RTEMS allocates the vector table it internally manages.
124 *  If FALSE, then the BSP is assumed to allocate and manage the vector
125 *  table
126 *
127 *  Port Specific Information:
128 *
129 *  XXX document implementation including references if appropriate
130 */
131#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
132
133/**
134 *  Does this CPU have hardware support for a dedicated interrupt stack?
135 *
136 *  If TRUE, then it must be installed during initialization.
137 *  If FALSE, then no installation is performed.
138 *
139 *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
140 *
141 *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
142 *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
143 *  possible that both are FALSE for a particular CPU.  Although it
144 *  is unclear what that would imply about the interrupt processing
145 *  procedure on that CPU.
146 *
147 *  Port Specific Information:
148 *
149 *  XXX document implementation including references if appropriate
150 */
151#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
152
153/**
154 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
155 *
156 *  If TRUE, then the memory is allocated during initialization.
157 *  If FALSE, then the memory is allocated during initialization.
158 *
159 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
160 *
161 *  Port Specific Information:
162 *
163 *  XXX document implementation including references if appropriate
164 */
165#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
166
167/**
168 *  Does the RTEMS invoke the user's ISR with the vector number and
169 *  a pointer to the saved interrupt frame (1) or just the vector
170 *  number (0)?
171 *
172 *  Port Specific Information:
173 *
174 *  XXX document implementation including references if appropriate
175 */
176#define CPU_ISR_PASSES_FRAME_POINTER 0
177
178/**
179 *  @def CPU_HARDWARE_FP
180 *
181 *  Does the CPU have hardware floating point?
182 *
183 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
184 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
185 *
186 *  If there is a FP coprocessor such as the i387 or mc68881, then
187 *  the answer is TRUE.
188 *
189 *  The macro name "M32R_HAS_FPU" should be made CPU specific.
190 *  It indicates whether or not this CPU model has FP support.  For
191 *  example, it would be possible to have an i386_nofp CPU model
192 *  which set this to false to indicate that you have an i386 without
193 *  an i387 and wish to leave floating point support out of RTEMS.
194 */
195
196/**
197 *  @def CPU_SOFTWARE_FP
198 *
199 *  Does the CPU have no hardware floating point and GCC provides a
200 *  software floating point implementation which must be context
201 *  switched?
202 *
203 *  This feature conditional is used to indicate whether or not there
204 *  is software implemented floating point that must be context
205 *  switched.  The determination of whether or not this applies
206 *  is very tool specific and the state saved/restored is also
207 *  compiler specific.
208 *
209 *  Port Specific Information:
210 *
211 *  XXX document implementation including references if appropriate
212 */
213#if ( M32R_HAS_FPU == 1 )
214#define CPU_HARDWARE_FP     TRUE
215#else
216#define CPU_HARDWARE_FP     FALSE
217#endif
218#define CPU_SOFTWARE_FP     FALSE
219
220/**
221 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
222 *
223 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
224 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
225 *
226 *  So far, the only CPUs in which this option has been used are the
227 *  HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
228 *  gcc both implicitly used the floating point registers to perform
229 *  integer multiplies.  Similarly, the PowerPC port of gcc has been
230 *  seen to allocate floating point local variables and touch the FPU
231 *  even when the flow through a subroutine (like vfprintf()) might
232 *  not use floating point formats.
233 *
234 *  If a function which you would not think utilize the FP unit DOES,
235 *  then one can not easily predict which tasks will use the FP hardware.
236 *  In this case, this option should be TRUE.
237 *
238 *  If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
239 *
240 *  Port Specific Information:
241 *
242 *  XXX document implementation including references if appropriate
243 */
244#define CPU_ALL_TASKS_ARE_FP     TRUE
245
246/**
247 *  Should the IDLE task have a floating point context?
248 *
249 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
250 *  and it has a floating point context which is switched in and out.
251 *  If FALSE, then the IDLE task does not have a floating point context.
252 *
253 *  Setting this to TRUE negatively impacts the time required to preempt
254 *  the IDLE task from an interrupt because the floating point context
255 *  must be saved as part of the preemption.
256 *
257 *  Port Specific Information:
258 *
259 *  XXX document implementation including references if appropriate
260 */
261#define CPU_IDLE_TASK_IS_FP      FALSE
262
263/**
264 *  Should the saving of the floating point registers be deferred
265 *  until a context switch is made to another different floating point
266 *  task?
267 *
268 *  If TRUE, then the floating point context will not be stored until
269 *  necessary.  It will remain in the floating point registers and not
270 *  disturned until another floating point task is switched to.
271 *
272 *  If FALSE, then the floating point context is saved when a floating
273 *  point task is switched out and restored when the next floating point
274 *  task is restored.  The state of the floating point registers between
275 *  those two operations is not specified.
276 *
277 *  If the floating point context does NOT have to be saved as part of
278 *  interrupt dispatching, then it should be safe to set this to TRUE.
279 *
280 *  Setting this flag to TRUE results in using a different algorithm
281 *  for deciding when to save and restore the floating point context.
282 *  The deferred FP switch algorithm minimizes the number of times
283 *  the FP context is saved and restored.  The FP context is not saved
284 *  until a context switch is made to another, different FP task.
285 *  Thus in a system with only one FP task, the FP context will never
286 *  be saved or restored.
287 *
288 *  Port Specific Information:
289 *
290 *  XXX document implementation including references if appropriate
291 */
292#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
293
294/**
295 *  Does this port provide a CPU dependent IDLE task implementation?
296 *
297 *  If TRUE, then the routine @ref _CPU_Thread_Idle_body
298 *  must be provided and is the default IDLE thread body instead of
299 *  @ref _CPU_Thread_Idle_body.
300 *
301 *  If FALSE, then use the generic IDLE thread body if the BSP does
302 *  not provide one.
303 *
304 *  This is intended to allow for supporting processors which have
305 *  a low power or idle mode.  When the IDLE thread is executed, then
306 *  the CPU can be powered down.
307 *
308 *  The order of precedence for selecting the IDLE thread body is:
309 *
310 *    -#  BSP provided
311 *    -#  CPU dependent (if provided)
312 *    -#  generic (if no BSP and no CPU dependent)
313 *
314 *  Port Specific Information:
315 *
316 *  XXX document implementation including references if appropriate
317 */
318#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
319
320/**
321 *  Does the stack grow up (toward higher addresses) or down
322 *  (toward lower addresses)?
323 *
324 *  If TRUE, then the grows upward.
325 *  If FALSE, then the grows toward smaller addresses.
326 *
327 *  Port Specific Information:
328 *
329 *  XXX document implementation including references if appropriate
330 */
331#define CPU_STACK_GROWS_UP               TRUE
332
333/**
334 *  The following is the variable attribute used to force alignment
335 *  of critical RTEMS structures.  On some processors it may make
336 *  sense to have these aligned on tighter boundaries than
337 *  the minimum requirements of the compiler in order to have as
338 *  much of the critical data area as possible in a cache line.
339 *
340 *  The placement of this macro in the declaration of the variables
341 *  is based on the syntactically requirements of the GNU C
342 *  "__attribute__" extension.  For example with GNU C, use
343 *  the following to force a structures to a 32 byte boundary.
344 *
345 *      __attribute__ ((aligned (32)))
346 *
347 *  @note Currently only the Priority Bit Map table uses this feature.
348 *        To benefit from using this, the data must be heavily
349 *        used so it will stay in the cache and used frequently enough
350 *        in the executive to justify turning this on.
351 *
352 *  Port Specific Information:
353 *
354 *  XXX document implementation including references if appropriate
355 */
356#define CPU_STRUCTURE_ALIGNMENT
357
358/**
359 *  @defgroup CPUEndian Processor Dependent Endianness Support
360 *
361 *  This group assists in issues related to processor endianness.
362 */
363
364/**
365 *  @ingroup CPUEndian
366 *  Define what is required to specify how the network to host conversion
367 *  routines are handled.
368 *
369 *  @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
370 *  same values.
371 *
372 *  @see CPU_LITTLE_ENDIAN
373 *
374 *  Port Specific Information:
375 *
376 *  XXX document implementation including references if appropriate
377 */
378#define CPU_BIG_ENDIAN                           TRUE
379
380/**
381 *  @ingroup CPUEndian
382 *  Define what is required to specify how the network to host conversion
383 *  routines are handled.
384 *
385 *  @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
386 *  same values.
387 *
388 *  @see CPU_BIG_ENDIAN
389 *
390 *  Port Specific Information:
391 *
392 *  XXX document implementation including references if appropriate
393 */
394#define CPU_LITTLE_ENDIAN                        FALSE
395
396/**
397 *  @ingroup CPUInterrupt
398 *  The following defines the number of bits actually used in the
399 *  interrupt field of the task mode.  How those bits map to the
400 *  CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
401 *
402 *  Port Specific Information:
403 *
404 *  XXX document implementation including references if appropriate
405 */
406#define CPU_MODES_INTERRUPT_MASK   0x00000001
407
408/*
409 *  Processor defined structures required for cpukit/score.
410 *
411 *  Port Specific Information:
412 *
413 *  XXX document implementation including references if appropriate
414 */
415
416/* may need to put some structures here.  */
417
418/**
419 * @defgroup CPUContext Processor Dependent Context Management
420 *
421 *  From the highest level viewpoint, there are 2 types of context to save.
422 *
423 *     -# Interrupt registers to save
424 *     -# Task level registers to save
425 *
426 *  Since RTEMS handles integer and floating point contexts separately, this
427 *  means we have the following 3 context items:
428 *
429 *     -# task level context stuff::  Context_Control
430 *     -# floating point task stuff:: Context_Control_fp
431 *     -# special interrupt level context :: CPU_Interrupt_frame
432 *
433 *  On some processors, it is cost-effective to save only the callee
434 *  preserved registers during a task context switch.  This means
435 *  that the ISR code needs to save those registers which do not
436 *  persist across function calls.  It is not mandatory to make this
437 *  distinctions between the caller/callee saves registers for the
438 *  purpose of minimizing context saved during task switch and on interrupts.
439 *  If the cost of saving extra registers is minimal, simplicity is the
440 *  choice.  Save the same context on interrupt entry as for tasks in
441 *  this case.
442 *
443 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
444 *  care should be used in designing the context area.
445 *
446 *  On some CPUs with hardware floating point support, the Context_Control_fp
447 *  structure will not be used or it simply consist of an array of a
448 *  fixed number of bytes.   This is done when the floating point context
449 *  is dumped by a "FP save context" type instruction and the format
450 *  is not really defined by the CPU.  In this case, there is no need
451 *  to figure out the exact format -- only the size.  Of course, although
452 *  this is enough information for RTEMS, it is probably not enough for
453 *  a debugger such as gdb.  But that is another problem.
454 *
455 *  Port Specific Information:
456 *
457 *  XXX document implementation including references if appropriate
458 */
459
460/**
461 *  @ingroup CPUContext Management
462 *  This defines the minimal set of integer and processor state registers
463 *  that must be saved during a voluntary context switch from one thread
464 *  to another.
465 */
466typedef struct {
467  /** r8 -- temporary register */
468  uint32_t r8;
469  /** r9 -- temporary register */
470  uint32_t r9;
471  /** r10 -- temporary register */
472  uint32_t r10;
473  /** r11 -- temporary register */
474  uint32_t r11;
475  /** r12 -- may be global pointer */
476  uint32_t r12;
477  /** r13 -- frame pointer */
478  uint32_t r13_fp;
479  /** r14 -- link register (aka return pointer */
480  uint32_t r14_lr;
481  /** r15 -- stack pointer */
482  uint32_t r15_sp;
483  /** dsp accumulator low order 32-bits */
484  uint32_t acc_low;
485  /** dsp accumulator high order 32-bits */
486  uint32_t acc_high;
487} Context_Control;
488
489/**
490 *  @ingroup CPUContext Management
491 *
492 *  This macro returns the stack pointer associated with @a _context.
493 *
494 *  @param[in] _context is the thread context area to access
495 *
496 *  @return This method returns the stack pointer.
497 */
498#define _CPU_Context_Get_SP( _context ) \
499  (_context)->r15_sp
500
501/**
502 *  @ingroup CPUContext Management
503 *  This defines the complete set of floating point registers that must
504 *  be saved during any context switch from one thread to another.
505 */
506typedef struct {
507    /** FPU registers are listed here */
508    double      some_float_register;
509} Context_Control_fp;
510
511/**
512 *  @ingroup CPUContext Management
513 *  This defines the set of integer and processor state registers that must
514 *  be saved during an interrupt.  This set does not include any which are
515 *  in @ref Context_Control.
516 */
517typedef struct {
518    /** This field is a hint that a port will have a number of integer
519     *  registers that need to be saved when an interrupt occurs or
520     *  when a context switch occurs at the end of an ISR.
521     */
522    uint32_t   special_interrupt_register;
523} CPU_Interrupt_frame;
524
525/**
526 *  This variable is optional.  It is used on CPUs on which it is difficult
527 *  to generate an "uninitialized" FP context.  It is filled in by
528 *  @ref _CPU_Initialize and copied into the task's FP context area during
529 *  @ref _CPU_Context_Initialize.
530 *
531 *  Port Specific Information:
532 *
533 *  XXX document implementation including references if appropriate
534 */
535SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
536
537/**
538 *  @defgroup CPUInterrupt Processor Dependent Interrupt Management
539 *
540 *  On some CPUs, RTEMS supports a software managed interrupt stack.
541 *  This stack is allocated by the Interrupt Manager and the switch
542 *  is performed in @ref _ISR_Handler.  These variables contain pointers
543 *  to the lowest and highest addresses in the chunk of memory allocated
544 *  for the interrupt stack.  Since it is unknown whether the stack
545 *  grows up or down (in general), this give the CPU dependent
546 *  code the option of picking the version it wants to use.
547 *
548 *  @note These two variables are required if the macro
549 *        @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
550 *
551 *  Port Specific Information:
552 *
553 *  XXX document implementation including references if appropriate
554 */
555
556/*
557 *  Nothing prevents the porter from declaring more CPU specific variables.
558 *
559 *  Port Specific Information:
560 *
561 *  XXX document implementation including references if appropriate
562 */
563
564/* XXX: if needed, put more variables here */
565
566/**
567 *  @ingroup CPUContext
568 *  The size of the floating point context area.  On some CPUs this
569 *  will not be a "sizeof" because the format of the floating point
570 *  area is not defined -- only the size is.  This is usually on
571 *  CPUs with a "floating point save context" instruction.
572 *
573 *  Port Specific Information:
574 *
575 *  XXX document implementation including references if appropriate
576 */
577#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
578
579/**
580 *  Amount of extra stack (above minimum stack size) required by
581 *  MPCI receive server thread.  Remember that in a multiprocessor
582 *  system this thread must exist and be able to process all directives.
583 *
584 *  Port Specific Information:
585 *
586 *  XXX document implementation including references if appropriate
587 */
588#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
589
590/**
591 *  @ingroup CPUInterrupt
592 *  This defines the number of entries in the @ref _ISR_Vector_table managed
593 *  by RTEMS.
594 *
595 *  Port Specific Information:
596 *
597 *  XXX document implementation including references if appropriate
598 */
599#define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
600
601/**
602 *  @ingroup CPUInterrupt
603 *  This defines the highest interrupt vector number for this port.
604 */
605#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
606
607/**
608 *  @ingroup CPUInterrupt
609 *  This is defined if the port has a special way to report the ISR nesting
610 *  level.  Most ports maintain the variable @a _ISR_Nest_level.
611 */
612#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
613
614/**
615 *  @ingroup CPUContext
616 *  Should be large enough to run all RTEMS tests.  This ensures
617 *  that a "reasonable" small application should not have any problems.
618 *
619 *  Port Specific Information:
620 *
621 *  XXX document implementation including references if appropriate
622 */
623#define CPU_STACK_MINIMUM_SIZE          (1024)
624
625/**
626 *  CPU's worst alignment requirement for data types on a byte boundary.  This
627 *  alignment does not take into account the requirements for the stack.
628 *
629 *  Port Specific Information:
630 *
631 *  XXX document implementation including references if appropriate
632 */
633#define CPU_ALIGNMENT              8
634
635/**
636 *  This number corresponds to the byte alignment requirement for the
637 *  heap handler.  This alignment requirement may be stricter than that
638 *  for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
639 *  common for the heap to follow the same alignment requirement as
640 *  @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
641 *  the heap, then this should be set to @ref CPU_ALIGNMENT.
642 *
643 *  @note  This does not have to be a power of 2 although it should be
644 *         a multiple of 2 greater than or equal to 2.  The requirement
645 *         to be a multiple of 2 is because the heap uses the least
646 *         significant field of the front and back flags to indicate
647 *         that a block is in use or free.  So you do not want any odd
648 *         length blocks really putting length data in that bit.
649 *
650 *         On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
651 *         have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
652 *         elements allocated from the heap meet all restrictions.
653 *
654 *  Port Specific Information:
655 *
656 *  XXX document implementation including references if appropriate
657 */
658#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
659
660/**
661 *  This number corresponds to the byte alignment requirement for memory
662 *  buffers allocated by the partition manager.  This alignment requirement
663 *  may be stricter than that for the data types alignment specified by
664 *  @ref CPU_ALIGNMENT.  It is common for the partition to follow the same
665 *  alignment requirement as @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is
666 *  strict enough for the partition, then this should be set to
667 *  @ref CPU_ALIGNMENT.
668 *
669 *  @note  This does not have to be a power of 2.  It does have to
670 *         be greater or equal to than @ref CPU_ALIGNMENT.
671 *
672 *  Port Specific Information:
673 *
674 *  XXX document implementation including references if appropriate
675 */
676#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
677
678/**
679 *  This number corresponds to the byte alignment requirement for the
680 *  stack.  This alignment requirement may be stricter than that for the
681 *  data types alignment specified by @ref CPU_ALIGNMENT.  If the
682 *  @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
683 *  set to 0.
684 *
685 *  @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
686 *
687 *  Port Specific Information:
688 *
689 *  XXX document implementation including references if appropriate
690 */
691#define CPU_STACK_ALIGNMENT        0
692
693/*
694 *  ISR handler macros
695 */
696
697/**
698 *  @ingroup CPUInterrupt
699 *  Support routine to initialize the RTEMS vector table after it is allocated.
700 *
701 *  Port Specific Information:
702 *
703 *  XXX document implementation including references if appropriate
704 */
705#define _CPU_Initialize_vectors()
706
707/**
708 *  @ingroup CPUInterrupt
709 *  Disable all interrupts for an RTEMS critical section.  The previous
710 *  level is returned in @a _isr_cookie.
711 *
712 *  @param[out] _isr_cookie will contain the previous level cookie
713 *
714 *  Port Specific Information:
715 *
716 *  XXX document implementation including references if appropriate
717 */
718#define _CPU_ISR_Disable( _isr_cookie ) \
719  { \
720    (_isr_cookie) = 0;   /* do something to prevent warnings */ \
721  }
722
723/**
724 *  @ingroup CPUInterrupt
725 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
726 *  This indicates the end of an RTEMS critical section.  The parameter
727 *  @a _isr_cookie is not modified.
728 *
729 *  @param[in] _isr_cookie contain the previous level cookie
730 *
731 *  Port Specific Information:
732 *
733 *  XXX document implementation including references if appropriate
734 */
735#define _CPU_ISR_Enable( _isr_cookie )  \
736  { \
737    (_isr_cookie) = 0;   /* do something to prevent warnings */ \
738  }
739
740/**
741 *  @ingroup CPUInterrupt
742 *  This temporarily restores the interrupt to @a _isr_cookie before immediately
743 *  disabling them again.  This is used to divide long RTEMS critical
744 *  sections into two or more parts.  The parameter @a _isr_cookie is not
745 *  modified.
746 *
747 *  @param[in] _isr_cookie contain the previous level cookie
748 *
749 *  Port Specific Information:
750 *
751 *  XXX document implementation including references if appropriate
752 */
753#define _CPU_ISR_Flash( _isr_cookie ) \
754  { \
755  }
756
757/**
758 *  @ingroup CPUInterrupt
759 *
760 *  This routine and @ref _CPU_ISR_Get_level
761 *  Map the interrupt level in task mode onto the hardware that the CPU
762 *  actually provides.  Currently, interrupt levels which do not
763 *  map onto the CPU in a generic fashion are undefined.  Someday,
764 *  it would be nice if these were "mapped" by the application
765 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
766 *  8 - 255 would be available for bsp/application specific meaning.
767 *  This could be used to manage a programmable interrupt controller
768 *  via the rtems_task_mode directive.
769 *
770 *  Port Specific Information:
771 *
772 *  XXX document implementation including references if appropriate
773 */
774#define _CPU_ISR_Set_level( new_level ) \
775  { \
776  }
777
778/**
779 *  @ingroup CPUInterrupt
780 *  Return the current interrupt disable level for this task in
781 *  the format used by the interrupt level portion of the task mode.
782 *
783 *  @note This routine usually must be implemented as a subroutine.
784 *
785 *  Port Specific Information:
786 *
787 *  XXX document implementation including references if appropriate
788 */
789uint32_t   _CPU_ISR_Get_level( void );
790
791/* end of ISR handler macros */
792
793/* Context handler macros */
794
795/**
796 *  @ingroup CPUContext
797 *  Initialize the context to a state suitable for starting a
798 *  task after a context restore operation.  Generally, this
799 *  involves:
800 *
801 *     - setting a starting address
802 *     - preparing the stack
803 *     - preparing the stack and frame pointers
804 *     - setting the proper interrupt level in the context
805 *     - initializing the floating point context
806 *
807 *  This routine generally does not set any unnecessary register
808 *  in the context.  The state of the "general data" registers is
809 *  undefined at task start time.
810 *
811 *  @param[in] _the_context is the context structure to be initialized
812 *  @param[in] _stack_base is the lowest physical address of this task's stack
813 *  @param[in] _size is the size of this task's stack
814 *  @param[in] _isr is the interrupt disable level
815 *  @param[in] _entry_point is the thread's entry point.  This is
816 *         always @a _Thread_Handler
817 *  @param[in] _is_fp is TRUE if the thread is to be a floating
818 *        point thread.  This is typically only used on CPUs where the
819 *        FPU may be easily disabled by software such as on the SPARC
820 *        where the PSR contains an enable FPU bit.
821 *
822 *  Port Specific Information:
823 *
824 *  XXX document implementation including references if appropriate
825 */
826void _CPU_Context_Initialize(
827  Context_Control  *the_context,
828  uint32_t         *stack_base,
829  size_t            size,
830  uint32_t          new_level,
831  void             *entry_point,
832  bool              is_fp
833);
834
835/**
836 *  This routine is responsible for somehow restarting the currently
837 *  executing task.  If you are lucky, then all that is necessary
838 *  is restoring the context.  Otherwise, there will need to be
839 *  a special assembly routine which does something special in this
840 *  case.  For many ports, simply adding a label to the restore path
841 *  of @ref _CPU_Context_switch will work.  On other ports, it may be
842 *  possibly to load a few arguments and jump to the restore path. It will
843 *  not work if restarting self conflicts with the stack frame
844 *  assumptions of restoring a context.
845 *
846 *  Port Specific Information:
847 *
848 *  XXX document implementation including references if appropriate
849 */
850void _CPU_Context_Restart_self(
851  Context_Control  *the_context
852);
853
854/**
855 *  @ingroup CPUContext
856 *  The purpose of this macro is to allow the initial pointer into
857 *  a floating point context area (used to save the floating point
858 *  context) to be at an arbitrary place in the floating point
859 *  context area.
860 *
861 *  This is necessary because some FP units are designed to have
862 *  their context saved as a stack which grows into lower addresses.
863 *  Other FP units can be saved by simply moving registers into offsets
864 *  from the base of the context area.  Finally some FP units provide
865 *  a "dump context" instruction which could fill in from high to low
866 *  or low to high based on the whim of the CPU designers.
867 *
868 *  @param[in] _base is the lowest physical address of the floating point
869 *         context area
870 *  @param[in] _offset is the offset into the floating point area
871 *
872 *  Port Specific Information:
873 *
874 *  XXX document implementation including references if appropriate
875 */
876#define _CPU_Context_Fp_start( _base, _offset ) \
877   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
878
879/**
880 *  This routine initializes the FP context area passed to it to.
881 *  There are a few standard ways in which to initialize the
882 *  floating point context.  The code included for this macro assumes
883 *  that this is a CPU in which a "initial" FP context was saved into
884 *  @a _CPU_Null_fp_context and it simply copies it to the destination
885 *  context passed to it.
886 *
887 *  Other floating point context save/restore models include:
888 *    -# not doing anything, and
889 *    -# putting a "null FP status word" in the correct place in the FP context.
890 *
891 *  @param[in] _destination is the floating point context area
892 *
893 *  Port Specific Information:
894 *
895 *  XXX document implementation including references if appropriate
896 */
897#define _CPU_Context_Initialize_fp( _destination ) \
898  { \
899   *(*(_destination)) = _CPU_Null_fp_context; \
900  }
901
902/* end of Context handler macros */
903
904/* Fatal Error manager macros */
905
906/**
907 *  This routine copies _error into a known place -- typically a stack
908 *  location or a register, optionally disables interrupts, and
909 *  halts/stops the CPU.
910 *
911 *  Port Specific Information:
912 *
913 *  XXX document implementation including references if appropriate
914 */
915#define _CPU_Fatal_halt( _error ) \
916  { \
917  }
918
919/* end of Fatal Error manager macros */
920
921/* Bitfield handler macros */
922
923/**
924 *  @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
925 *
926 *  This set of routines are used to implement fast searches for
927 *  the most important ready task.
928 */
929
930/**
931 *  @ingroup CPUBitfield
932 *  This definition is set to TRUE if the port uses the generic bitfield
933 *  manipulation implementation.
934 */
935#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
936
937/**
938 *  @ingroup CPUBitfield
939 *  This definition is set to TRUE if the port uses the data tables provided
940 *  by the generic bitfield manipulation implementation.
941 *  This can occur when actually using the generic bitfield manipulation
942 *  implementation or when implementing the same algorithm in assembly
943 *  language for improved performance.  It is unlikely that a port will use
944 *  the data if it has a bitfield scan instruction.
945 */
946#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
947
948/**
949 *  @ingroup CPUBitfield
950 *  This routine sets @a _output to the bit number of the first bit
951 *  set in @a _value.  @a _value is of CPU dependent type
952 *  @a Priority_bit_map_Control.  This type may be either 16 or 32 bits
953 *  wide although only the 16 least significant bits will be used.
954 *
955 *  There are a number of variables in using a "find first bit" type
956 *  instruction.
957 *
958 *    -# What happens when run on a value of zero?
959 *    -# Bits may be numbered from MSB to LSB or vice-versa.
960 *    -# The numbering may be zero or one based.
961 *    -# The "find first bit" instruction may search from MSB or LSB.
962 *
963 *  RTEMS guarantees that (1) will never happen so it is not a concern.
964 *  (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
965 *  @ref _CPU_Priority_bits_index.  These three form a set of routines
966 *  which must logically operate together.  Bits in the _value are
967 *  set and cleared based on masks built by @ref _CPU_Priority_Mask.
968 *  The basic major and minor values calculated by @ref _Priority_Major
969 *  and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
970 *  to properly range between the values returned by the "find first bit"
971 *  instruction.  This makes it possible for @ref _Priority_Get_highest to
972 *  calculate the major and directly index into the minor table.
973 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
974 *  is the first bit found.
975 *
976 *  This entire "find first bit" and mapping process depends heavily
977 *  on the manner in which a priority is broken into a major and minor
978 *  components with the major being the 4 MSB of a priority and minor
979 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
980 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
981 *  to the lowest priority.
982 *
983 *  If your CPU does not have a "find first bit" instruction, then
984 *  there are ways to make do without it.  Here are a handful of ways
985 *  to implement this in software:
986 *
987@verbatim
988      - a series of 16 bit test instructions
989      - a "binary search using if's"
990      - _number = 0
991        if _value > 0x00ff
992          _value >>=8
993          _number = 8;
994
995        if _value > 0x0000f
996          _value >=8
997          _number += 4
998
999        _number += bit_set_table[ _value ]
1000@endverbatim
1001
1002 *    where bit_set_table[ 16 ] has values which indicate the first
1003 *      bit set
1004 *
1005 *  @param[in] _value is the value to be scanned
1006 *  @param[in] _output is the first bit set
1007 *
1008 *  Port Specific Information:
1009 *
1010 *  XXX document implementation including references if appropriate
1011 */
1012
1013#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1014#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
1015  { \
1016    (_output) = 0;   /* do something to prevent warnings */ \
1017  }
1018#endif
1019
1020/* end of Bitfield handler macros */
1021
1022/**
1023 *  This routine builds the mask which corresponds to the bit fields
1024 *  as searched by @ref _CPU_Bitfield_Find_first_bit.  See the discussion
1025 *  for that routine.
1026 *
1027 *  Port Specific Information:
1028 *
1029 *  XXX document implementation including references if appropriate
1030 */
1031#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1032
1033#define _CPU_Priority_Mask( _bit_number ) \
1034  ( 1 << (_bit_number) )
1035
1036#endif
1037
1038/**
1039 *  @ingroup CPUBitfield
1040 *  This routine translates the bit numbers returned by
1041 *  @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
1042 *  a major or minor component of a priority.  See the discussion
1043 *  for that routine.
1044 *
1045 *  @param[in] _priority is the major or minor number to translate
1046 *
1047 *  Port Specific Information:
1048 *
1049 *  XXX document implementation including references if appropriate
1050 */
1051#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1052
1053#define _CPU_Priority_bits_index( _priority ) \
1054  (_priority)
1055
1056#endif
1057
1058/* end of Priority handler macros */
1059
1060/* functions */
1061
1062/**
1063 *  This routine performs CPU dependent initialization.
1064 *
1065 *  Port Specific Information:
1066 *
1067 *  XXX document implementation including references if appropriate
1068 */
1069void _CPU_Initialize(void);
1070
1071/**
1072 *  @ingroup CPUInterrupt
1073 *  This routine installs a "raw" interrupt handler directly into the
1074 *  processor's vector table.
1075 *
1076 *  @param[in] vector is the vector number
1077 *  @param[in] new_handler is the raw ISR handler to install
1078 *  @param[in] old_handler is the previously installed ISR Handler
1079 *
1080 *  Port Specific Information:
1081 *
1082 *  XXX document implementation including references if appropriate
1083 */
1084void _CPU_ISR_install_raw_handler(
1085  uint32_t    vector,
1086  proc_ptr    new_handler,
1087  proc_ptr   *old_handler
1088);
1089
1090/**
1091 *  @ingroup CPUInterrupt
1092 *  This routine installs an interrupt vector.
1093 *
1094 *  @param[in] vector is the vector number
1095 *  @param[in] new_handler is the RTEMS ISR handler to install
1096 *  @param[in] old_handler is the previously installed ISR Handler
1097 *
1098 *  Port Specific Information:
1099 *
1100 *  XXX document implementation including references if appropriate
1101 */
1102void _CPU_ISR_install_vector(
1103  uint32_t    vector,
1104  proc_ptr    new_handler,
1105  proc_ptr   *old_handler
1106);
1107
1108/**
1109 *  @ingroup CPUInterrupt
1110 *  This routine installs the hardware interrupt stack pointer.
1111 *
1112 *  @note  It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
1113 *         is TRUE.
1114 *
1115 *  Port Specific Information:
1116 *
1117 *  XXX document implementation including references if appropriate
1118 */
1119void _CPU_Install_interrupt_stack( void );
1120
1121/**
1122 *  @ingroup CPUContext
1123 *  This routine switches from the run context to the heir context.
1124 *
1125 *  @param[in] run points to the context of the currently executing task
1126 *  @param[in] heir points to the context of the heir task
1127 *
1128 *  Port Specific Information:
1129 *
1130 *  XXX document implementation including references if appropriate
1131 */
1132void _CPU_Context_switch(
1133  Context_Control  *run,
1134  Context_Control  *heir
1135);
1136
1137/**
1138 *  @ingroup CPUContext
1139 *  This routine is generally used only to restart self in an
1140 *  efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
1141 *
1142 *  @param[in] new_context points to the context to be restored.
1143 *
1144 *  @note May be unnecessary to reload some registers.
1145 *
1146 *  Port Specific Information:
1147 *
1148 *  XXX document implementation including references if appropriate
1149 */
1150void _CPU_Context_restore(
1151  Context_Control *new_context
1152);
1153
1154/**
1155 *  @ingroup CPUContext
1156 *  This routine saves the floating point context passed to it.
1157 *
1158 *  @param[in] fp_context_ptr is a pointer to a pointer to a floating
1159 *  point context area
1160 *
1161 *  @return on output @a *fp_context_ptr will contain the address that
1162 *  should be used with @ref _CPU_Context_restore_fp to restore this context.
1163 *
1164 *  Port Specific Information:
1165 *
1166 *  XXX document implementation including references if appropriate
1167 */
1168void _CPU_Context_save_fp(
1169  Context_Control_fp **fp_context_ptr
1170);
1171
1172/**
1173 *  @ingroup CPUContext
1174 *  This routine restores the floating point context passed to it.
1175 *
1176 *  @param[in] fp_context_ptr is a pointer to a pointer to a floating
1177 *  point context area to restore
1178 *
1179 *  @return on output @a *fp_context_ptr will contain the address that
1180 *  should be used with @ref _CPU_Context_save_fp to save this context.
1181 *
1182 *  Port Specific Information:
1183 *
1184 *  XXX document implementation including references if appropriate
1185 */
1186void _CPU_Context_restore_fp(
1187  Context_Control_fp **fp_context_ptr
1188);
1189
1190/**
1191 *  @ingroup CPUEndian
1192 *  The following routine swaps the endian format of an unsigned int.
1193 *  It must be static because it is referenced indirectly.
1194 *
1195 *  This version will work on any processor, but if there is a better
1196 *  way for your CPU PLEASE use it.  The most common way to do this is to:
1197 *
1198 *     swap least significant two bytes with 16-bit rotate
1199 *     swap upper and lower 16-bits
1200 *     swap most significant two bytes with 16-bit rotate
1201 *
1202 *  Some CPUs have special instructions which swap a 32-bit quantity in
1203 *  a single instruction (e.g. i486).  It is probably best to avoid
1204 *  an "endian swapping control bit" in the CPU.  One good reason is
1205 *  that interrupts would probably have to be disabled to ensure that
1206 *  an interrupt does not try to access the same "chunk" with the wrong
1207 *  endian.  Another good reason is that on some CPUs, the endian bit
1208 *  endianness for ALL fetches -- both code and data -- so the code
1209 *  will be fetched incorrectly.
1210 *
1211 *  @param[in] value is the value to be swapped
1212 *  @return the value after being endian swapped
1213 *
1214 *  Port Specific Information:
1215 *
1216 *  XXX document implementation including references if appropriate
1217 */
1218static inline uint32_t CPU_swap_u32(
1219  uint32_t value
1220)
1221{
1222  uint32_t byte1, byte2, byte3, byte4, swapped;
1223
1224  byte4 = (value >> 24) & 0xff;
1225  byte3 = (value >> 16) & 0xff;
1226  byte2 = (value >> 8)  & 0xff;
1227  byte1 =  value        & 0xff;
1228
1229  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1230  return swapped;
1231}
1232
1233/**
1234 *  @ingroup CPUEndian
1235 *  This routine swaps a 16 bir quantity.
1236 *
1237 *  @param[in] value is the value to be swapped
1238 *  @return the value after being endian swapped
1239 */
1240#define CPU_swap_u16( value ) \
1241  (((value&0xff) << 8) | ((value >> 8)&0xff))
1242
1243#ifdef __cplusplus
1244}
1245#endif
1246
1247#endif
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