source: rtems/cpukit/score/cpu/m32r/cpu_asm.c @ 4990792

4.104.11
Last change on this file since 4990792 was 4990792, checked in by Joel Sherrill <joel.sherrill@…>, on Mar 27, 2010 at 3:02:02 PM

2010-03-27 Joel Sherrill <joel.sherrill@…>

  • context_init.c, context_switch.S, cpu.c, cpu_asm.c: Add include of config.h
  • Property mode set to 100644
File size: 3.1 KB
Line 
1/*  cpu_asm.c  ===> cpu_asm.S or cpu_asm.s
2 *
3 *  NOTE:  This is supposed to be a .S or .s file NOT a C file.
4 *
5 *  M32R does not yet have interrupt support.  When this functionality
6 *  is written, this file should become obsolete.
7 *
8 *  COPYRIGHT (c) 1989-2008.
9 *  On-Line Applications Research Corporation (OAR).
10 *
11 *  The license and distribution terms for this file may be
12 *  found in the file LICENSE in this distribution or at
13 *  http://www.rtems.com/license/LICENSE.
14 *
15 *  $Id$
16 */
17
18#ifdef HAVE_CONFIG_H
19#include "config.h"
20#endif
21
22#include <rtems/system.h>
23#include <rtems/score/cpu.h>
24
25/*  void __ISR_Handler()
26 *
27 *  This routine provides the RTEMS interrupt management.
28 *
29 *  NO_CPU Specific Information:
30 *
31 *  XXX document implementation including references if appropriate
32 */
33
34void _ISR_Handler(void)
35{
36   /*
37    *  This discussion ignores a lot of the ugly details in a real
38    *  implementation such as saving enough registers/state to be
39    *  able to do something real.  Keep in mind that the goal is
40    *  to invoke a user's ISR handler which is written in C and
41    *  uses a certain set of registers.
42    *
43    *  Also note that the exact order is to a large extent flexible.
44    *  Hardware will dictate a sequence for a certain subset of
45    *  _ISR_Handler while requirements for setting
46    */
47
48  /*
49   *  At entry to "common" _ISR_Handler, the vector number must be
50   *  available.  On some CPUs the hardware puts either the vector
51   *  number or the offset into the vector table for this ISR in a
52   *  known place.  If the hardware does not give us this information,
53   *  then the assembly portion of RTEMS for this port will contain
54   *  a set of distinct interrupt entry points which somehow place
55   *  the vector number in a known place (which is safe if another
56   *  interrupt nests this one) and branches to _ISR_Handler.
57   *
58   *  save some or all context on stack
59   *  may need to save some special interrupt information for exit
60   *
61   *  #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
62   *    if ( _ISR_Nest_level == 0 )
63   *      switch to software interrupt stack
64   *  #endif
65   *
66   *  _ISR_Nest_level++;
67   *
68   *  _Thread_Dispatch_disable_level++;
69   *
70   *  (*_ISR_Vector_table[ vector ])( vector );
71   *
72   *  _Thread_Dispatch_disable_level--;
73   *
74   *  --_ISR_Nest_level;
75   *
76   *  if ( _ISR_Nest_level )
77   *    goto the label "exit interrupt (simple case)"
78   *
79   *  if ( _Thread_Dispatch_disable_level )
80   *    _ISR_Signals_to_thread_executing = FALSE;
81   *    goto the label "exit interrupt (simple case)"
82   *
83   *  if ( _Context_Switch_necessary || _ISR_Signals_to_thread_executing ) {
84   *    _ISR_Signals_to_thread_executing = FALSE;
85   *    call _Thread_Dispatch() or prepare to return to _ISR_Dispatch
86   *    prepare to get out of interrupt
87   *    return from interrupt  (maybe to _ISR_Dispatch)
88   *
89   *  LABEL "exit interrupt (simple case):
90   *  #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
91   *    if outermost interrupt
92   *      restore stack
93   *  #endif
94   *  prepare to get out of interrupt
95   *  return from interrupt
96   */
97}
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