[0e5b446] | 1 | /* |
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| 2 | * M32R CPU Dependent Source |
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| 3 | * |
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| 4 | * COPYRIGHT (c) 1989-2008. |
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| 5 | * On-Line Applications Research Corporation (OAR). |
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| 6 | * |
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| 7 | * The license and distribution terms for this file may be |
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| 8 | * found in the file LICENSE in this distribution or at |
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| 9 | * http://www.rtems.com/license/LICENSE. |
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| 10 | * |
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| 11 | * $Id$ |
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| 12 | */ |
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| 13 | |
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[4990792] | 14 | #ifdef HAVE_CONFIG_H |
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| 15 | #include "config.h" |
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| 16 | #endif |
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| 17 | |
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[0e5b446] | 18 | #include <rtems/system.h> |
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| 19 | #include <rtems/score/isr.h> |
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| 20 | |
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| 21 | /* _CPU_Initialize |
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| 22 | * |
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| 23 | * This routine performs processor dependent initialization. |
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| 24 | * |
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[c03e2bc] | 25 | * INPUT PARAMETERS: NONE |
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[0e5b446] | 26 | * |
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| 27 | * NO_CPU Specific Information: |
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| 28 | * |
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| 29 | * XXX document implementation including references if appropriate |
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| 30 | */ |
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[c03e2bc] | 31 | |
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| 32 | void _CPU_Initialize(void) |
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[0e5b446] | 33 | { |
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| 34 | } |
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| 35 | |
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| 36 | /* |
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| 37 | * This routine returns the current interrupt level. |
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| 38 | * |
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| 39 | * NO_CPU Specific Information: |
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| 40 | * |
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| 41 | * XXX document implementation including references if appropriate |
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| 42 | */ |
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[5bb38e15] | 43 | |
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[0e5b446] | 44 | uint32_t _CPU_ISR_Get_level( void ) |
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| 45 | { |
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| 46 | return 0; |
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| 47 | } |
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| 48 | |
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| 49 | /*PAGE |
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| 50 | * |
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| 51 | * _CPU_ISR_install_raw_handler |
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| 52 | * |
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| 53 | * NO_CPU Specific Information: |
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| 54 | * |
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| 55 | * XXX document implementation including references if appropriate |
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| 56 | */ |
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[5bb38e15] | 57 | |
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[0e5b446] | 58 | void _CPU_ISR_install_raw_handler( |
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| 59 | uint32_t vector, |
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| 60 | proc_ptr new_handler, |
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| 61 | proc_ptr *old_handler |
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| 62 | ) |
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| 63 | { |
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| 64 | /* |
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| 65 | * This is where we install the interrupt handler into the "raw" interrupt |
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| 66 | * table used by the CPU to dispatch interrupt handlers. |
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| 67 | */ |
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| 68 | /* _set_var_vect(new_handler,vector); */ |
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| 69 | } |
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| 70 | |
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| 71 | /*PAGE |
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| 72 | * |
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| 73 | * _CPU_ISR_install_vector |
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| 74 | * |
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| 75 | * This kernel routine installs the RTEMS handler for the |
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| 76 | * specified vector. |
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| 77 | * |
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| 78 | * Input parameters: |
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| 79 | * vector - interrupt vector number |
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| 80 | * old_handler - former ISR for this vector number |
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| 81 | * new_handler - replacement ISR for this vector number |
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| 82 | * |
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| 83 | * Output parameters: NONE |
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| 84 | * |
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| 85 | * |
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| 86 | * NO_CPU Specific Information: |
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| 87 | * |
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| 88 | * XXX document implementation including references if appropriate |
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| 89 | */ |
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| 90 | |
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| 91 | void _CPU_ISR_install_vector( |
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| 92 | uint32_t vector, |
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| 93 | proc_ptr new_handler, |
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| 94 | proc_ptr *old_handler |
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| 95 | ) |
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| 96 | { |
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| 97 | *old_handler = _ISR_Vector_table[ vector ]; |
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| 98 | |
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| 99 | /* |
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| 100 | * If the interrupt vector table is a table of pointer to isr entry |
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| 101 | * points, then we need to install the appropriate RTEMS interrupt |
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| 102 | * handler for this vector number. |
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| 103 | */ |
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| 104 | |
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| 105 | _CPU_ISR_install_raw_handler( vector, new_handler, old_handler ); |
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| 106 | |
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| 107 | /* |
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| 108 | * We put the actual user ISR address in '_ISR_vector_table'. This will |
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| 109 | * be used by the _ISR_Handler so the user gets control. |
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| 110 | */ |
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| 111 | |
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| 112 | _ISR_Vector_table[ vector ] = new_handler; |
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| 113 | } |
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| 114 | |
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| 115 | /*PAGE |
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| 116 | * |
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| 117 | * _CPU_Install_interrupt_stack |
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| 118 | * |
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| 119 | * NO_CPU Specific Information: |
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| 120 | * |
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| 121 | * XXX document implementation including references if appropriate |
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| 122 | */ |
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| 123 | |
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| 124 | void _CPU_Install_interrupt_stack( void ) |
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| 125 | { |
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| 126 | } |
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