source: rtems/cpukit/score/cpu/m32c/rtems/score/cpu.h @ f82752a4

4.115
Last change on this file since f82752a4 was f82752a4, checked in by Daniel Hellstrom <daniel@…>, on 06/04/14 at 09:23:34

Let CPU/BSP Fatal handler have access to source

Without the source the error code does not say that much.
Let it be up to the CPU/BSP to determine the error code
reported on fatal shutdown.

This patch does not change the current behaviour, just
adds the option to handle the source of the fatal halt.

  • Property mode set to 100644
File size: 39.0 KB
RevLine 
[ed6e947]1/**
[d9e0006]2 * @file
3 *
4 * @brief M32C CPU Dependent Source
[ed6e947]5 */
6
7/*
8 *  This include file contains information pertaining to the XXX
9 *  processor.
10 *
11 *  @note This file is part of a porting template that is intended
12 *  to be used as the starting point when porting RTEMS to a new
13 *  CPU family.  The following needs to be done when using this as
14 *  the starting point for a new port:
15 *
16 *  + Anywhere there is an XXX, it should be replaced
17 *    with information about the CPU family being ported to.
[28352fae]18 *
[ed6e947]19 *  + At the end of each comment section, there is a heading which
20 *    says "Port Specific Information:".  When porting to RTEMS,
21 *    add CPU family specific information in this section
22 */
23
24/*
25 *  COPYRIGHT (c) 1989-2008.
26 *  On-Line Applications Research Corporation (OAR).
27 *
28 *  The license and distribution terms for this file may be
29 *  found in the file LICENSE in this distribution or at
[c499856]30 *  http://www.rtems.org/license/LICENSE.
[ed6e947]31 */
32
33#ifndef _RTEMS_SCORE_CPU_H
34#define _RTEMS_SCORE_CPU_H
35
36#ifdef __cplusplus
37extern "C" {
38#endif
39
40#include <rtems/score/types.h>
[89b85e51]41#include <rtems/score/m32c.h>
[ed6e947]42
43/* conditional compilation parameters */
44
[9cf17fb]45#define RTEMS_USE_16_BIT_OBJECT
46
[ed6e947]47/**
[d9e0006]48 * Should the calls to @ref _Thread_Enable_dispatch be inlined?
[ed6e947]49 *
[d9e0006]50 * If TRUE, then they are inlined.
51 * If FALSE, then a subroutine call is made.
[ed6e947]52 *
[d9e0006]53 * This conditional is an example of the classic trade-off of size
54 * versus speed.  Inlining the call (TRUE) typically increases the
55 * size of RTEMS while speeding up the enabling of dispatching.
[ed6e947]56 *
[d9e0006]57 * NOTE: In general, the @ref _Thread_Dispatch_disable_level will
58 * only be 0 or 1 unless you are in an interrupt handler and that
59 * interrupt handler invokes the executive.]  When not inlined
60 * something calls @ref _Thread_Enable_dispatch which in turns calls
61 * @ref _Thread_Dispatch.  If the enable dispatch is inlined, then
62 * one subroutine call is avoided entirely.
[ed6e947]63 *
[d9e0006]64 * Port Specific Information:
[ed6e947]65 *
[d9e0006]66 * XXX document implementation including references if appropriate
[ed6e947]67 */
68#define CPU_INLINE_ENABLE_DISPATCH       FALSE
69
70/**
[d9e0006]71 * Should the body of the search loops in _Thread_queue_Enqueue_priority
72 * be unrolled one time?  In unrolled each iteration of the loop examines
73 * two "nodes" on the chain being searched.  Otherwise, only one node
74 * is examined per iteration.
[ed6e947]75 *
[d9e0006]76 * If TRUE, then the loops are unrolled.
77 * If FALSE, then the loops are not unrolled.
[ed6e947]78 *
[d9e0006]79 * The primary factor in making this decision is the cost of disabling
80 * and enabling interrupts (_ISR_Flash) versus the cost of rest of the
81 * body of the loop.  On some CPUs, the flash is more expensive than
82 * one iteration of the loop body.  In this case, it might be desirable
83 * to unroll the loop.  It is important to note that on some CPUs, this
84 * code is the longest interrupt disable period in RTEMS.  So it is
85 * necessary to strike a balance when setting this parameter.
86 *
87 * Port Specific Information:
88 *
89 * XXX document implementation including references if appropriate
[ed6e947]90 */
91#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
92
93/**
[d9e0006]94 * Does RTEMS manage a dedicated interrupt stack in software?
[ed6e947]95 *
[d9e0006]96 * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
97 * If FALSE, nothing is done.
[ed6e947]98 *
[d9e0006]99 * If the CPU supports a dedicated interrupt stack in hardware,
100 * then it is generally the responsibility of the BSP to allocate it
101 * and set it up.
[ed6e947]102 *
[d9e0006]103 * If the CPU does not support a dedicated interrupt stack, then
104 * the porter has two options: (1) execute interrupts on the
105 * stack of the interrupted task, and (2) have RTEMS manage a dedicated
106 * interrupt stack.
[ed6e947]107 *
[d9e0006]108 * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
[ed6e947]109 *
[d9e0006]110 * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
111 * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
112 * possible that both are FALSE for a particular CPU.  Although it
113 * is unclear what that would imply about the interrupt processing
114 * procedure on that CPU.
[ed6e947]115 *
[d9e0006]116 * Port Specific Information:
[ed6e947]117 *
[d9e0006]118 * XXX document implementation including references if appropriate
[ed6e947]119 */
120#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
121
122/**
[d9e0006]123 * Does the CPU follow the simple vectored interrupt model?
[ed6e947]124 *
[d9e0006]125 * If TRUE, then RTEMS allocates the vector table it internally manages.
126 * If FALSE, then the BSP is assumed to allocate and manage the vector
127 * table
[ed6e947]128 *
[d9e0006]129 * Port Specific Information:
[ed6e947]130 *
[d9e0006]131 * XXX document implementation including references if appropriate
[ed6e947]132 */
133#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
134
135/**
[d9e0006]136 * Does this CPU have hardware support for a dedicated interrupt stack?
[ed6e947]137 *
[d9e0006]138 * If TRUE, then it must be installed during initialization.
139 * If FALSE, then no installation is performed.
[ed6e947]140 *
[d9e0006]141 * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
[ed6e947]142 *
[d9e0006]143 * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
144 * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
145 * possible that both are FALSE for a particular CPU.  Although it
146 * is unclear what that would imply about the interrupt processing
147 * procedure on that CPU.
[ed6e947]148 *
[d9e0006]149 * Port Specific Information:
[ed6e947]150 *
[d9e0006]151 * XXX document implementation including references if appropriate
[ed6e947]152 */
153#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
154
155/**
[d9e0006]156 * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
[ed6e947]157 *
[d9e0006]158 * If TRUE, then the memory is allocated during initialization.
159 * If FALSE, then the memory is allocated during initialization.
[ed6e947]160 *
[d9e0006]161 * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
[ed6e947]162 *
[d9e0006]163 * Port Specific Information:
[ed6e947]164 *
[d9e0006]165 * XXX document implementation including references if appropriate
[ed6e947]166 */
167#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
168
169/**
[d9e0006]170 * Does the RTEMS invoke the user's ISR with the vector number and
171 * a pointer to the saved interrupt frame (1) or just the vector
172 * number (0)?
[ed6e947]173 *
[d9e0006]174 * Port Specific Information:
[ed6e947]175 *
[d9e0006]176 * XXX document implementation including references if appropriate
[ed6e947]177 */
178#define CPU_ISR_PASSES_FRAME_POINTER 0
179
180/**
[d9e0006]181 * @def CPU_HARDWARE_FP
[ed6e947]182 *
[d9e0006]183 * Does the CPU have hardware floating point?
[ed6e947]184 *
[d9e0006]185 * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
186 * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
[ed6e947]187 *
[d9e0006]188 * If there is a FP coprocessor such as the i387 or mc68881, then
189 * the answer is TRUE.
[ed6e947]190 *
[d9e0006]191 * The macro name "M32C_HAS_FPU" should be made CPU specific.
192 * It indicates whether or not this CPU model has FP support.  For
193 * example, it would be possible to have an i386_nofp CPU model
194 * which set this to false to indicate that you have an i386 without
195 * an i387 and wish to leave floating point support out of RTEMS.
[ed6e947]196 */
197
[28352fae]198/**
[d9e0006]199 * @def CPU_SOFTWARE_FP
[ed6e947]200 *
[d9e0006]201 * Does the CPU have no hardware floating point and GCC provides a
202 * software floating point implementation which must be context
203 * switched?
[ed6e947]204 *
[d9e0006]205 * This feature conditional is used to indicate whether or not there
206 * is software implemented floating point that must be context
207 * switched.  The determination of whether or not this applies
208 * is very tool specific and the state saved/restored is also
209 * compiler specific.
[ed6e947]210 *
[d9e0006]211 * Port Specific Information:
[ed6e947]212 *
[d9e0006]213 * XXX document implementation including references if appropriate
[ed6e947]214 */
215#if ( M32C_HAS_FPU == 1 )
216#define CPU_HARDWARE_FP     TRUE
217#else
218#define CPU_HARDWARE_FP     FALSE
219#endif
220#define CPU_SOFTWARE_FP     FALSE
221
222#define CPU_CONTEXT_FP_SIZE 0
223
224/**
[d9e0006]225 * Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
[ed6e947]226 *
[d9e0006]227 * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
228 * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
[ed6e947]229 *
[d9e0006]230 * So far, the only CPUs in which this option has been used are the
231 * HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
232 * gcc both implicitly used the floating point registers to perform
233 * integer multiplies.  Similarly, the PowerPC port of gcc has been
234 * seen to allocate floating point local variables and touch the FPU
235 * even when the flow through a subroutine (like vfprintf()) might
236 * not use floating point formats.
[ed6e947]237 *
[d9e0006]238 * If a function which you would not think utilize the FP unit DOES,
239 * then one can not easily predict which tasks will use the FP hardware.
240 * In this case, this option should be TRUE.
[ed6e947]241 *
[d9e0006]242 * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
[ed6e947]243 *
[d9e0006]244 * Port Specific Information:
[ed6e947]245 *
[d9e0006]246 * XXX document implementation including references if appropriate
[ed6e947]247 */
248#define CPU_ALL_TASKS_ARE_FP     TRUE
249
250/**
[d9e0006]251 * Should the IDLE task have a floating point context?
[ed6e947]252 *
[d9e0006]253 * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
254 * and it has a floating point context which is switched in and out.
255 * If FALSE, then the IDLE task does not have a floating point context.
[ed6e947]256 *
[d9e0006]257 * Setting this to TRUE negatively impacts the time required to preempt
258 * the IDLE task from an interrupt because the floating point context
259 * must be saved as part of the preemption.
[ed6e947]260 *
[d9e0006]261 * Port Specific Information:
[ed6e947]262 *
[d9e0006]263 * XXX document implementation including references if appropriate
[ed6e947]264 */
265#define CPU_IDLE_TASK_IS_FP      FALSE
266
267/**
[d9e0006]268 * Should the saving of the floating point registers be deferred
269 * until a context switch is made to another different floating point
270 * task?
[ed6e947]271 *
[d9e0006]272 * If TRUE, then the floating point context will not be stored until
273 * necessary.  It will remain in the floating point registers and not
274 * disturned until another floating point task is switched to.
[ed6e947]275 *
[d9e0006]276 * If FALSE, then the floating point context is saved when a floating
277 * point task is switched out and restored when the next floating point
278 * task is restored.  The state of the floating point registers between
279 * those two operations is not specified.
280 *
281 * If the floating point context does NOT have to be saved as part of
282 * interrupt dispatching, then it should be safe to set this to TRUE.
283 *
284 * Setting this flag to TRUE results in using a different algorithm
285 * for deciding when to save and restore the floating point context.
286 * The deferred FP switch algorithm minimizes the number of times
287 * the FP context is saved and restored.  The FP context is not saved
288 * until a context switch is made to another, different FP task.
289 * Thus in a system with only one FP task, the FP context will never
290 * be saved or restored.
291 *
292 * Port Specific Information:
293 *
294 * XXX document implementation including references if appropriate
[ed6e947]295 */
296#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
297
298/**
[d9e0006]299 * Does this port provide a CPU dependent IDLE task implementation?
[ed6e947]300 *
[d9e0006]301 * If TRUE, then the routine @ref _CPU_Thread_Idle_body
302 * must be provided and is the default IDLE thread body instead of
303 * @ref _CPU_Thread_Idle_body.
[ed6e947]304 *
[d9e0006]305 * If FALSE, then use the generic IDLE thread body if the BSP does
306 * not provide one.
[ed6e947]307 *
[d9e0006]308 * This is intended to allow for supporting processors which have
309 * a low power or idle mode.  When the IDLE thread is executed, then
310 * the CPU can be powered down.
[ed6e947]311 *
[d9e0006]312 * The order of precedence for selecting the IDLE thread body is:
[ed6e947]313 *
[d9e0006]314 *   -#  BSP provided
315 *   -#  CPU dependent (if provided)
316 *   -#  generic (if no BSP and no CPU dependent)
[ed6e947]317 *
[d9e0006]318 * Port Specific Information:
[ed6e947]319 *
[d9e0006]320 * XXX document implementation including references if appropriate
[ed6e947]321 */
322#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
323
324/**
[d9e0006]325 * Does the stack grow up (toward higher addresses) or down
326 * (toward lower addresses)?
[ed6e947]327 *
[d9e0006]328 * If TRUE, then the grows upward.
329 * If FALSE, then the grows toward smaller addresses.
[ed6e947]330 *
[d9e0006]331 * Port Specific Information:
[ed6e947]332 *
[d9e0006]333 * XXX document implementation including references if appropriate
[ed6e947]334 */
335#define CPU_STACK_GROWS_UP               TRUE
336
337/**
[d9e0006]338 * The following is the variable attribute used to force alignment
339 * of critical RTEMS structures.  On some processors it may make
340 * sense to have these aligned on tighter boundaries than
341 * the minimum requirements of the compiler in order to have as
342 * much of the critical data area as possible in a cache line.
[ed6e947]343 *
[d9e0006]344 * The placement of this macro in the declaration of the variables
345 * is based on the syntactically requirements of the GNU C
346 * "__attribute__" extension.  For example with GNU C, use
347 * the following to force a structures to a 32 byte boundary.
[ed6e947]348 *
[d9e0006]349 *     __attribute__ ((aligned (32)))
[ed6e947]350 *
[d9e0006]351 * NOTE: Currently only the Priority Bit Map table uses this feature.
352 *       To benefit from using this, the data must be heavily
353 *       used so it will stay in the cache and used frequently enough
354 *       in the executive to justify turning this on.
[ed6e947]355 *
[d9e0006]356 * Port Specific Information:
[ed6e947]357 *
[d9e0006]358 * XXX document implementation including references if appropriate
[ed6e947]359 */
[f517be0]360#define CPU_STRUCTURE_ALIGNMENT          __attribute__ ((aligned (2)))
361
[9c121991]362#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE
[ed6e947]363
364/**
[d9e0006]365 * @defgroup CPUEndian Processor Dependent Endianness Support
[ed6e947]366 *
[d9e0006]367 * This group assists in issues related to processor endianness.
368 *
[ed6e947]369 */
[b697bc6]370/**@{**/
[ed6e947]371
372/**
[d9e0006]373 * Define what is required to specify how the network to host conversion
374 * routines are handled.
[ed6e947]375 *
[d9e0006]376 * NOTE: @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
377 * same values.
[ed6e947]378 *
[d9e0006]379 * @see CPU_LITTLE_ENDIAN
[ed6e947]380 *
[d9e0006]381 * Port Specific Information:
[ed6e947]382 *
[d9e0006]383 * XXX document implementation including references if appropriate
[ed6e947]384 */
385#define CPU_BIG_ENDIAN                           TRUE
386
387/**
[d9e0006]388 * Define what is required to specify how the network to host conversion
389 * routines are handled.
[ed6e947]390 *
[d9e0006]391 * NOTE: @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
392 * same values.
[ed6e947]393 *
[d9e0006]394 * @see CPU_BIG_ENDIAN
[ed6e947]395 *
[d9e0006]396 * Port Specific Information:
[ed6e947]397 *
[d9e0006]398 * XXX document implementation including references if appropriate
[ed6e947]399 */
400#define CPU_LITTLE_ENDIAN                        FALSE
401
[d9e0006]402/** @} */
403
[ed6e947]404/**
[d9e0006]405 * @ingroup CPUInterrupt
406 *
407 * The following defines the number of bits actually used in the
408 * interrupt field of the task mode.  How those bits map to the
409 * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
[ed6e947]410 *
[d9e0006]411 * Port Specific Information:
[ed6e947]412 *
[d9e0006]413 * XXX document implementation including references if appropriate
[ed6e947]414 */
415#define CPU_MODES_INTERRUPT_MASK   0x00000001
416
[10fd4aac]417#define CPU_PER_CPU_CONTROL_SIZE 0
418
[ed6e947]419/*
420 *  Processor defined structures required for cpukit/score.
421 *
422 *  Port Specific Information:
423 *
424 *  XXX document implementation including references if appropriate
425 */
426
427/* may need to put some structures here.  */
428
[10fd4aac]429typedef struct {
430  /* There is no CPU specific per-CPU state */
431} CPU_Per_CPU_control;
432
[ed6e947]433/**
434 * @defgroup CPUContext Processor Dependent Context Management
435 *
[d9e0006]436 * From the highest level viewpoint, there are 2 types of context to save.
[ed6e947]437 *
[d9e0006]438 *    -# Interrupt registers to save
439 *    -# Task level registers to save
[ed6e947]440 *
[d9e0006]441 * Since RTEMS handles integer and floating point contexts separately, this
442 * means we have the following 3 context items:
[ed6e947]443 *
[d9e0006]444 *    -# task level context stuff::  Context_Control
445 *    -# floating point task stuff:: Context_Control_fp
446 *    -# special interrupt level context :: CPU_Interrupt_frame
[ed6e947]447 *
[d9e0006]448 * On some processors, it is cost-effective to save only the callee
449 * preserved registers during a task context switch.  This means
450 * that the ISR code needs to save those registers which do not
451 * persist across function calls.  It is not mandatory to make this
452 * distinctions between the caller/callee saves registers for the
453 * purpose of minimizing context saved during task switch and on interrupts.
454 * If the cost of saving extra registers is minimal, simplicity is the
455 * choice.  Save the same context on interrupt entry as for tasks in
456 * this case.
[ed6e947]457 *
[d9e0006]458 * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
459 * care should be used in designing the context area.
[ed6e947]460 *
[d9e0006]461 * On some CPUs with hardware floating point support, the Context_Control_fp
462 * structure will not be used or it simply consist of an array of a
463 * fixed number of bytes.   This is done when the floating point context
464 * is dumped by a "FP save context" type instruction and the format
465 * is not really defined by the CPU.  In this case, there is no need
466 * to figure out the exact format -- only the size.  Of course, although
467 * this is enough information for RTEMS, it is probably not enough for
468 * a debugger such as gdb.  But that is another problem.
[ed6e947]469 *
[d9e0006]470 * Port Specific Information:
[ed6e947]471 *
[d9e0006]472 * XXX document implementation including references if appropriate
[ed6e947]473 */
[b697bc6]474/**@{**/
[ed6e947]475
476/**
[d9e0006]477 * @ingroup Management
478 *
479 * This defines the minimal set of integer and processor state registers
480 * that must be saved during a voluntary context switch from one thread
481 * to another.
[ed6e947]482 */
483typedef struct {
484  /** This will contain the stack pointer. */
485  uint32_t sp;
486  /** This will contain the frame base pointer. */
487  uint32_t fb;
488} Context_Control;
489
490/**
[d9e0006]491 * @ingroup Management
[ed6e947]492 *
[d9e0006]493 * This macro returns the stack pointer associated with @a _context.
[ed6e947]494 *
[d9e0006]495 * @param[in] _context is the thread context area to access
[28352fae]496 *
[d9e0006]497 * @return This method returns the stack pointer.
[ed6e947]498 */
499#define _CPU_Context_Get_SP( _context ) \
500  (_context)->sp
501
502/**
[d9e0006]503 * @ingroup Management
504 *
505 * This defines the set of integer and processor state registers that must
506 * be saved during an interrupt.  This set does not include any which are
507 * in @ref Context_Control.
[ed6e947]508 */
509typedef struct {
[d9e0006]510    /**
511     * This field is a hint that a port will have a number of integer
512     * registers that need to be saved when an interrupt occurs or
513     * when a context switch occurs at the end of an ISR.
[ed6e947]514     */
515    uint32_t   special_interrupt_register;
516} CPU_Interrupt_frame;
517
[d9e0006]518/** @} */
519
[ed6e947]520/**
[d9e0006]521 * @defgroup CPUInterrupt Processor Dependent Interrupt Management
[ed6e947]522 *
[d9e0006]523 * On some CPUs, RTEMS supports a software managed interrupt stack.
524 * This stack is allocated by the Interrupt Manager and the switch
525 * is performed in @ref _ISR_Handler.  These variables contain pointers
526 * to the lowest and highest addresses in the chunk of memory allocated
527 * for the interrupt stack.  Since it is unknown whether the stack
528 * grows up or down (in general), this give the CPU dependent
529 * code the option of picking the version it wants to use.
[ed6e947]530 *
[d9e0006]531 * NOTE: These two variables are required if the macro
532 *       @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
[ed6e947]533 *
[d9e0006]534 * Port Specific Information:
[ed6e947]535 *
[d9e0006]536 * XXX document implementation including references if appropriate
537 *
[ed6e947]538 */
[b697bc6]539/**@{**/
[ed6e947]540
541/*
542 *  Nothing prevents the porter from declaring more CPU specific variables.
543 *
544 *  Port Specific Information:
545 *
546 *  XXX document implementation including references if appropriate
547 */
548
549/* XXX: if needed, put more variables here */
550
551/**
[d9e0006]552 * Amount of extra stack (above minimum stack size) required by
553 * MPCI receive server thread.  Remember that in a multiprocessor
554 * system this thread must exist and be able to process all directives.
[ed6e947]555 *
[d9e0006]556 * Port Specific Information:
[ed6e947]557 *
[d9e0006]558 * XXX document implementation including references if appropriate
[ed6e947]559 */
560#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
561
562/**
[d9e0006]563 * This defines the number of entries in the @ref _ISR_Vector_table managed
564 * by RTEMS.
[ed6e947]565 *
[d9e0006]566 * Port Specific Information:
[ed6e947]567 *
[d9e0006]568 * XXX document implementation including references if appropriate
[ed6e947]569 */
570#define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
571
[d9e0006]572/** This defines the highest interrupt vector number for this port. */
[ed6e947]573#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
574
575/**
[d9e0006]576 * This is defined if the port has a special way to report the ISR nesting
577 * level.  Most ports maintain the variable @a _ISR_Nest_level.
[ed6e947]578 */
579#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
580
[d9e0006]581/** @} */
582
[ed6e947]583/**
[d9e0006]584 * @ingroup CPUContext
585 *
586 * Should be large enough to run all RTEMS tests.  This ensures
587 * that a "reasonable" small application should not have any problems.
[ed6e947]588 *
[d9e0006]589 * Port Specific Information:
[ed6e947]590 *
[d9e0006]591 * XXX document implementation including references if appropriate
[ed6e947]592 */
593#define CPU_STACK_MINIMUM_SIZE          (2048L)
594
[f1738ed]595#ifdef __m32cm_cpu__
596  #define CPU_SIZEOF_POINTER 4
597#else
598  #define CPU_SIZEOF_POINTER 2
599#endif
600
[ed6e947]601/**
[d9e0006]602 * CPU's worst alignment requirement for data types on a byte boundary.  This
603 * alignment does not take into account the requirements for the stack.
[ed6e947]604 *
[d9e0006]605 * Port Specific Information:
[ed6e947]606 *
[d9e0006]607 * XXX document implementation including references if appropriate
[ed6e947]608 */
[f517be0]609#define CPU_ALIGNMENT              2
[ed6e947]610
611/**
[d9e0006]612 * This number corresponds to the byte alignment requirement for the
613 * heap handler.  This alignment requirement may be stricter than that
614 * for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
615 * common for the heap to follow the same alignment requirement as
616 * @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
617 * the heap, then this should be set to @ref CPU_ALIGNMENT.
[ed6e947]618 *
[d9e0006]619 * NOTE:  This does not have to be a power of 2 although it should be
620 *        a multiple of 2 greater than or equal to 2.  The requirement
621 *        to be a multiple of 2 is because the heap uses the least
622 *        significant field of the front and back flags to indicate
623 *        that a block is in use or free.  So you do not want any odd
624 *        length blocks really putting length data in that bit.
[ed6e947]625 *
[d9e0006]626 *        On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
627 *        have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
628 *        elements allocated from the heap meet all restrictions.
629 *
630 * Port Specific Information:
631 *
632 * XXX document implementation including references if appropriate
[ed6e947]633 */
[97f46a8]634#define CPU_HEAP_ALIGNMENT         4
[ed6e947]635
636/**
[d9e0006]637 * This number corresponds to the byte alignment requirement for memory
638 * buffers allocated by the partition manager.  This alignment requirement
639 * may be stricter than that for the data types alignment specified by
640 * @ref CPU_ALIGNMENT.  It is common for the partition to follow the same
641 * alignment requirement as @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is
642 * strict enough for the partition, then this should be set to
643 * @ref CPU_ALIGNMENT.
[ed6e947]644 *
[d9e0006]645 * NOTE:  This does not have to be a power of 2.  It does have to
646 *        be greater or equal to than @ref CPU_ALIGNMENT.
[ed6e947]647 *
[d9e0006]648 * Port Specific Information:
[ed6e947]649 *
[d9e0006]650 * XXX document implementation including references if appropriate
[ed6e947]651 */
652#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
653
654/**
[d9e0006]655 * This number corresponds to the byte alignment requirement for the
656 * stack.  This alignment requirement may be stricter than that for the
657 * data types alignment specified by @ref CPU_ALIGNMENT.  If the
658 * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
659 * set to 0.
[ed6e947]660 *
[d9e0006]661 * NOTE: This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
[ed6e947]662 *
[d9e0006]663 * Port Specific Information:
[ed6e947]664 *
[d9e0006]665 * XXX document implementation including references if appropriate
[ed6e947]666 */
667#define CPU_STACK_ALIGNMENT        0
668
669/*
670 *  ISR handler macros
671 */
672
673/**
[d9e0006]674 * @ingroup CPUInterrupt
675 *
676 * Support routine to initialize the RTEMS vector table after it is allocated.
[ed6e947]677 *
[d9e0006]678 * Port Specific Information:
[ed6e947]679 *
[d9e0006]680 * XXX document implementation including references if appropriate
[ed6e947]681 */
682#define _CPU_Initialize_vectors()
683
684/**
[d9e0006]685 * @ingroup CPUInterrupt
686 *
687 * Disable all interrupts for an RTEMS critical section.  The previous
688 * level is returned in @a _isr_cookie.
[ed6e947]689 *
[d9e0006]690 * @param[out] _isr_cookie will contain the previous level cookie
[ed6e947]691 *
[d9e0006]692 * Port Specific Information:
[ed6e947]693 *
[d9e0006]694 * XXX document implementation including references if appropriate
[ed6e947]695 */
696#define _CPU_ISR_Disable( _isr_cookie ) \
697  do { \
698    int _flg; \
699    m32c_get_flg( _flg ); \
700    _isr_cookie = _flg; \
[901ffac]701    __asm__ volatile( "fclr I" ); \
[ed6e947]702  } while(0)
703
704/**
[d9e0006]705 * @ingroup CPUInterrupt
706 *
707 * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
708 * This indicates the end of an RTEMS critical section.  The parameter
709 * @a _isr_cookie is not modified.
[ed6e947]710 *
[d9e0006]711 * @param[in] _isr_cookie contain the previous level cookie
[ed6e947]712 *
[d9e0006]713 * Port Specific Information:
[ed6e947]714 *
[d9e0006]715 * XXX document implementation including references if appropriate
[ed6e947]716 */
717#define _CPU_ISR_Enable(_isr_cookie) \
718  do { \
719    int _flg = (int) (_isr_cookie); \
720    m32c_set_flg( _flg ); \
721  } while(0)
722
723/**
[d9e0006]724 * @ingroup CPUInterrupt
725 *
726 * This temporarily restores the interrupt to @a _isr_cookie before immediately
727 * disabling them again.  This is used to divide long RTEMS critical
728 * sections into two or more parts.  The parameter @a _isr_cookie is not
729 * modified.
[ed6e947]730 *
[d9e0006]731 * @param[in] _isr_cookie contain the previous level cookie
[ed6e947]732 *
[d9e0006]733 * Port Specific Information:
[ed6e947]734 *
[d9e0006]735 * XXX document implementation including references if appropriate
[ed6e947]736 */
737#define _CPU_ISR_Flash( _isr_cookie ) \
738  do { \
739    int _flg = (int) (_isr_cookie); \
740    m32c_set_flg( _flg ); \
[901ffac]741    __asm__ volatile( "fclr I" ); \
[ed6e947]742  } while(0)
743
744/**
[d9e0006]745 * @ingroup CPUInterrupt
[ed6e947]746 *
[d9e0006]747 * This routine and @ref _CPU_ISR_Get_level
748 * Map the interrupt level in task mode onto the hardware that the CPU
749 * actually provides.  Currently, interrupt levels which do not
750 * map onto the CPU in a generic fashion are undefined.  Someday,
751 * it would be nice if these were "mapped" by the application
752 * via a callout.  For example, m68k has 8 levels 0 - 7, levels
753 * 8 - 255 would be available for bsp/application specific meaning.
754 *This could be used to manage a programmable interrupt controller
755 * via the rtems_task_mode directive.
[ed6e947]756 *
[d9e0006]757 * Port Specific Information:
758 *
759 * XXX document implementation including references if appropriate
[ed6e947]760 */
761#define _CPU_ISR_Set_level( _new_level ) \
762  do { \
[901ffac]763    if (_new_level) __asm__ volatile( "fclr I" ); \
764    else            __asm__ volatile( "fset I" ); \
[ed6e947]765  } while(0)
766
767/**
[d9e0006]768 * @ingroup CPUInterrupt
769 *
770 * Return the current interrupt disable level for this task in
771 * the format used by the interrupt level portion of the task mode.
[ed6e947]772 *
[d9e0006]773 * NOTE: This routine usually must be implemented as a subroutine.
[ed6e947]774 *
[d9e0006]775 * Port Specific Information:
[ed6e947]776 *
[d9e0006]777 * XXX document implementation including references if appropriate
[ed6e947]778 */
779uint32_t   _CPU_ISR_Get_level( void );
780
781/* end of ISR handler macros */
782
783/* Context handler macros */
784
785/**
[d9e0006]786 * @ingroup CPUContext
787 *
788 * Initialize the context to a state suitable for starting a
789 * task after a context restore operation.  Generally, this
790 * involves:
791 *
792 *    - setting a starting address
793 *    - preparing the stack
794 *    - preparing the stack and frame pointers
795 *    - setting the proper interrupt level in the context
796 *    - initializing the floating point context
797 *
798 * This routine generally does not set any unnecessary register
799 * in the context.  The state of the "general data" registers is
800 * undefined at task start time.
801 *
802 * @param[in] _the_context is the context structure to be initialized
803 * @param[in] _stack_base is the lowest physical address of this task's stack
804 * @param[in] _size is the size of this task's stack
805 * @param[in] _isr is the interrupt disable level
806 * @param[in] _entry_point is the thread's entry point.  This is
807 *        always @a _Thread_Handler
808 * @param[in] _is_fp is TRUE if the thread is to be a floating
809 *       point thread.  This is typically only used on CPUs where the
810 *       FPU may be easily disabled by software such as on the SPARC
811 *       where the PSR contains an enable FPU bit.
[022851a]812 * @param[in] tls_area is the thread-local storage (TLS) area
[d9e0006]813 *
814 * Port Specific Information:
815 *
816 * XXX document implementation including references if appropriate
[ed6e947]817 */
818void _CPU_Context_Initialize(
819  Context_Control  *the_context,
820  uint32_t         *stack_base,
821  size_t            size,
822  uint32_t          new_level,
823  void             *entry_point,
[022851a]824  bool              is_fp,
825  void             *tls_area
[ed6e947]826);
827
828/**
[d9e0006]829 * This routine is responsible for somehow restarting the currently
830 * executing task.  If you are lucky, then all that is necessary
831 * is restoring the context.  Otherwise, there will need to be
832 * a special assembly routine which does something special in this
833 * case.  For many ports, simply adding a label to the restore path
834 * of @ref _CPU_Context_switch will work.  On other ports, it may be
835 * possibly to load a few arguments and jump to the restore path. It will
836 * not work if restarting self conflicts with the stack frame
837 * assumptions of restoring a context.
[ed6e947]838 *
[d9e0006]839 * Port Specific Information:
[ed6e947]840 *
[d9e0006]841 * XXX document implementation including references if appropriate
[ed6e947]842 */
[f517be0]843void _CPU_Context_Restart_self(
844  Context_Control  *the_context
845);
[ed6e947]846
847/**
[d9e0006]848 * @ingroup CPUContext
849 *
850 * The purpose of this macro is to allow the initial pointer into
851 * a floating point context area (used to save the floating point
852 * context) to be at an arbitrary place in the floating point
853 * context area.
[ed6e947]854 *
[d9e0006]855 * This is necessary because some FP units are designed to have
856 * their context saved as a stack which grows into lower addresses.
857 * Other FP units can be saved by simply moving registers into offsets
858 * from the base of the context area.  Finally some FP units provide
859 * a "dump context" instruction which could fill in from high to low
860 * or low to high based on the whim of the CPU designers.
[ed6e947]861 *
[d9e0006]862 * @param[in] _base is the lowest physical address of the floating point
863 *        context area
864 * @param[in] _offset is the offset into the floating point area
865 *
866 * Port Specific Information:
867 *
868 * XXX document implementation including references if appropriate
[ed6e947]869 */
870#define _CPU_Context_Fp_start( _base, _offset ) \
871   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
872
873/**
[d9e0006]874 * This routine initializes the FP context area passed to it to.
875 * There are a few standard ways in which to initialize the
876 * floating point context.  The code included for this macro assumes
877 * that this is a CPU in which a "initial" FP context was saved into
878 * @a _CPU_Null_fp_context and it simply copies it to the destination
879 * context passed to it.
[ed6e947]880 *
[d9e0006]881 * Other floating point context save/restore models include:
882 *   -# not doing anything, and
883 *   -# putting a "null FP status word" in the correct place in the FP context.
[ed6e947]884 *
[d9e0006]885 * @param[in] _destination is the floating point context area
[ed6e947]886 *
[d9e0006]887 * Port Specific Information:
[ed6e947]888 *
[d9e0006]889 * XXX document implementation including references if appropriate
[ed6e947]890 */
891#define _CPU_Context_Initialize_fp( _destination ) \
892  { \
893   *(*(_destination)) = _CPU_Null_fp_context; \
894  }
895
896/* end of Context handler macros */
897
898/* Fatal Error manager macros */
899
900/**
[d9e0006]901 * This routine copies _error into a known place -- typically a stack
902 * location or a register, optionally disables interrupts, and
903 * halts/stops the CPU.
[ed6e947]904 *
[d9e0006]905 * Port Specific Information:
[ed6e947]906 *
[d9e0006]907 * XXX document implementation including references if appropriate
[ed6e947]908 */
[f82752a4]909#define _CPU_Fatal_halt( _source, _error ) \
[ed6e947]910  { \
911  }
912
913/* end of Fatal Error manager macros */
914
915/* Bitfield handler macros */
916
917/**
[d9e0006]918 * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
[ed6e947]919 *
[d9e0006]920 * This set of routines are used to implement fast searches for
921 * the most important ready task.
[ed6e947]922 */
[b697bc6]923/**@{**/
[ed6e947]924
925/**
[d9e0006]926 * This definition is set to TRUE if the port uses the generic bitfield
927 * manipulation implementation.
[ed6e947]928 */
929#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
930
931/**
[d9e0006]932 * This definition is set to TRUE if the port uses the data tables provided
933 * by the generic bitfield manipulation implementation.
934 * This can occur when actually using the generic bitfield manipulation
935 * implementation or when implementing the same algorithm in assembly
936 * language for improved performance.  It is unlikely that a port will use
937 * the data if it has a bitfield scan instruction.
[ed6e947]938 */
939#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
940
941/**
[d9e0006]942 * This routine sets @a _output to the bit number of the first bit
943 * set in @a _value.  @a _value is of CPU dependent type
[f570b071]944 * @a Priority_bit_map_Word.  This type may be either 16 or 32 bits
[d9e0006]945 * wide although only the 16 least significant bits will be used.
946 *
947 * There are a number of variables in using a "find first bit" type
948 * instruction.
949 *
950 *   -# What happens when run on a value of zero?
951 *   -# Bits may be numbered from MSB to LSB or vice-versa.
952 *   -# The numbering may be zero or one based.
953 *   -# The "find first bit" instruction may search from MSB or LSB.
954 *
955 * RTEMS guarantees that (1) will never happen so it is not a concern.
956 * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
957 * @ref _CPU_Priority_bits_index.  These three form a set of routines
958 * which must logically operate together.  Bits in the _value are
959 * set and cleared based on masks built by @ref _CPU_Priority_Mask.
960 * The basic major and minor values calculated by @ref _Priority_Major
961 * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
962 * to properly range between the values returned by the "find first bit"
963 * instruction.  This makes it possible for @ref _Priority_Get_highest to
964 * calculate the major and directly index into the minor table.
965 * This mapping is necessary to ensure that 0 (a high priority major/minor)
966 * is the first bit found.
967 *
968 * This entire "find first bit" and mapping process depends heavily
969 * on the manner in which a priority is broken into a major and minor
970 * components with the major being the 4 MSB of a priority and minor
971 * the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
972 * priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
973 * to the lowest priority.
974 *
975 * If your CPU does not have a "find first bit" instruction, then
976 * there are ways to make do without it.  Here are a handful of ways
977 * to implement this in software:
[ed6e947]978 *
979@verbatim
980      - a series of 16 bit test instructions
981      - a "binary search using if's"
982      - _number = 0
983        if _value > 0x00ff
984          _value >>=8
985          _number = 8;
[28352fae]986
[ed6e947]987        if _value > 0x0000f
988          _value >=8
989          _number += 4
[28352fae]990
[ed6e947]991        _number += bit_set_table[ _value ]
992@endverbatim
[28352fae]993
[d9e0006]994 *   where bit_set_table[ 16 ] has values which indicate the first
995 *     bit set
[ed6e947]996 *
[d9e0006]997 * @param[in] _value is the value to be scanned
998 * @param[in] _output is the first bit set
[ed6e947]999 *
[d9e0006]1000 * Port Specific Information:
[ed6e947]1001 *
[d9e0006]1002 * XXX document implementation including references if appropriate
[ed6e947]1003 */
1004
1005#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1006#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
1007  { \
1008    (_output) = 0;   /* do something to prevent warnings */ \
1009  }
1010#endif
1011
1012/* end of Bitfield handler macros */
1013
1014/**
[d9e0006]1015 * This routine builds the mask which corresponds to the bit fields
1016 * as searched by @ref _CPU_Bitfield_Find_first_bit.  See the discussion
1017 * for that routine.
[ed6e947]1018 *
[d9e0006]1019 * Port Specific Information:
[ed6e947]1020 *
[d9e0006]1021 * XXX document implementation including references if appropriate
[ed6e947]1022 */
1023#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1024
1025#define _CPU_Priority_Mask( _bit_number ) \
1026  ( 1 << (_bit_number) )
1027
1028#endif
1029
1030/**
[d9e0006]1031 * This routine translates the bit numbers returned by
1032 * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
1033 * a major or minor component of a priority.  See the discussion
1034 * for that routine.
[ed6e947]1035 *
[d9e0006]1036 * @param[in] _priority is the major or minor number to translate
[ed6e947]1037 *
[d9e0006]1038 * Port Specific Information:
[ed6e947]1039 *
[d9e0006]1040 * XXX document implementation including references if appropriate
[ed6e947]1041 */
1042#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1043
1044#define _CPU_Priority_bits_index( _priority ) \
1045  (_priority)
1046
1047#endif
1048
[d9e0006]1049/** @} */
1050
[ed6e947]1051/* end of Priority handler macros */
1052
1053/* functions */
1054
1055/**
[d9e0006]1056 * This routine performs CPU dependent initialization.
[ed6e947]1057 *
[d9e0006]1058 * Port Specific Information:
[ed6e947]1059 *
[d9e0006]1060 * XXX document implementation including references if appropriate
[ed6e947]1061 */
[c03e2bc]1062void _CPU_Initialize(void);
[ed6e947]1063
1064/**
[d9e0006]1065 * @ingroup CPUInterrupt
[ed6e947]1066 *
[d9e0006]1067 * This routine installs a "raw" interrupt handler directly into the
1068 * processor's vector table.
[ed6e947]1069 *
[d9e0006]1070 * @param[in] vector is the vector number
1071 * @param[in] new_handler is the raw ISR handler to install
1072 * @param[in] old_handler is the previously installed ISR Handler
[ed6e947]1073 *
[d9e0006]1074 * Port Specific Information:
1075 *
1076 * XXX document implementation including references if appropriate
[ed6e947]1077 */
1078void _CPU_ISR_install_raw_handler(
1079  uint32_t    vector,
1080  proc_ptr    new_handler,
1081  proc_ptr   *old_handler
1082);
1083
1084/**
[d9e0006]1085 * @ingroup CPUInterrupt
1086 *
1087 * This routine installs an interrupt vector.
[ed6e947]1088 *
[d9e0006]1089 * @param[in] vector is the vector number
1090 * @param[in] new_handler is the RTEMS ISR handler to install
1091 * @param[in] old_handler is the previously installed ISR Handler
[ed6e947]1092 *
[d9e0006]1093 * Port Specific Information:
[ed6e947]1094 *
[d9e0006]1095 * XXX document implementation including references if appropriate
[ed6e947]1096 */
1097void _CPU_ISR_install_vector(
1098  uint32_t    vector,
1099  proc_ptr    new_handler,
1100  proc_ptr   *old_handler
1101);
1102
1103/**
[d9e0006]1104 * @ingroup CPUInterrupt
[ed6e947]1105 *
[d9e0006]1106 * This routine installs the hardware interrupt stack pointer.
[ed6e947]1107 *
[d9e0006]1108 * NOTE:  It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
1109 *        is TRUE.
[ed6e947]1110 *
[d9e0006]1111 * Port Specific Information:
1112 *
1113 * XXX document implementation including references if appropriate
[ed6e947]1114 */
1115void _CPU_Install_interrupt_stack( void );
1116
1117/**
[d9e0006]1118 * This routine is the CPU dependent IDLE thread body.
[ed6e947]1119 *
[d9e0006]1120 * NOTE:  It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY
1121 *        is TRUE.
[ed6e947]1122 *
[d9e0006]1123 * Port Specific Information:
[ed6e947]1124 *
[d9e0006]1125 * XXX document implementation including references if appropriate
[ed6e947]1126 */
[cca8379]1127void *_CPU_Thread_Idle_body( uintptr_t ignored );
[ed6e947]1128
1129/**
[d9e0006]1130 * @ingroup CPUContext
1131 *
1132 * This routine switches from the run context to the heir context.
[ed6e947]1133 *
[d9e0006]1134 * @param[in] run points to the context of the currently executing task
1135 * @param[in] heir points to the context of the heir task
[ed6e947]1136 *
[d9e0006]1137 * Port Specific Information:
[ed6e947]1138 *
[d9e0006]1139 * XXX document implementation including references if appropriate
[ed6e947]1140 */
1141void _CPU_Context_switch(
1142  Context_Control  *run,
1143  Context_Control  *heir
1144);
1145
1146/**
[d9e0006]1147 * @ingroup CPUContext
1148 *
1149 * This routine is generally used only to restart self in an
1150 * efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
[ed6e947]1151 *
[d9e0006]1152 * @param[in] new_context points to the context to be restored.
[ed6e947]1153 *
[d9e0006]1154 * NOTE: May be unnecessary to reload some registers.
[ed6e947]1155 *
[d9e0006]1156 * Port Specific Information:
[ed6e947]1157 *
[d9e0006]1158 * XXX document implementation including references if appropriate
[ed6e947]1159 */
1160void _CPU_Context_restore(
1161  Context_Control *new_context
[479cbaf8]1162) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
[ed6e947]1163
[39993d6]1164static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
1165{
1166  /* TODO */
1167}
1168
1169static inline void _CPU_Context_validate( uintptr_t pattern )
1170{
1171  while (1) {
1172    /* TODO */
1173  }
1174}
1175
[815994f]1176/* FIXME */
1177typedef CPU_Interrupt_frame CPU_Exception_frame;
1178
1179void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
1180
[ed6e947]1181/**
[d9e0006]1182 * @ingroup CPUEndian
1183 *
1184 * The following routine swaps the endian format of an unsigned int.
1185 * It must be static because it is referenced indirectly.
[ed6e947]1186 *
[d9e0006]1187 * This version will work on any processor, but if there is a better
1188 * way for your CPU PLEASE use it.  The most common way to do this is to:
[ed6e947]1189 *
[d9e0006]1190 *    swap least significant two bytes with 16-bit rotate
1191 *    swap upper and lower 16-bits
1192 *    swap most significant two bytes with 16-bit rotate
[ed6e947]1193 *
[d9e0006]1194 * Some CPUs have special instructions which swap a 32-bit quantity in
1195 * a single instruction (e.g. i486).  It is probably best to avoid
1196 * an "endian swapping control bit" in the CPU.  One good reason is
1197 * that interrupts would probably have to be disabled to ensure that
1198 * an interrupt does not try to access the same "chunk" with the wrong
1199 * endian.  Another good reason is that on some CPUs, the endian bit
1200 * endianness for ALL fetches -- both code and data -- so the code
1201 * will be fetched incorrectly.
[ed6e947]1202 *
[d9e0006]1203 * @param[in] value is the value to be swapped
1204 * @return the value after being endian swapped
[ed6e947]1205 *
[d9e0006]1206 * Port Specific Information:
[ed6e947]1207 *
[d9e0006]1208 * XXX document implementation including references if appropriate
[ed6e947]1209 */
1210static inline uint32_t CPU_swap_u32(
1211  uint32_t value
1212)
1213{
1214  uint32_t byte1, byte2, byte3, byte4, swapped;
[28352fae]1215
[ed6e947]1216  byte4 = (value >> 24) & 0xff;
1217  byte3 = (value >> 16) & 0xff;
1218  byte2 = (value >> 8)  & 0xff;
1219  byte1 =  value        & 0xff;
[28352fae]1220
[ed6e947]1221  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1222  return swapped;
1223}
1224
1225/**
[d9e0006]1226 * @ingroup CPUEndian
1227 *
1228 * This routine swaps a 16 bir quantity.
[ed6e947]1229 *
[d9e0006]1230 * @param[in] value is the value to be swapped
1231 * @return the value after being endian swapped
[ed6e947]1232 */
1233#define CPU_swap_u16( value ) \
1234  (((value&0xff) << 8) | ((value >> 8)&0xff))
1235
[24bf11e]1236typedef uint32_t CPU_Counter_ticks;
1237
1238CPU_Counter_ticks _CPU_Counter_read( void );
1239
1240static inline CPU_Counter_ticks _CPU_Counter_difference(
1241  CPU_Counter_ticks second,
1242  CPU_Counter_ticks first
1243)
1244{
1245  return second - first;
1246}
1247
[ed6e947]1248#ifdef __cplusplus
1249}
1250#endif
1251
1252#endif
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