1 | /** |
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2 | * @file |
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3 | * |
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4 | * @brief M32C CPU Dependent Source |
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5 | */ |
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6 | |
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7 | /* |
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8 | * This include file contains information pertaining to the XXX |
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9 | * processor. |
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10 | * |
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11 | * @note This file is part of a porting template that is intended |
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12 | * to be used as the starting point when porting RTEMS to a new |
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13 | * CPU family. The following needs to be done when using this as |
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14 | * the starting point for a new port: |
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15 | * |
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16 | * + Anywhere there is an XXX, it should be replaced |
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17 | * with information about the CPU family being ported to. |
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18 | * |
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19 | * + At the end of each comment section, there is a heading which |
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20 | * says "Port Specific Information:". When porting to RTEMS, |
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21 | * add CPU family specific information in this section |
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22 | */ |
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23 | |
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24 | /* |
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25 | * COPYRIGHT (c) 1989-2008. |
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26 | * On-Line Applications Research Corporation (OAR). |
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27 | * |
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28 | * The license and distribution terms for this file may be |
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29 | * found in the file LICENSE in this distribution or at |
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30 | * http://www.rtems.org/license/LICENSE. |
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31 | */ |
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32 | |
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33 | #ifndef _RTEMS_SCORE_CPU_H |
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34 | #define _RTEMS_SCORE_CPU_H |
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35 | |
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36 | #ifdef __cplusplus |
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37 | extern "C" { |
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38 | #endif |
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39 | |
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40 | #include <rtems/score/types.h> |
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41 | #include <rtems/score/m32c.h> |
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42 | |
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43 | /* conditional compilation parameters */ |
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44 | |
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45 | #define RTEMS_USE_16_BIT_OBJECT |
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46 | |
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47 | /** |
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48 | * Does RTEMS manage a dedicated interrupt stack in software? |
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49 | * |
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50 | * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization. |
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51 | * If FALSE, nothing is done. |
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52 | * |
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53 | * If the CPU supports a dedicated interrupt stack in hardware, |
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54 | * then it is generally the responsibility of the BSP to allocate it |
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55 | * and set it up. |
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56 | * |
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57 | * If the CPU does not support a dedicated interrupt stack, then |
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58 | * the porter has two options: (1) execute interrupts on the |
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59 | * stack of the interrupted task, and (2) have RTEMS manage a dedicated |
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60 | * interrupt stack. |
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61 | * |
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62 | * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
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63 | * |
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64 | * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
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65 | * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
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66 | * possible that both are FALSE for a particular CPU. Although it |
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67 | * is unclear what that would imply about the interrupt processing |
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68 | * procedure on that CPU. |
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69 | * |
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70 | * Port Specific Information: |
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71 | * |
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72 | * XXX document implementation including references if appropriate |
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73 | */ |
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74 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE |
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75 | |
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76 | /** |
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77 | * Does the CPU follow the simple vectored interrupt model? |
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78 | * |
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79 | * If TRUE, then RTEMS allocates the vector table it internally manages. |
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80 | * If FALSE, then the BSP is assumed to allocate and manage the vector |
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81 | * table |
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82 | * |
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83 | * Port Specific Information: |
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84 | * |
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85 | * XXX document implementation including references if appropriate |
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86 | */ |
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87 | #define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE |
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88 | |
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89 | /** |
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90 | * Does this CPU have hardware support for a dedicated interrupt stack? |
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91 | * |
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92 | * If TRUE, then it must be installed during initialization. |
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93 | * If FALSE, then no installation is performed. |
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94 | * |
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95 | * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
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96 | * |
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97 | * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
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98 | * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
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99 | * possible that both are FALSE for a particular CPU. Although it |
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100 | * is unclear what that would imply about the interrupt processing |
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101 | * procedure on that CPU. |
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102 | * |
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103 | * Port Specific Information: |
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104 | * |
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105 | * XXX document implementation including references if appropriate |
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106 | */ |
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107 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE |
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108 | |
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109 | /** |
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110 | * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? |
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111 | * |
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112 | * If TRUE, then the memory is allocated during initialization. |
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113 | * If FALSE, then the memory is allocated during initialization. |
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114 | * |
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115 | * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. |
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116 | * |
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117 | * Port Specific Information: |
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118 | * |
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119 | * XXX document implementation including references if appropriate |
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120 | */ |
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121 | #define CPU_ALLOCATE_INTERRUPT_STACK TRUE |
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122 | |
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123 | /** |
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124 | * Does the RTEMS invoke the user's ISR with the vector number and |
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125 | * a pointer to the saved interrupt frame (1) or just the vector |
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126 | * number (0)? |
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127 | * |
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128 | * Port Specific Information: |
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129 | * |
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130 | * XXX document implementation including references if appropriate |
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131 | */ |
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132 | #define CPU_ISR_PASSES_FRAME_POINTER FALSE |
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133 | |
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134 | /** |
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135 | * @def CPU_HARDWARE_FP |
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136 | * |
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137 | * Does the CPU have hardware floating point? |
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138 | * |
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139 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. |
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140 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. |
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141 | * |
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142 | * If there is a FP coprocessor such as the i387 or mc68881, then |
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143 | * the answer is TRUE. |
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144 | * |
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145 | * The macro name "M32C_HAS_FPU" should be made CPU specific. |
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146 | * It indicates whether or not this CPU model has FP support. For |
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147 | * example, it would be possible to have an i386_nofp CPU model |
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148 | * which set this to false to indicate that you have an i386 without |
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149 | * an i387 and wish to leave floating point support out of RTEMS. |
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150 | */ |
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151 | |
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152 | /** |
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153 | * @def CPU_SOFTWARE_FP |
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154 | * |
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155 | * Does the CPU have no hardware floating point and GCC provides a |
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156 | * software floating point implementation which must be context |
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157 | * switched? |
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158 | * |
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159 | * This feature conditional is used to indicate whether or not there |
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160 | * is software implemented floating point that must be context |
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161 | * switched. The determination of whether or not this applies |
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162 | * is very tool specific and the state saved/restored is also |
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163 | * compiler specific. |
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164 | * |
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165 | * Port Specific Information: |
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166 | * |
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167 | * XXX document implementation including references if appropriate |
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168 | */ |
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169 | #if ( M32C_HAS_FPU == 1 ) |
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170 | #define CPU_HARDWARE_FP TRUE |
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171 | #else |
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172 | #define CPU_HARDWARE_FP FALSE |
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173 | #endif |
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174 | #define CPU_SOFTWARE_FP FALSE |
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175 | |
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176 | #define CPU_CONTEXT_FP_SIZE 0 |
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177 | |
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178 | /** |
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179 | * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? |
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180 | * |
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181 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. |
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182 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. |
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183 | * |
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184 | * So far, the only CPUs in which this option has been used are the |
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185 | * HP PA-RISC and PowerPC. On the PA-RISC, The HP C compiler and |
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186 | * gcc both implicitly used the floating point registers to perform |
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187 | * integer multiplies. Similarly, the PowerPC port of gcc has been |
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188 | * seen to allocate floating point local variables and touch the FPU |
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189 | * even when the flow through a subroutine (like vfprintf()) might |
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190 | * not use floating point formats. |
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191 | * |
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192 | * If a function which you would not think utilize the FP unit DOES, |
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193 | * then one can not easily predict which tasks will use the FP hardware. |
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194 | * In this case, this option should be TRUE. |
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195 | * |
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196 | * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. |
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197 | * |
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198 | * Port Specific Information: |
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199 | * |
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200 | * XXX document implementation including references if appropriate |
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201 | */ |
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202 | #define CPU_ALL_TASKS_ARE_FP TRUE |
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203 | |
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204 | /** |
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205 | * Should the IDLE task have a floating point context? |
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206 | * |
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207 | * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task |
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208 | * and it has a floating point context which is switched in and out. |
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209 | * If FALSE, then the IDLE task does not have a floating point context. |
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210 | * |
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211 | * Setting this to TRUE negatively impacts the time required to preempt |
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212 | * the IDLE task from an interrupt because the floating point context |
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213 | * must be saved as part of the preemption. |
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214 | * |
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215 | * Port Specific Information: |
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216 | * |
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217 | * XXX document implementation including references if appropriate |
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218 | */ |
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219 | #define CPU_IDLE_TASK_IS_FP FALSE |
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220 | |
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221 | /** |
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222 | * Should the saving of the floating point registers be deferred |
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223 | * until a context switch is made to another different floating point |
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224 | * task? |
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225 | * |
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226 | * If TRUE, then the floating point context will not be stored until |
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227 | * necessary. It will remain in the floating point registers and not |
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228 | * disturned until another floating point task is switched to. |
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229 | * |
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230 | * If FALSE, then the floating point context is saved when a floating |
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231 | * point task is switched out and restored when the next floating point |
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232 | * task is restored. The state of the floating point registers between |
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233 | * those two operations is not specified. |
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234 | * |
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235 | * If the floating point context does NOT have to be saved as part of |
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236 | * interrupt dispatching, then it should be safe to set this to TRUE. |
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237 | * |
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238 | * Setting this flag to TRUE results in using a different algorithm |
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239 | * for deciding when to save and restore the floating point context. |
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240 | * The deferred FP switch algorithm minimizes the number of times |
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241 | * the FP context is saved and restored. The FP context is not saved |
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242 | * until a context switch is made to another, different FP task. |
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243 | * Thus in a system with only one FP task, the FP context will never |
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244 | * be saved or restored. |
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245 | * |
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246 | * Port Specific Information: |
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247 | * |
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248 | * XXX document implementation including references if appropriate |
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249 | */ |
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250 | #define CPU_USE_DEFERRED_FP_SWITCH TRUE |
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251 | |
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252 | #define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE |
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253 | |
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254 | /** |
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255 | * Does this port provide a CPU dependent IDLE task implementation? |
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256 | * |
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257 | * If TRUE, then the routine @ref _CPU_Thread_Idle_body |
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258 | * must be provided and is the default IDLE thread body instead of |
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259 | * @ref _CPU_Thread_Idle_body. |
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260 | * |
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261 | * If FALSE, then use the generic IDLE thread body if the BSP does |
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262 | * not provide one. |
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263 | * |
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264 | * This is intended to allow for supporting processors which have |
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265 | * a low power or idle mode. When the IDLE thread is executed, then |
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266 | * the CPU can be powered down. |
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267 | * |
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268 | * The order of precedence for selecting the IDLE thread body is: |
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269 | * |
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270 | * -# BSP provided |
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271 | * -# CPU dependent (if provided) |
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272 | * -# generic (if no BSP and no CPU dependent) |
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273 | * |
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274 | * Port Specific Information: |
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275 | * |
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276 | * XXX document implementation including references if appropriate |
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277 | */ |
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278 | #define CPU_PROVIDES_IDLE_THREAD_BODY TRUE |
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279 | |
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280 | /** |
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281 | * Does the stack grow up (toward higher addresses) or down |
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282 | * (toward lower addresses)? |
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283 | * |
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284 | * If TRUE, then the grows upward. |
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285 | * If FALSE, then the grows toward smaller addresses. |
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286 | * |
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287 | * Port Specific Information: |
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288 | * |
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289 | * XXX document implementation including references if appropriate |
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290 | */ |
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291 | #define CPU_STACK_GROWS_UP TRUE |
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292 | |
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293 | /* FIXME: Is this the right value? */ |
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294 | #define CPU_CACHE_LINE_BYTES 2 |
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295 | |
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296 | #define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) |
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297 | |
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298 | /** |
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299 | * @ingroup CPUInterrupt |
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300 | * |
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301 | * The following defines the number of bits actually used in the |
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302 | * interrupt field of the task mode. How those bits map to the |
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303 | * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level. |
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304 | * |
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305 | * Port Specific Information: |
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306 | * |
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307 | * XXX document implementation including references if appropriate |
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308 | */ |
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309 | #define CPU_MODES_INTERRUPT_MASK 0x00000001 |
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310 | |
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311 | #define CPU_MAXIMUM_PROCESSORS 32 |
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312 | |
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313 | /* |
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314 | * Processor defined structures required for cpukit/score. |
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315 | * |
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316 | * Port Specific Information: |
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317 | * |
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318 | * XXX document implementation including references if appropriate |
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319 | */ |
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320 | |
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321 | /* may need to put some structures here. */ |
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322 | |
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323 | /** |
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324 | * @defgroup CPUContext Processor Dependent Context Management |
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325 | * |
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326 | * From the highest level viewpoint, there are 2 types of context to save. |
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327 | * |
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328 | * -# Interrupt registers to save |
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329 | * -# Task level registers to save |
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330 | * |
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331 | * Since RTEMS handles integer and floating point contexts separately, this |
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332 | * means we have the following 3 context items: |
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333 | * |
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334 | * -# task level context stuff:: Context_Control |
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335 | * -# floating point task stuff:: Context_Control_fp |
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336 | * -# special interrupt level context :: CPU_Interrupt_frame |
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337 | * |
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338 | * On some processors, it is cost-effective to save only the callee |
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339 | * preserved registers during a task context switch. This means |
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340 | * that the ISR code needs to save those registers which do not |
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341 | * persist across function calls. It is not mandatory to make this |
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342 | * distinctions between the caller/callee saves registers for the |
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343 | * purpose of minimizing context saved during task switch and on interrupts. |
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344 | * If the cost of saving extra registers is minimal, simplicity is the |
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345 | * choice. Save the same context on interrupt entry as for tasks in |
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346 | * this case. |
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347 | * |
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348 | * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then |
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349 | * care should be used in designing the context area. |
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350 | * |
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351 | * On some CPUs with hardware floating point support, the Context_Control_fp |
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352 | * structure will not be used or it simply consist of an array of a |
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353 | * fixed number of bytes. This is done when the floating point context |
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354 | * is dumped by a "FP save context" type instruction and the format |
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355 | * is not really defined by the CPU. In this case, there is no need |
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356 | * to figure out the exact format -- only the size. Of course, although |
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357 | * this is enough information for RTEMS, it is probably not enough for |
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358 | * a debugger such as gdb. But that is another problem. |
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359 | * |
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360 | * Port Specific Information: |
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361 | * |
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362 | * XXX document implementation including references if appropriate |
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363 | */ |
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364 | /**@{**/ |
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365 | |
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366 | /** |
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367 | * @ingroup Management |
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368 | * |
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369 | * This defines the minimal set of integer and processor state registers |
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370 | * that must be saved during a voluntary context switch from one thread |
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371 | * to another. |
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372 | */ |
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373 | typedef struct { |
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374 | /** This will contain the stack pointer. */ |
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375 | uint32_t sp; |
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376 | /** This will contain the frame base pointer. */ |
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377 | uint32_t fb; |
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378 | } Context_Control; |
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379 | |
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380 | /** |
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381 | * @ingroup Management |
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382 | * |
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383 | * This macro returns the stack pointer associated with @a _context. |
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384 | * |
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385 | * @param[in] _context is the thread context area to access |
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386 | * |
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387 | * @return This method returns the stack pointer. |
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388 | */ |
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389 | #define _CPU_Context_Get_SP( _context ) \ |
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390 | (_context)->sp |
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391 | |
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392 | /** |
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393 | * @ingroup Management |
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394 | * |
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395 | * This defines the set of integer and processor state registers that must |
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396 | * be saved during an interrupt. This set does not include any which are |
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397 | * in @ref Context_Control. |
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398 | */ |
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399 | typedef struct { |
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400 | /** |
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401 | * This field is a hint that a port will have a number of integer |
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402 | * registers that need to be saved when an interrupt occurs or |
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403 | * when a context switch occurs at the end of an ISR. |
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404 | */ |
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405 | uint32_t special_interrupt_register; |
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406 | } CPU_Interrupt_frame; |
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407 | |
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408 | /** @} */ |
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409 | |
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410 | /** |
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411 | * @defgroup CPUInterrupt Processor Dependent Interrupt Management |
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412 | * |
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413 | * On some CPUs, RTEMS supports a software managed interrupt stack. |
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414 | * This stack is allocated by the Interrupt Manager and the switch |
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415 | * is performed in @ref _ISR_Handler. These variables contain pointers |
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416 | * to the lowest and highest addresses in the chunk of memory allocated |
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417 | * for the interrupt stack. Since it is unknown whether the stack |
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418 | * grows up or down (in general), this give the CPU dependent |
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419 | * code the option of picking the version it wants to use. |
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420 | * |
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421 | * NOTE: These two variables are required if the macro |
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422 | * @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. |
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423 | * |
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424 | * Port Specific Information: |
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425 | * |
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426 | * XXX document implementation including references if appropriate |
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427 | * |
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428 | */ |
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429 | /**@{**/ |
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430 | |
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431 | /* |
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432 | * Nothing prevents the porter from declaring more CPU specific variables. |
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433 | * |
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434 | * Port Specific Information: |
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435 | * |
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436 | * XXX document implementation including references if appropriate |
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437 | */ |
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438 | |
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439 | /* XXX: if needed, put more variables here */ |
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440 | |
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441 | /** |
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442 | * Amount of extra stack (above minimum stack size) required by |
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443 | * MPCI receive server thread. Remember that in a multiprocessor |
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444 | * system this thread must exist and be able to process all directives. |
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445 | * |
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446 | * Port Specific Information: |
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447 | * |
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448 | * XXX document implementation including references if appropriate |
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449 | */ |
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450 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
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451 | |
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452 | /** |
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453 | * This defines the number of entries in the @ref _ISR_Vector_table managed |
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454 | * by RTEMS. |
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455 | * |
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456 | * Port Specific Information: |
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457 | * |
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458 | * XXX document implementation including references if appropriate |
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459 | */ |
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460 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS 32 |
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461 | |
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462 | /** This defines the highest interrupt vector number for this port. */ |
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463 | #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) |
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464 | |
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465 | /** |
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466 | * This is defined if the port has a special way to report the ISR nesting |
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467 | * level. Most ports maintain the variable @a _ISR_Nest_level. |
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468 | */ |
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469 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
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470 | |
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471 | /** @} */ |
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472 | |
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473 | /** |
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474 | * @ingroup CPUContext |
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475 | * |
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476 | * Should be large enough to run all RTEMS tests. This ensures |
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477 | * that a "reasonable" small application should not have any problems. |
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478 | * |
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479 | * Port Specific Information: |
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480 | * |
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481 | * XXX document implementation including references if appropriate |
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482 | */ |
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483 | #define CPU_STACK_MINIMUM_SIZE (2048L) |
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484 | |
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485 | #ifdef __m32cm_cpu__ |
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486 | #define CPU_SIZEOF_POINTER 4 |
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487 | #else |
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488 | #define CPU_SIZEOF_POINTER 2 |
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489 | #endif |
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490 | |
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491 | /** |
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492 | * CPU's worst alignment requirement for data types on a byte boundary. This |
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493 | * alignment does not take into account the requirements for the stack. |
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494 | * |
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495 | * Port Specific Information: |
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496 | * |
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497 | * XXX document implementation including references if appropriate |
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498 | */ |
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499 | #define CPU_ALIGNMENT 2 |
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500 | |
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501 | /** |
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502 | * This number corresponds to the byte alignment requirement for the |
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503 | * heap handler. This alignment requirement may be stricter than that |
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504 | * for the data types alignment specified by @ref CPU_ALIGNMENT. It is |
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505 | * common for the heap to follow the same alignment requirement as |
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506 | * @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is strict enough for |
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507 | * the heap, then this should be set to @ref CPU_ALIGNMENT. |
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508 | * |
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509 | * NOTE: This does not have to be a power of 2 although it should be |
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510 | * a multiple of 2 greater than or equal to 2. The requirement |
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511 | * to be a multiple of 2 is because the heap uses the least |
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512 | * significant field of the front and back flags to indicate |
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513 | * that a block is in use or free. So you do not want any odd |
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514 | * length blocks really putting length data in that bit. |
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515 | * |
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516 | * On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will |
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517 | * have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that |
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518 | * elements allocated from the heap meet all restrictions. |
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519 | * |
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520 | * Port Specific Information: |
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521 | * |
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522 | * XXX document implementation including references if appropriate |
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523 | */ |
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524 | #define CPU_HEAP_ALIGNMENT 4 |
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525 | |
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526 | /** |
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527 | * This number corresponds to the byte alignment requirement for memory |
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528 | * buffers allocated by the partition manager. This alignment requirement |
---|
529 | * may be stricter than that for the data types alignment specified by |
---|
530 | * @ref CPU_ALIGNMENT. It is common for the partition to follow the same |
---|
531 | * alignment requirement as @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is |
---|
532 | * strict enough for the partition, then this should be set to |
---|
533 | * @ref CPU_ALIGNMENT. |
---|
534 | * |
---|
535 | * NOTE: This does not have to be a power of 2. It does have to |
---|
536 | * be greater or equal to than @ref CPU_ALIGNMENT. |
---|
537 | * |
---|
538 | * Port Specific Information: |
---|
539 | * |
---|
540 | * XXX document implementation including references if appropriate |
---|
541 | */ |
---|
542 | #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT |
---|
543 | |
---|
544 | /** |
---|
545 | * This number corresponds to the byte alignment requirement for the |
---|
546 | * stack. This alignment requirement may be stricter than that for the |
---|
547 | * data types alignment specified by @ref CPU_ALIGNMENT. If the |
---|
548 | * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be |
---|
549 | * set to 0. |
---|
550 | * |
---|
551 | * NOTE: This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT. |
---|
552 | * |
---|
553 | * Port Specific Information: |
---|
554 | * |
---|
555 | * XXX document implementation including references if appropriate |
---|
556 | */ |
---|
557 | #define CPU_STACK_ALIGNMENT 0 |
---|
558 | |
---|
559 | /* |
---|
560 | * ISR handler macros |
---|
561 | */ |
---|
562 | |
---|
563 | /** |
---|
564 | * @ingroup CPUInterrupt |
---|
565 | * |
---|
566 | * Support routine to initialize the RTEMS vector table after it is allocated. |
---|
567 | * |
---|
568 | * Port Specific Information: |
---|
569 | * |
---|
570 | * XXX document implementation including references if appropriate |
---|
571 | */ |
---|
572 | #define _CPU_Initialize_vectors() |
---|
573 | |
---|
574 | /** |
---|
575 | * @ingroup CPUInterrupt |
---|
576 | * |
---|
577 | * Disable all interrupts for an RTEMS critical section. The previous |
---|
578 | * level is returned in @a _isr_cookie. |
---|
579 | * |
---|
580 | * @param[out] _isr_cookie will contain the previous level cookie |
---|
581 | * |
---|
582 | * Port Specific Information: |
---|
583 | * |
---|
584 | * XXX document implementation including references if appropriate |
---|
585 | */ |
---|
586 | #define _CPU_ISR_Disable( _isr_cookie ) \ |
---|
587 | do { \ |
---|
588 | int _flg; \ |
---|
589 | m32c_get_flg( _flg ); \ |
---|
590 | _isr_cookie = _flg; \ |
---|
591 | __asm__ volatile( "fclr I" ); \ |
---|
592 | } while(0) |
---|
593 | |
---|
594 | /** |
---|
595 | * @ingroup CPUInterrupt |
---|
596 | * |
---|
597 | * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). |
---|
598 | * This indicates the end of an RTEMS critical section. The parameter |
---|
599 | * @a _isr_cookie is not modified. |
---|
600 | * |
---|
601 | * @param[in] _isr_cookie contain the previous level cookie |
---|
602 | * |
---|
603 | * Port Specific Information: |
---|
604 | * |
---|
605 | * XXX document implementation including references if appropriate |
---|
606 | */ |
---|
607 | #define _CPU_ISR_Enable(_isr_cookie) \ |
---|
608 | do { \ |
---|
609 | int _flg = (int) (_isr_cookie); \ |
---|
610 | m32c_set_flg( _flg ); \ |
---|
611 | } while(0) |
---|
612 | |
---|
613 | /** |
---|
614 | * @ingroup CPUInterrupt |
---|
615 | * |
---|
616 | * This temporarily restores the interrupt to @a _isr_cookie before immediately |
---|
617 | * disabling them again. This is used to divide long RTEMS critical |
---|
618 | * sections into two or more parts. The parameter @a _isr_cookie is not |
---|
619 | * modified. |
---|
620 | * |
---|
621 | * @param[in] _isr_cookie contain the previous level cookie |
---|
622 | * |
---|
623 | * Port Specific Information: |
---|
624 | * |
---|
625 | * XXX document implementation including references if appropriate |
---|
626 | */ |
---|
627 | #define _CPU_ISR_Flash( _isr_cookie ) \ |
---|
628 | do { \ |
---|
629 | int _flg = (int) (_isr_cookie); \ |
---|
630 | m32c_set_flg( _flg ); \ |
---|
631 | __asm__ volatile( "fclr I" ); \ |
---|
632 | } while(0) |
---|
633 | |
---|
634 | RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) |
---|
635 | { |
---|
636 | return ( level & 0x40 ) != 0; |
---|
637 | } |
---|
638 | |
---|
639 | /** |
---|
640 | * @ingroup CPUInterrupt |
---|
641 | * |
---|
642 | * This routine and @ref _CPU_ISR_Get_level |
---|
643 | * Map the interrupt level in task mode onto the hardware that the CPU |
---|
644 | * actually provides. Currently, interrupt levels which do not |
---|
645 | * map onto the CPU in a generic fashion are undefined. Someday, |
---|
646 | * it would be nice if these were "mapped" by the application |
---|
647 | * via a callout. For example, m68k has 8 levels 0 - 7, levels |
---|
648 | * 8 - 255 would be available for bsp/application specific meaning. |
---|
649 | *This could be used to manage a programmable interrupt controller |
---|
650 | * via the rtems_task_mode directive. |
---|
651 | * |
---|
652 | * Port Specific Information: |
---|
653 | * |
---|
654 | * XXX document implementation including references if appropriate |
---|
655 | */ |
---|
656 | #define _CPU_ISR_Set_level( _new_level ) \ |
---|
657 | do { \ |
---|
658 | if (_new_level) __asm__ volatile( "fclr I" ); \ |
---|
659 | else __asm__ volatile( "fset I" ); \ |
---|
660 | } while(0) |
---|
661 | |
---|
662 | /** |
---|
663 | * @ingroup CPUInterrupt |
---|
664 | * |
---|
665 | * Return the current interrupt disable level for this task in |
---|
666 | * the format used by the interrupt level portion of the task mode. |
---|
667 | * |
---|
668 | * NOTE: This routine usually must be implemented as a subroutine. |
---|
669 | * |
---|
670 | * Port Specific Information: |
---|
671 | * |
---|
672 | * XXX document implementation including references if appropriate |
---|
673 | */ |
---|
674 | uint32_t _CPU_ISR_Get_level( void ); |
---|
675 | |
---|
676 | /* end of ISR handler macros */ |
---|
677 | |
---|
678 | /* Context handler macros */ |
---|
679 | |
---|
680 | /** |
---|
681 | * @ingroup CPUContext |
---|
682 | * |
---|
683 | * Initialize the context to a state suitable for starting a |
---|
684 | * task after a context restore operation. Generally, this |
---|
685 | * involves: |
---|
686 | * |
---|
687 | * - setting a starting address |
---|
688 | * - preparing the stack |
---|
689 | * - preparing the stack and frame pointers |
---|
690 | * - setting the proper interrupt level in the context |
---|
691 | * - initializing the floating point context |
---|
692 | * |
---|
693 | * This routine generally does not set any unnecessary register |
---|
694 | * in the context. The state of the "general data" registers is |
---|
695 | * undefined at task start time. |
---|
696 | * |
---|
697 | * @param[in] _the_context is the context structure to be initialized |
---|
698 | * @param[in] _stack_base is the lowest physical address of this task's stack |
---|
699 | * @param[in] _size is the size of this task's stack |
---|
700 | * @param[in] _isr is the interrupt disable level |
---|
701 | * @param[in] _entry_point is the thread's entry point. This is |
---|
702 | * always @a _Thread_Handler |
---|
703 | * @param[in] _is_fp is TRUE if the thread is to be a floating |
---|
704 | * point thread. This is typically only used on CPUs where the |
---|
705 | * FPU may be easily disabled by software such as on the SPARC |
---|
706 | * where the PSR contains an enable FPU bit. |
---|
707 | * @param[in] tls_area is the thread-local storage (TLS) area |
---|
708 | * |
---|
709 | * Port Specific Information: |
---|
710 | * |
---|
711 | * XXX document implementation including references if appropriate |
---|
712 | */ |
---|
713 | void _CPU_Context_Initialize( |
---|
714 | Context_Control *the_context, |
---|
715 | uint32_t *stack_base, |
---|
716 | size_t size, |
---|
717 | uint32_t new_level, |
---|
718 | void *entry_point, |
---|
719 | bool is_fp, |
---|
720 | void *tls_area |
---|
721 | ); |
---|
722 | |
---|
723 | /** |
---|
724 | * This routine is responsible for somehow restarting the currently |
---|
725 | * executing task. If you are lucky, then all that is necessary |
---|
726 | * is restoring the context. Otherwise, there will need to be |
---|
727 | * a special assembly routine which does something special in this |
---|
728 | * case. For many ports, simply adding a label to the restore path |
---|
729 | * of @ref _CPU_Context_switch will work. On other ports, it may be |
---|
730 | * possibly to load a few arguments and jump to the restore path. It will |
---|
731 | * not work if restarting self conflicts with the stack frame |
---|
732 | * assumptions of restoring a context. |
---|
733 | * |
---|
734 | * Port Specific Information: |
---|
735 | * |
---|
736 | * XXX document implementation including references if appropriate |
---|
737 | */ |
---|
738 | void _CPU_Context_Restart_self( |
---|
739 | Context_Control *the_context |
---|
740 | ) RTEMS_NO_RETURN; |
---|
741 | |
---|
742 | /** |
---|
743 | * This routine initializes the FP context area passed to it to. |
---|
744 | * There are a few standard ways in which to initialize the |
---|
745 | * floating point context. The code included for this macro assumes |
---|
746 | * that this is a CPU in which a "initial" FP context was saved into |
---|
747 | * @a _CPU_Null_fp_context and it simply copies it to the destination |
---|
748 | * context passed to it. |
---|
749 | * |
---|
750 | * Other floating point context save/restore models include: |
---|
751 | * -# not doing anything, and |
---|
752 | * -# putting a "null FP status word" in the correct place in the FP context. |
---|
753 | * |
---|
754 | * @param[in] _destination is the floating point context area |
---|
755 | * |
---|
756 | * Port Specific Information: |
---|
757 | * |
---|
758 | * XXX document implementation including references if appropriate |
---|
759 | */ |
---|
760 | #define _CPU_Context_Initialize_fp( _destination ) \ |
---|
761 | { \ |
---|
762 | *(*(_destination)) = _CPU_Null_fp_context; \ |
---|
763 | } |
---|
764 | |
---|
765 | /* end of Context handler macros */ |
---|
766 | |
---|
767 | /* Fatal Error manager macros */ |
---|
768 | |
---|
769 | /** |
---|
770 | * This routine copies _error into a known place -- typically a stack |
---|
771 | * location or a register, optionally disables interrupts, and |
---|
772 | * halts/stops the CPU. |
---|
773 | * |
---|
774 | * Port Specific Information: |
---|
775 | * |
---|
776 | * XXX document implementation including references if appropriate |
---|
777 | */ |
---|
778 | #define _CPU_Fatal_halt( _source, _error ) \ |
---|
779 | { \ |
---|
780 | } |
---|
781 | |
---|
782 | /* end of Fatal Error manager macros */ |
---|
783 | |
---|
784 | #define CPU_USE_GENERIC_BITFIELD_CODE TRUE |
---|
785 | |
---|
786 | /* functions */ |
---|
787 | |
---|
788 | /** |
---|
789 | * This routine performs CPU dependent initialization. |
---|
790 | * |
---|
791 | * Port Specific Information: |
---|
792 | * |
---|
793 | * XXX document implementation including references if appropriate |
---|
794 | */ |
---|
795 | void _CPU_Initialize(void); |
---|
796 | |
---|
797 | /** |
---|
798 | * @ingroup CPUInterrupt |
---|
799 | * |
---|
800 | * This routine installs a "raw" interrupt handler directly into the |
---|
801 | * processor's vector table. |
---|
802 | * |
---|
803 | * @param[in] vector is the vector number |
---|
804 | * @param[in] new_handler is the raw ISR handler to install |
---|
805 | * @param[in] old_handler is the previously installed ISR Handler |
---|
806 | * |
---|
807 | * Port Specific Information: |
---|
808 | * |
---|
809 | * XXX document implementation including references if appropriate |
---|
810 | */ |
---|
811 | void _CPU_ISR_install_raw_handler( |
---|
812 | uint32_t vector, |
---|
813 | proc_ptr new_handler, |
---|
814 | proc_ptr *old_handler |
---|
815 | ); |
---|
816 | |
---|
817 | /** |
---|
818 | * @ingroup CPUInterrupt |
---|
819 | * |
---|
820 | * This routine installs an interrupt vector. |
---|
821 | * |
---|
822 | * @param[in] vector is the vector number |
---|
823 | * @param[in] new_handler is the RTEMS ISR handler to install |
---|
824 | * @param[in] old_handler is the previously installed ISR Handler |
---|
825 | * |
---|
826 | * Port Specific Information: |
---|
827 | * |
---|
828 | * XXX document implementation including references if appropriate |
---|
829 | */ |
---|
830 | void _CPU_ISR_install_vector( |
---|
831 | uint32_t vector, |
---|
832 | proc_ptr new_handler, |
---|
833 | proc_ptr *old_handler |
---|
834 | ); |
---|
835 | |
---|
836 | /** |
---|
837 | * @ingroup CPUInterrupt |
---|
838 | * |
---|
839 | * This routine installs the hardware interrupt stack pointer. |
---|
840 | * |
---|
841 | * NOTE: It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK |
---|
842 | * is TRUE. |
---|
843 | * |
---|
844 | * Port Specific Information: |
---|
845 | * |
---|
846 | * XXX document implementation including references if appropriate |
---|
847 | */ |
---|
848 | void _CPU_Install_interrupt_stack( void ); |
---|
849 | |
---|
850 | /** |
---|
851 | * This routine is the CPU dependent IDLE thread body. |
---|
852 | * |
---|
853 | * NOTE: It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY |
---|
854 | * is TRUE. |
---|
855 | * |
---|
856 | * Port Specific Information: |
---|
857 | * |
---|
858 | * XXX document implementation including references if appropriate |
---|
859 | */ |
---|
860 | void *_CPU_Thread_Idle_body( uintptr_t ignored ); |
---|
861 | |
---|
862 | /** |
---|
863 | * @ingroup CPUContext |
---|
864 | * |
---|
865 | * This routine switches from the run context to the heir context. |
---|
866 | * |
---|
867 | * @param[in] run points to the context of the currently executing task |
---|
868 | * @param[in] heir points to the context of the heir task |
---|
869 | * |
---|
870 | * Port Specific Information: |
---|
871 | * |
---|
872 | * XXX document implementation including references if appropriate |
---|
873 | */ |
---|
874 | void _CPU_Context_switch( |
---|
875 | Context_Control *run, |
---|
876 | Context_Control *heir |
---|
877 | ); |
---|
878 | |
---|
879 | /** |
---|
880 | * @ingroup CPUContext |
---|
881 | * |
---|
882 | * This routine is generally used only to restart self in an |
---|
883 | * efficient manner. It may simply be a label in @ref _CPU_Context_switch. |
---|
884 | * |
---|
885 | * @param[in] new_context points to the context to be restored. |
---|
886 | * |
---|
887 | * NOTE: May be unnecessary to reload some registers. |
---|
888 | * |
---|
889 | * Port Specific Information: |
---|
890 | * |
---|
891 | * XXX document implementation including references if appropriate |
---|
892 | */ |
---|
893 | void _CPU_Context_restore( |
---|
894 | Context_Control *new_context |
---|
895 | ) RTEMS_NO_RETURN; |
---|
896 | |
---|
897 | static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) |
---|
898 | { |
---|
899 | /* TODO */ |
---|
900 | } |
---|
901 | |
---|
902 | static inline void _CPU_Context_validate( uintptr_t pattern ) |
---|
903 | { |
---|
904 | while (1) { |
---|
905 | /* TODO */ |
---|
906 | } |
---|
907 | } |
---|
908 | |
---|
909 | /* FIXME */ |
---|
910 | typedef CPU_Interrupt_frame CPU_Exception_frame; |
---|
911 | |
---|
912 | void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); |
---|
913 | |
---|
914 | /** |
---|
915 | * @ingroup CPUEndian |
---|
916 | * |
---|
917 | * The following routine swaps the endian format of an unsigned int. |
---|
918 | * It must be static because it is referenced indirectly. |
---|
919 | * |
---|
920 | * This version will work on any processor, but if there is a better |
---|
921 | * way for your CPU PLEASE use it. The most common way to do this is to: |
---|
922 | * |
---|
923 | * swap least significant two bytes with 16-bit rotate |
---|
924 | * swap upper and lower 16-bits |
---|
925 | * swap most significant two bytes with 16-bit rotate |
---|
926 | * |
---|
927 | * Some CPUs have special instructions which swap a 32-bit quantity in |
---|
928 | * a single instruction (e.g. i486). It is probably best to avoid |
---|
929 | * an "endian swapping control bit" in the CPU. One good reason is |
---|
930 | * that interrupts would probably have to be disabled to ensure that |
---|
931 | * an interrupt does not try to access the same "chunk" with the wrong |
---|
932 | * endian. Another good reason is that on some CPUs, the endian bit |
---|
933 | * endianness for ALL fetches -- both code and data -- so the code |
---|
934 | * will be fetched incorrectly. |
---|
935 | * |
---|
936 | * @param[in] value is the value to be swapped |
---|
937 | * @return the value after being endian swapped |
---|
938 | * |
---|
939 | * Port Specific Information: |
---|
940 | * |
---|
941 | * XXX document implementation including references if appropriate |
---|
942 | */ |
---|
943 | static inline uint32_t CPU_swap_u32( |
---|
944 | uint32_t value |
---|
945 | ) |
---|
946 | { |
---|
947 | uint32_t byte1, byte2, byte3, byte4, swapped; |
---|
948 | |
---|
949 | byte4 = (value >> 24) & 0xff; |
---|
950 | byte3 = (value >> 16) & 0xff; |
---|
951 | byte2 = (value >> 8) & 0xff; |
---|
952 | byte1 = value & 0xff; |
---|
953 | |
---|
954 | swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; |
---|
955 | return swapped; |
---|
956 | } |
---|
957 | |
---|
958 | /** |
---|
959 | * @ingroup CPUEndian |
---|
960 | * |
---|
961 | * This routine swaps a 16 bir quantity. |
---|
962 | * |
---|
963 | * @param[in] value is the value to be swapped |
---|
964 | * @return the value after being endian swapped |
---|
965 | */ |
---|
966 | #define CPU_swap_u16( value ) \ |
---|
967 | (((value&0xff) << 8) | ((value >> 8)&0xff)) |
---|
968 | |
---|
969 | typedef uint32_t CPU_Counter_ticks; |
---|
970 | |
---|
971 | CPU_Counter_ticks _CPU_Counter_read( void ); |
---|
972 | |
---|
973 | static inline CPU_Counter_ticks _CPU_Counter_difference( |
---|
974 | CPU_Counter_ticks second, |
---|
975 | CPU_Counter_ticks first |
---|
976 | ) |
---|
977 | { |
---|
978 | return second - first; |
---|
979 | } |
---|
980 | |
---|
981 | #ifdef __cplusplus |
---|
982 | } |
---|
983 | #endif |
---|
984 | |
---|
985 | #endif |
---|