source: rtems/cpukit/score/cpu/m32c/include/rtems/score/cpu.h @ 27bbc05

Last change on this file since 27bbc05 was 27bbc05, checked in by Sebastian Huber <sebastian.huber@…>, on Aug 2, 2018 at 12:49:01 PM

score: Remove CPU_PARTITION_ALIGNMENT

Use the CPU_SIZEOF_POINTER alignment instead. The internal alignment
requirement is defined by the use of Chain_Node (consisting of two
pointers) to manage the free chain of partitions.

It seems that previously the condition

CPU_PARTITION_ALIGNMENT >= sizeof(Chain_Node)

was true on all CPU ports. Now, we need an additional check.

Update #3482.

  • Property mode set to 100644
File size: 26.1 KB
Line 
1/**
2 * @file
3 *
4 * @brief M32C CPU Dependent Source
5 */
6
7/*
8 *  This include file contains information pertaining to the XXX
9 *  processor.
10 *
11 *  @note This file is part of a porting template that is intended
12 *  to be used as the starting point when porting RTEMS to a new
13 *  CPU family.  The following needs to be done when using this as
14 *  the starting point for a new port:
15 *
16 *  + Anywhere there is an XXX, it should be replaced
17 *    with information about the CPU family being ported to.
18 *
19 *  + At the end of each comment section, there is a heading which
20 *    says "Port Specific Information:".  When porting to RTEMS,
21 *    add CPU family specific information in this section
22 */
23
24/*
25 *  COPYRIGHT (c) 1989-2008.
26 *  On-Line Applications Research Corporation (OAR).
27 *
28 *  The license and distribution terms for this file may be
29 *  found in the file LICENSE in this distribution or at
30 *  http://www.rtems.org/license/LICENSE.
31 */
32
33#ifndef _RTEMS_SCORE_CPU_H
34#define _RTEMS_SCORE_CPU_H
35
36#ifdef __cplusplus
37extern "C" {
38#endif
39
40#include <rtems/score/basedefs.h>
41#include <rtems/score/m32c.h>
42
43/* conditional compilation parameters */
44
45#define RTEMS_USE_16_BIT_OBJECT
46
47/**
48 * Does the CPU follow the simple vectored interrupt model?
49 *
50 * If TRUE, then RTEMS allocates the vector table it internally manages.
51 * If FALSE, then the BSP is assumed to allocate and manage the vector
52 * table
53 *
54 * Port Specific Information:
55 *
56 * XXX document implementation including references if appropriate
57 */
58#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
59
60/**
61 * Does the RTEMS invoke the user's ISR with the vector number and
62 * a pointer to the saved interrupt frame (1) or just the vector
63 * number (0)?
64 *
65 * Port Specific Information:
66 *
67 * XXX document implementation including references if appropriate
68 */
69#define CPU_ISR_PASSES_FRAME_POINTER FALSE
70
71/**
72 * @def CPU_HARDWARE_FP
73 *
74 * Does the CPU have hardware floating point?
75 *
76 * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
77 * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
78 *
79 * If there is a FP coprocessor such as the i387 or mc68881, then
80 * the answer is TRUE.
81 *
82 * The macro name "M32C_HAS_FPU" should be made CPU specific.
83 * It indicates whether or not this CPU model has FP support.  For
84 * example, it would be possible to have an i386_nofp CPU model
85 * which set this to false to indicate that you have an i386 without
86 * an i387 and wish to leave floating point support out of RTEMS.
87 */
88
89/**
90 * @def CPU_SOFTWARE_FP
91 *
92 * Does the CPU have no hardware floating point and GCC provides a
93 * software floating point implementation which must be context
94 * switched?
95 *
96 * This feature conditional is used to indicate whether or not there
97 * is software implemented floating point that must be context
98 * switched.  The determination of whether or not this applies
99 * is very tool specific and the state saved/restored is also
100 * compiler specific.
101 *
102 * Port Specific Information:
103 *
104 * XXX document implementation including references if appropriate
105 */
106#if ( M32C_HAS_FPU == 1 )
107#define CPU_HARDWARE_FP     TRUE
108#else
109#define CPU_HARDWARE_FP     FALSE
110#endif
111#define CPU_SOFTWARE_FP     FALSE
112
113#define CPU_CONTEXT_FP_SIZE 0
114
115/**
116 * Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
117 *
118 * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
119 * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
120 *
121 * So far, the only CPUs in which this option has been used are the
122 * HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
123 * gcc both implicitly used the floating point registers to perform
124 * integer multiplies.  Similarly, the PowerPC port of gcc has been
125 * seen to allocate floating point local variables and touch the FPU
126 * even when the flow through a subroutine (like vfprintf()) might
127 * not use floating point formats.
128 *
129 * If a function which you would not think utilize the FP unit DOES,
130 * then one can not easily predict which tasks will use the FP hardware.
131 * In this case, this option should be TRUE.
132 *
133 * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
134 *
135 * Port Specific Information:
136 *
137 * XXX document implementation including references if appropriate
138 */
139#define CPU_ALL_TASKS_ARE_FP     TRUE
140
141/**
142 * Should the IDLE task have a floating point context?
143 *
144 * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
145 * and it has a floating point context which is switched in and out.
146 * If FALSE, then the IDLE task does not have a floating point context.
147 *
148 * Setting this to TRUE negatively impacts the time required to preempt
149 * the IDLE task from an interrupt because the floating point context
150 * must be saved as part of the preemption.
151 *
152 * Port Specific Information:
153 *
154 * XXX document implementation including references if appropriate
155 */
156#define CPU_IDLE_TASK_IS_FP      FALSE
157
158/**
159 * Should the saving of the floating point registers be deferred
160 * until a context switch is made to another different floating point
161 * task?
162 *
163 * If TRUE, then the floating point context will not be stored until
164 * necessary.  It will remain in the floating point registers and not
165 * disturned until another floating point task is switched to.
166 *
167 * If FALSE, then the floating point context is saved when a floating
168 * point task is switched out and restored when the next floating point
169 * task is restored.  The state of the floating point registers between
170 * those two operations is not specified.
171 *
172 * If the floating point context does NOT have to be saved as part of
173 * interrupt dispatching, then it should be safe to set this to TRUE.
174 *
175 * Setting this flag to TRUE results in using a different algorithm
176 * for deciding when to save and restore the floating point context.
177 * The deferred FP switch algorithm minimizes the number of times
178 * the FP context is saved and restored.  The FP context is not saved
179 * until a context switch is made to another, different FP task.
180 * Thus in a system with only one FP task, the FP context will never
181 * be saved or restored.
182 *
183 * Port Specific Information:
184 *
185 * XXX document implementation including references if appropriate
186 */
187#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
188
189#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
190
191/**
192 * Does this port provide a CPU dependent IDLE task implementation?
193 *
194 * If TRUE, then the routine @ref _CPU_Thread_Idle_body
195 * must be provided and is the default IDLE thread body instead of
196 * @ref _CPU_Thread_Idle_body.
197 *
198 * If FALSE, then use the generic IDLE thread body if the BSP does
199 * not provide one.
200 *
201 * This is intended to allow for supporting processors which have
202 * a low power or idle mode.  When the IDLE thread is executed, then
203 * the CPU can be powered down.
204 *
205 * The order of precedence for selecting the IDLE thread body is:
206 *
207 *   -#  BSP provided
208 *   -#  CPU dependent (if provided)
209 *   -#  generic (if no BSP and no CPU dependent)
210 *
211 * Port Specific Information:
212 *
213 * XXX document implementation including references if appropriate
214 */
215#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
216
217/**
218 * Does the stack grow up (toward higher addresses) or down
219 * (toward lower addresses)?
220 *
221 * If TRUE, then the grows upward.
222 * If FALSE, then the grows toward smaller addresses.
223 *
224 * Port Specific Information:
225 *
226 * XXX document implementation including references if appropriate
227 */
228#define CPU_STACK_GROWS_UP               TRUE
229
230/* FIXME: Is this the right value? */
231#define CPU_CACHE_LINE_BYTES 2
232
233#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
234
235/**
236 * @ingroup CPUInterrupt
237 *
238 * The following defines the number of bits actually used in the
239 * interrupt field of the task mode.  How those bits map to the
240 * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
241 *
242 * Port Specific Information:
243 *
244 * XXX document implementation including references if appropriate
245 */
246#define CPU_MODES_INTERRUPT_MASK   0x00000001
247
248#define CPU_MAXIMUM_PROCESSORS 32
249
250/*
251 *  Processor defined structures required for cpukit/score.
252 *
253 *  Port Specific Information:
254 *
255 *  XXX document implementation including references if appropriate
256 */
257
258/* may need to put some structures here.  */
259
260/**
261 * @defgroup CPUContext Processor Dependent Context Management
262 *
263 * From the highest level viewpoint, there are 2 types of context to save.
264 *
265 *    -# Interrupt registers to save
266 *    -# Task level registers to save
267 *
268 * Since RTEMS handles integer and floating point contexts separately, this
269 * means we have the following 3 context items:
270 *
271 *    -# task level context stuff::  Context_Control
272 *    -# floating point task stuff:: Context_Control_fp
273 *    -# special interrupt level context :: CPU_Interrupt_frame
274 *
275 * On some processors, it is cost-effective to save only the callee
276 * preserved registers during a task context switch.  This means
277 * that the ISR code needs to save those registers which do not
278 * persist across function calls.  It is not mandatory to make this
279 * distinctions between the caller/callee saves registers for the
280 * purpose of minimizing context saved during task switch and on interrupts.
281 * If the cost of saving extra registers is minimal, simplicity is the
282 * choice.  Save the same context on interrupt entry as for tasks in
283 * this case.
284 *
285 * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
286 * care should be used in designing the context area.
287 *
288 * On some CPUs with hardware floating point support, the Context_Control_fp
289 * structure will not be used or it simply consist of an array of a
290 * fixed number of bytes.   This is done when the floating point context
291 * is dumped by a "FP save context" type instruction and the format
292 * is not really defined by the CPU.  In this case, there is no need
293 * to figure out the exact format -- only the size.  Of course, although
294 * this is enough information for RTEMS, it is probably not enough for
295 * a debugger such as gdb.  But that is another problem.
296 *
297 * Port Specific Information:
298 *
299 * XXX document implementation including references if appropriate
300 */
301/**@{**/
302
303/**
304 * @ingroup Management
305 *
306 * This defines the minimal set of integer and processor state registers
307 * that must be saved during a voluntary context switch from one thread
308 * to another.
309 */
310typedef struct {
311  /** This will contain the stack pointer. */
312  uint32_t sp;
313  /** This will contain the frame base pointer. */
314  uint32_t fb;
315} Context_Control;
316
317/**
318 * @ingroup Management
319 *
320 * This macro returns the stack pointer associated with @a _context.
321 *
322 * @param[in] _context is the thread context area to access
323 *
324 * @return This method returns the stack pointer.
325 */
326#define _CPU_Context_Get_SP( _context ) \
327  (_context)->sp
328
329/**
330 * @ingroup Management
331 *
332 * This defines the set of integer and processor state registers that must
333 * be saved during an interrupt.  This set does not include any which are
334 * in @ref Context_Control.
335 */
336typedef struct {
337    /**
338     * This field is a hint that a port will have a number of integer
339     * registers that need to be saved when an interrupt occurs or
340     * when a context switch occurs at the end of an ISR.
341     */
342    uint32_t   special_interrupt_register;
343} CPU_Interrupt_frame;
344
345/** @} */
346
347/**
348 * @defgroup CPUInterrupt Processor Dependent Interrupt Management
349 */
350/**@{**/
351
352/*
353 *  Nothing prevents the porter from declaring more CPU specific variables.
354 *
355 *  Port Specific Information:
356 *
357 *  XXX document implementation including references if appropriate
358 */
359
360/* XXX: if needed, put more variables here */
361
362/**
363 * Amount of extra stack (above minimum stack size) required by
364 * MPCI receive server thread.  Remember that in a multiprocessor
365 * system this thread must exist and be able to process all directives.
366 *
367 * Port Specific Information:
368 *
369 * XXX document implementation including references if appropriate
370 */
371#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
372
373/**
374 * This defines the number of entries in the @ref _ISR_Vector_table managed
375 * by RTEMS.
376 *
377 * Port Specific Information:
378 *
379 * XXX document implementation including references if appropriate
380 */
381#define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
382
383/** This defines the highest interrupt vector number for this port. */
384#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
385
386/**
387 * This is defined if the port has a special way to report the ISR nesting
388 * level.  Most ports maintain the variable @a _ISR_Nest_level.
389 */
390#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
391
392/** @} */
393
394/**
395 * @ingroup CPUContext
396 *
397 * Should be large enough to run all RTEMS tests.  This ensures
398 * that a "reasonable" small application should not have any problems.
399 *
400 * Port Specific Information:
401 *
402 * XXX document implementation including references if appropriate
403 */
404#define CPU_STACK_MINIMUM_SIZE          (2048L)
405
406#ifdef __m32cm_cpu__
407  #define CPU_SIZEOF_POINTER 4
408#else
409  #define CPU_SIZEOF_POINTER 2
410#endif
411
412/**
413 * CPU's worst alignment requirement for data types on a byte boundary.  This
414 * alignment does not take into account the requirements for the stack.
415 *
416 * Port Specific Information:
417 *
418 * XXX document implementation including references if appropriate
419 */
420#define CPU_ALIGNMENT              2
421
422/**
423 * This number corresponds to the byte alignment requirement for the
424 * heap handler.  This alignment requirement may be stricter than that
425 * for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
426 * common for the heap to follow the same alignment requirement as
427 * @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
428 * the heap, then this should be set to @ref CPU_ALIGNMENT.
429 *
430 * NOTE:  This does not have to be a power of 2 although it should be
431 *        a multiple of 2 greater than or equal to 2.  The requirement
432 *        to be a multiple of 2 is because the heap uses the least
433 *        significant field of the front and back flags to indicate
434 *        that a block is in use or free.  So you do not want any odd
435 *        length blocks really putting length data in that bit.
436 *
437 *        On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
438 *        have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
439 *        elements allocated from the heap meet all restrictions.
440 *
441 * Port Specific Information:
442 *
443 * XXX document implementation including references if appropriate
444 */
445#define CPU_HEAP_ALIGNMENT         4
446
447/**
448 * This number corresponds to the byte alignment requirement for the
449 * stack.  This alignment requirement may be stricter than that for the
450 * data types alignment specified by @ref CPU_ALIGNMENT.  If the
451 * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
452 * set to 0.
453 *
454 * NOTE: This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
455 *
456 * Port Specific Information:
457 *
458 * XXX document implementation including references if appropriate
459 */
460#define CPU_STACK_ALIGNMENT        0
461
462#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
463
464/*
465 *  ISR handler macros
466 */
467
468/**
469 * @ingroup CPUInterrupt
470 *
471 * Support routine to initialize the RTEMS vector table after it is allocated.
472 *
473 * Port Specific Information:
474 *
475 * XXX document implementation including references if appropriate
476 */
477#define _CPU_Initialize_vectors()
478
479/**
480 * @ingroup CPUInterrupt
481 *
482 * Disable all interrupts for an RTEMS critical section.  The previous
483 * level is returned in @a _isr_cookie.
484 *
485 * @param[out] _isr_cookie will contain the previous level cookie
486 *
487 * Port Specific Information:
488 *
489 * XXX document implementation including references if appropriate
490 */
491#define _CPU_ISR_Disable( _isr_cookie ) \
492  do { \
493    int _flg; \
494    m32c_get_flg( _flg ); \
495    _isr_cookie = _flg; \
496    __asm__ volatile( "fclr I" ); \
497  } while(0)
498
499/**
500 * @ingroup CPUInterrupt
501 *
502 * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
503 * This indicates the end of an RTEMS critical section.  The parameter
504 * @a _isr_cookie is not modified.
505 *
506 * @param[in] _isr_cookie contain the previous level cookie
507 *
508 * Port Specific Information:
509 *
510 * XXX document implementation including references if appropriate
511 */
512#define _CPU_ISR_Enable(_isr_cookie) \
513  do { \
514    int _flg = (int) (_isr_cookie); \
515    m32c_set_flg( _flg ); \
516  } while(0)
517
518/**
519 * @ingroup CPUInterrupt
520 *
521 * This temporarily restores the interrupt to @a _isr_cookie before immediately
522 * disabling them again.  This is used to divide long RTEMS critical
523 * sections into two or more parts.  The parameter @a _isr_cookie is not
524 * modified.
525 *
526 * @param[in] _isr_cookie contain the previous level cookie
527 *
528 * Port Specific Information:
529 *
530 * XXX document implementation including references if appropriate
531 */
532#define _CPU_ISR_Flash( _isr_cookie ) \
533  do { \
534    int _flg = (int) (_isr_cookie); \
535    m32c_set_flg( _flg ); \
536    __asm__ volatile( "fclr I" ); \
537  } while(0)
538
539RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
540{
541  return ( level & 0x40 ) != 0;
542}
543
544/**
545 * @ingroup CPUInterrupt
546 *
547 * This routine and @ref _CPU_ISR_Get_level
548 * Map the interrupt level in task mode onto the hardware that the CPU
549 * actually provides.  Currently, interrupt levels which do not
550 * map onto the CPU in a generic fashion are undefined.  Someday,
551 * it would be nice if these were "mapped" by the application
552 * via a callout.  For example, m68k has 8 levels 0 - 7, levels
553 * 8 - 255 would be available for bsp/application specific meaning.
554 *This could be used to manage a programmable interrupt controller
555 * via the rtems_task_mode directive.
556 *
557 * Port Specific Information:
558 *
559 * XXX document implementation including references if appropriate
560 */
561#define _CPU_ISR_Set_level( _new_level ) \
562  do { \
563    if (_new_level) __asm__ volatile( "fclr I" ); \
564    else            __asm__ volatile( "fset I" ); \
565  } while(0)
566
567/**
568 * @ingroup CPUInterrupt
569 *
570 * Return the current interrupt disable level for this task in
571 * the format used by the interrupt level portion of the task mode.
572 *
573 * NOTE: This routine usually must be implemented as a subroutine.
574 *
575 * Port Specific Information:
576 *
577 * XXX document implementation including references if appropriate
578 */
579uint32_t   _CPU_ISR_Get_level( void );
580
581/* end of ISR handler macros */
582
583/* Context handler macros */
584
585/**
586 * @ingroup CPUContext
587 *
588 * Initialize the context to a state suitable for starting a
589 * task after a context restore operation.  Generally, this
590 * involves:
591 *
592 *    - setting a starting address
593 *    - preparing the stack
594 *    - preparing the stack and frame pointers
595 *    - setting the proper interrupt level in the context
596 *    - initializing the floating point context
597 *
598 * This routine generally does not set any unnecessary register
599 * in the context.  The state of the "general data" registers is
600 * undefined at task start time.
601 *
602 * @param[in] _the_context is the context structure to be initialized
603 * @param[in] _stack_base is the lowest physical address of this task's stack
604 * @param[in] _size is the size of this task's stack
605 * @param[in] _isr is the interrupt disable level
606 * @param[in] _entry_point is the thread's entry point.  This is
607 *        always @a _Thread_Handler
608 * @param[in] _is_fp is TRUE if the thread is to be a floating
609 *       point thread.  This is typically only used on CPUs where the
610 *       FPU may be easily disabled by software such as on the SPARC
611 *       where the PSR contains an enable FPU bit.
612 * @param[in] tls_area is the thread-local storage (TLS) area
613 *
614 * Port Specific Information:
615 *
616 * XXX document implementation including references if appropriate
617 */
618void _CPU_Context_Initialize(
619  Context_Control  *the_context,
620  uint32_t         *stack_base,
621  size_t            size,
622  uint32_t          new_level,
623  void             *entry_point,
624  bool              is_fp,
625  void             *tls_area
626);
627
628/**
629 * This routine is responsible for somehow restarting the currently
630 * executing task.  If you are lucky, then all that is necessary
631 * is restoring the context.  Otherwise, there will need to be
632 * a special assembly routine which does something special in this
633 * case.  For many ports, simply adding a label to the restore path
634 * of @ref _CPU_Context_switch will work.  On other ports, it may be
635 * possibly to load a few arguments and jump to the restore path. It will
636 * not work if restarting self conflicts with the stack frame
637 * assumptions of restoring a context.
638 *
639 * Port Specific Information:
640 *
641 * XXX document implementation including references if appropriate
642 */
643void _CPU_Context_Restart_self(
644  Context_Control  *the_context
645) RTEMS_NO_RETURN;
646
647/**
648 * This routine initializes the FP context area passed to it to.
649 * There are a few standard ways in which to initialize the
650 * floating point context.  The code included for this macro assumes
651 * that this is a CPU in which a "initial" FP context was saved into
652 * @a _CPU_Null_fp_context and it simply copies it to the destination
653 * context passed to it.
654 *
655 * Other floating point context save/restore models include:
656 *   -# not doing anything, and
657 *   -# putting a "null FP status word" in the correct place in the FP context.
658 *
659 * @param[in] _destination is the floating point context area
660 *
661 * Port Specific Information:
662 *
663 * XXX document implementation including references if appropriate
664 */
665#define _CPU_Context_Initialize_fp( _destination ) \
666  { \
667   *(*(_destination)) = _CPU_Null_fp_context; \
668  }
669
670/* end of Context handler macros */
671
672/* Fatal Error manager macros */
673
674/**
675 * This routine copies _error into a known place -- typically a stack
676 * location or a register, optionally disables interrupts, and
677 * halts/stops the CPU.
678 *
679 * Port Specific Information:
680 *
681 * XXX document implementation including references if appropriate
682 */
683#define _CPU_Fatal_halt( _source, _error ) \
684  { \
685  }
686
687/* end of Fatal Error manager macros */
688
689#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
690
691/* functions */
692
693/**
694 * This routine performs CPU dependent initialization.
695 *
696 * Port Specific Information:
697 *
698 * XXX document implementation including references if appropriate
699 */
700void _CPU_Initialize(void);
701
702/**
703 * @ingroup CPUInterrupt
704 *
705 * This routine installs a "raw" interrupt handler directly into the
706 * processor's vector table.
707 *
708 * @param[in] vector is the vector number
709 * @param[in] new_handler is the raw ISR handler to install
710 * @param[in] old_handler is the previously installed ISR Handler
711 *
712 * Port Specific Information:
713 *
714 * XXX document implementation including references if appropriate
715 */
716void _CPU_ISR_install_raw_handler(
717  uint32_t    vector,
718  proc_ptr    new_handler,
719  proc_ptr   *old_handler
720);
721
722/**
723 * @ingroup CPUInterrupt
724 *
725 * This routine installs an interrupt vector.
726 *
727 * @param[in] vector is the vector number
728 * @param[in] new_handler is the RTEMS ISR handler to install
729 * @param[in] old_handler is the previously installed ISR Handler
730 *
731 * Port Specific Information:
732 *
733 * XXX document implementation including references if appropriate
734 */
735void _CPU_ISR_install_vector(
736  uint32_t    vector,
737  proc_ptr    new_handler,
738  proc_ptr   *old_handler
739);
740
741/**
742 * This routine is the CPU dependent IDLE thread body.
743 *
744 * NOTE:  It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY
745 *        is TRUE.
746 *
747 * Port Specific Information:
748 *
749 * XXX document implementation including references if appropriate
750 */
751void *_CPU_Thread_Idle_body( uintptr_t ignored );
752
753/**
754 * @ingroup CPUContext
755 *
756 * This routine switches from the run context to the heir context.
757 *
758 * @param[in] run points to the context of the currently executing task
759 * @param[in] heir points to the context of the heir task
760 *
761 * Port Specific Information:
762 *
763 * XXX document implementation including references if appropriate
764 */
765void _CPU_Context_switch(
766  Context_Control  *run,
767  Context_Control  *heir
768);
769
770/**
771 * @ingroup CPUContext
772 *
773 * This routine is generally used only to restart self in an
774 * efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
775 *
776 * @param[in] new_context points to the context to be restored.
777 *
778 * NOTE: May be unnecessary to reload some registers.
779 *
780 * Port Specific Information:
781 *
782 * XXX document implementation including references if appropriate
783 */
784void _CPU_Context_restore(
785  Context_Control *new_context
786) RTEMS_NO_RETURN;
787
788/* FIXME */
789typedef CPU_Interrupt_frame CPU_Exception_frame;
790
791void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
792
793/**
794 * @ingroup CPUEndian
795 *
796 * The following routine swaps the endian format of an unsigned int.
797 * It must be static because it is referenced indirectly.
798 *
799 * This version will work on any processor, but if there is a better
800 * way for your CPU PLEASE use it.  The most common way to do this is to:
801 *
802 *    swap least significant two bytes with 16-bit rotate
803 *    swap upper and lower 16-bits
804 *    swap most significant two bytes with 16-bit rotate
805 *
806 * Some CPUs have special instructions which swap a 32-bit quantity in
807 * a single instruction (e.g. i486).  It is probably best to avoid
808 * an "endian swapping control bit" in the CPU.  One good reason is
809 * that interrupts would probably have to be disabled to ensure that
810 * an interrupt does not try to access the same "chunk" with the wrong
811 * endian.  Another good reason is that on some CPUs, the endian bit
812 * endianness for ALL fetches -- both code and data -- so the code
813 * will be fetched incorrectly.
814 *
815 * @param[in] value is the value to be swapped
816 * @return the value after being endian swapped
817 *
818 * Port Specific Information:
819 *
820 * XXX document implementation including references if appropriate
821 */
822static inline uint32_t CPU_swap_u32(
823  uint32_t value
824)
825{
826  uint32_t byte1, byte2, byte3, byte4, swapped;
827
828  byte4 = (value >> 24) & 0xff;
829  byte3 = (value >> 16) & 0xff;
830  byte2 = (value >> 8)  & 0xff;
831  byte1 =  value        & 0xff;
832
833  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
834  return swapped;
835}
836
837/**
838 * @ingroup CPUEndian
839 *
840 * This routine swaps a 16 bir quantity.
841 *
842 * @param[in] value is the value to be swapped
843 * @return the value after being endian swapped
844 */
845#define CPU_swap_u16( value ) \
846  (((value&0xff) << 8) | ((value >> 8)&0xff))
847
848typedef uint32_t CPU_Counter_ticks;
849
850uint32_t _CPU_Counter_frequency( void );
851
852CPU_Counter_ticks _CPU_Counter_read( void );
853
854static inline CPU_Counter_ticks _CPU_Counter_difference(
855  CPU_Counter_ticks second,
856  CPU_Counter_ticks first
857)
858{
859  return second - first;
860}
861
862/** Type that can store a 32-bit integer or a pointer. */
863typedef unsigned long CPU_Uint32ptr;
864
865#ifdef __cplusplus
866}
867#endif
868
869#endif
Note: See TracBrowser for help on using the repository browser.