source: rtems/cpukit/score/cpu/m32c/cpu_asm.c @ 28352fae

4.104.11
Last change on this file since 28352fae was 28352fae, checked in by Ralf Corsepius <ralf.corsepius@…>, on Nov 29, 2009 at 1:51:53 PM

Whitespace removal.

  • Property mode set to 100644
File size: 3.4 KB
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1/*  cpu_asm.c  ===> cpu_asm.S or cpu_asm.s
2 *
3 *  This file contains the basic algorithms for all assembly code used
4 *  in an specific CPU port of RTEMS.  These algorithms must be implemented
5 *  in assembly language
6 *
7 *  NOTE:  This is supposed to be a .S or .s file NOT a C file.
8 *
9 *  M32C does not yet have interrupt support.  When this functionality
10 *  is written, this file should become obsolete.
11 *
12 *  COPYRIGHT (c) 1989-2008.
13 *  On-Line Applications Research Corporation (OAR).
14 *
15 *  The license and distribution terms for this file may be
16 *  found in the file LICENSE in this distribution or at
17 *  http://www.rtems.com/license/LICENSE.
18 *
19 *  $Id$
20 */
21
22/*
23 *  This is supposed to be an assembly file.  This means that system.h
24 *  and cpu.h should not be included in a "real" cpu_asm file.  An
25 *  implementation in assembly should include "cpu_asm.h>
26 */
27
28#include <rtems/system.h>
29#include <rtems/score/cpu.h>
30
31/*  void __ISR_Handler()
32 *
33 *  This routine provides the RTEMS interrupt management.
34 *
35 *  NO_CPU Specific Information:
36 *
37 *  XXX document implementation including references if appropriate
38 */
39
40void _ISR_Handler(void)
41{
42   /*
43    *  This discussion ignores a lot of the ugly details in a real
44    *  implementation such as saving enough registers/state to be
45    *  able to do something real.  Keep in mind that the goal is
46    *  to invoke a user's ISR handler which is written in C and
47    *  uses a certain set of registers.
48    *
49    *  Also note that the exact order is to a large extent flexible.
50    *  Hardware will dictate a sequence for a certain subset of
51    *  _ISR_Handler while requirements for setting
52    */
53
54  /*
55   *  At entry to "common" _ISR_Handler, the vector number must be
56   *  available.  On some CPUs the hardware puts either the vector
57   *  number or the offset into the vector table for this ISR in a
58   *  known place.  If the hardware does not give us this information,
59   *  then the assembly portion of RTEMS for this port will contain
60   *  a set of distinct interrupt entry points which somehow place
61   *  the vector number in a known place (which is safe if another
62   *  interrupt nests this one) and branches to _ISR_Handler.
63   *
64   *  save some or all context on stack
65   *  may need to save some special interrupt information for exit
66   *
67   *  #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
68   *    if ( _ISR_Nest_level == 0 )
69   *      switch to software interrupt stack
70   *  #endif
71   *
72   *  _ISR_Nest_level++;
73   *
74   *  _Thread_Dispatch_disable_level++;
75   *
76   *  (*_ISR_Vector_table[ vector ])( vector );
77   *
78   *  _Thread_Dispatch_disable_level--;
79   *
80   *  --_ISR_Nest_level;
81   *
82   *  if ( _ISR_Nest_level )
83   *    goto the label "exit interrupt (simple case)"
84   *
85   *  if ( _Thread_Dispatch_disable_level )
86   *    _ISR_Signals_to_thread_executing = FALSE;
87   *    goto the label "exit interrupt (simple case)"
88   *
89   *  if ( _Context_Switch_necessary || _ISR_Signals_to_thread_executing ) {
90   *    _ISR_Signals_to_thread_executing = FALSE;
91   *    call _Thread_Dispatch() or prepare to return to _ISR_Dispatch
92   *    prepare to get out of interrupt
93   *    return from interrupt  (maybe to _ISR_Dispatch)
94   *
95   *  LABEL "exit interrupt (simple case):
96   *  #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
97   *    if outermost interrupt
98   *      restore stack
99   *  #endif
100   *  prepare to get out of interrupt
101   *  return from interrupt
102   */
103}
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