source: rtems/cpukit/score/cpu/m32c/cpu.c @ 55b115ec

4.104.115
Last change on this file since 55b115ec was 55b115ec, checked in by Joel Sherrill <joel.sherrill@…>, on 10/28/08 at 21:44:58

2008-10-28 Joel Sherrill <joel.sherrill@…>

  • context_init.c, context_switch.S, cpu.c, cpu_asm.c: Correct file headers.
  • Property mode set to 100644
File size: 3.4 KB
Line 
1/*
2 *  XXX CPU Dependent Source
3 *
4 *  COPYRIGHT (c) 1989-1999.
5 *  On-Line Applications Research Corporation (OAR).
6 *
7 *  The license and distribution terms for this file may be
8 *  found in the file LICENSE in this distribution or at
9 *  http://www.rtems.com/license/LICENSE.
10 *
11 *  $Id$
12 */
13
14#include <rtems/system.h>
15#include <rtems/score/isr.h>
16#include <varvects.h>
17
18/*  _CPU_Initialize
19 *
20 *  This routine performs processor dependent initialization.
21 *
22 *  INPUT PARAMETERS:
23 *    thread_dispatch - address of disptaching routine
24 *
25 *  NO_CPU Specific Information:
26 *
27 *  XXX document implementation including references if appropriate
28 */
29void _CPU_Initialize(
30  void      (*thread_dispatch)      /* ignored on this CPU */
31)
32{
33  asm volatile( "ldc    #__var_vects,intb" );
34}
35
36/*
37 *  This routine returns the current interrupt level.
38 *
39 *  NO_CPU Specific Information:
40 *
41 *  XXX document implementation including references if appropriate
42 */
43 
44uint32_t   _CPU_ISR_Get_level( void )
45{
46  int flag;
47  m32c_get_flg( flag );
48
49  return ((flag & 0x40) ? 0 : 1);
50}
51
52/*PAGE
53 *
54 *  _CPU_ISR_install_raw_handler
55 *
56 *  NO_CPU Specific Information:
57 *
58 *  XXX document implementation including references if appropriate
59 */
60 
61void _CPU_ISR_install_raw_handler(
62  uint32_t    vector,
63  proc_ptr    new_handler,
64  proc_ptr   *old_handler
65)
66{
67  /*
68   *  This is where we install the interrupt handler into the "raw" interrupt
69   *  table used by the CPU to dispatch interrupt handlers.
70   */
71  _set_var_vect(new_handler,vector);
72}
73
74/*PAGE
75 *
76 *  _CPU_ISR_install_vector
77 *
78 *  This kernel routine installs the RTEMS handler for the
79 *  specified vector.
80 *
81 *  Input parameters:
82 *    vector      - interrupt vector number
83 *    old_handler - former ISR for this vector number
84 *    new_handler - replacement ISR for this vector number
85 *
86 *  Output parameters:  NONE
87 *
88 *
89 *  NO_CPU Specific Information:
90 *
91 *  XXX document implementation including references if appropriate
92 */
93
94void _CPU_ISR_install_vector(
95  uint32_t    vector,
96  proc_ptr    new_handler,
97  proc_ptr   *old_handler
98)
99{
100   *old_handler = _ISR_Vector_table[ vector ];
101
102   /*
103    *  If the interrupt vector table is a table of pointer to isr entry
104    *  points, then we need to install the appropriate RTEMS interrupt
105    *  handler for this vector number.
106    */
107
108   _CPU_ISR_install_raw_handler( vector, new_handler, old_handler );
109
110   /*
111    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
112    *  be used by the _ISR_Handler so the user gets control.
113    */
114
115    _ISR_Vector_table[ vector ] = new_handler;
116}
117
118/*PAGE
119 *
120 *  _CPU_Install_interrupt_stack
121 *
122 *  NO_CPU Specific Information:
123 *
124 *  XXX document implementation including references if appropriate
125 */
126
127void _CPU_Install_interrupt_stack( void )
128{
129}
130
131/*PAGE
132 *
133 *  _CPU_Thread_Idle_body
134 *
135 *  NOTES:
136 *
137 *  1. This is the same as the regular CPU independent algorithm.
138 *
139 *  2. If you implement this using a "halt", "idle", or "shutdown"
140 *     instruction, then don't forget to put it in an infinite loop.
141 *
142 *  3. Be warned. Some processors with onboard DMA have been known
143 *     to stop the DMA if the CPU were put in IDLE mode.  This might
144 *     also be a problem with other on-chip peripherals.  So use this
145 *     hook with caution.
146 *
147 *  NO_CPU Specific Information:
148 *
149 *  XXX document implementation including references if appropriate
150 */
151
152void *_CPU_Thread_Idle_body( uint32_t ignored )
153{
154
155  for( ; ; )
156    /* insert your "halt" instruction here */ ;
157}
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