source: rtems/cpukit/score/cpu/m32c/cpu.c @ 2afb22b

5
Last change on this file since 2afb22b was c499856, checked in by Chris Johns <chrisj@…>, on 03/20/14 at 21:10:47

Change all references of rtems.com to rtems.org.

  • Property mode set to 100644
File size: 3.2 KB
Line 
1/**
2 *  @file
3 *
4 *  @brief M32C CPU Dependent Source
5 */
6
7/*
8 *  COPYRIGHT (c) 1989-1999.
9 *  On-Line Applications Research Corporation (OAR).
10 *
11 *  The license and distribution terms for this file may be
12 *  found in the file LICENSE in this distribution or at
13 *  http://www.rtems.org/license/LICENSE.
14 */
15
16#ifdef HAVE_CONFIG_H
17#include "config.h"
18#endif
19
20#include <rtems/system.h>
21#include <rtems/score/isr.h>
22#include <varvects.h>
23
24/*  _CPU_Initialize
25 *
26 *  This routine performs processor dependent initialization.
27 *
28 *  INPUT PARAMETERS: NONE
29 *
30 *  NO_CPU Specific Information:
31 *
32 *  XXX document implementation including references if appropriate
33 */
34
35void _CPU_Initialize(void)
36{
37  #if !defined(__r8c_cpu__)
38    __asm__ volatile( "ldc    #__var_vects,intb" );
39  #endif
40}
41
42/*
43 *  This routine returns the current interrupt level.
44 *
45 *  NO_CPU Specific Information:
46 *
47 *  XXX document implementation including references if appropriate
48 */
49
50uint32_t   _CPU_ISR_Get_level( void )
51{
52  int flag;
53  m32c_get_flg( flag );
54
55  return ((flag & 0x40) ? 0 : 1);
56}
57
58/*
59 *  _CPU_ISR_install_raw_handler
60 *
61 *  NO_CPU Specific Information:
62 *
63 *  XXX document implementation including references if appropriate
64 */
65
66void _CPU_ISR_install_raw_handler(
67  uint32_t    vector,
68  proc_ptr    new_handler,
69  proc_ptr   *old_handler
70)
71{
72  /*
73   *  This is where we install the interrupt handler into the "raw" interrupt
74   *  table used by the CPU to dispatch interrupt handlers.
75   */
76#if defined(__r8c_cpu__)
77  #warning "_CPU_ISR_install_raw_handler not implemented on R8C"
78#else
79  _set_var_vect(new_handler,vector);
80#endif
81}
82
83/*
84 *  _CPU_ISR_install_vector
85 *
86 *  NO_CPU Specific Information:
87 *
88 *  XXX document implementation including references if appropriate
89 */
90
91void _CPU_ISR_install_vector(
92  uint32_t    vector,
93  proc_ptr    new_handler,
94  proc_ptr   *old_handler
95)
96{
97   *old_handler = _ISR_Vector_table[ vector ];
98
99   /*
100    *  If the interrupt vector table is a table of pointer to isr entry
101    *  points, then we need to install the appropriate RTEMS interrupt
102    *  handler for this vector number.
103    */
104
105   _CPU_ISR_install_raw_handler( vector, new_handler, old_handler );
106
107   /*
108    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
109    *  be used by the _ISR_Handler so the user gets control.
110    */
111
112    _ISR_Vector_table[ vector ] = new_handler;
113}
114
115/*
116 *  _CPU_Install_interrupt_stack
117 *
118 *  NO_CPU Specific Information:
119 *
120 *  XXX document implementation including references if appropriate
121 */
122
123void _CPU_Install_interrupt_stack( void )
124{
125}
126
127/*
128 *  _CPU_Thread_Idle_body
129 *
130 *  NOTES:
131 *
132 *  1. This is the same as the regular CPU independent algorithm.
133 *
134 *  2. If you implement this using a "halt", "idle", or "shutdown"
135 *     instruction, then don't forget to put it in an infinite loop.
136 *
137 *  3. Be warned. Some processors with onboard DMA have been known
138 *     to stop the DMA if the CPU were put in IDLE mode.  This might
139 *     also be a problem with other on-chip peripherals.  So use this
140 *     hook with caution.
141 *
142 *  NO_CPU Specific Information:
143 *
144 *  XXX document implementation including references if appropriate
145 */
146
147void *_CPU_Thread_Idle_body( uintptr_t ignored )
148{
149
150  for( ; ; )
151    /* insert your "halt" instruction here */ ;
152}
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