source: rtems/cpukit/score/cpu/lm32/rtems/score/cpu.h @ f82752a4

4.115
Last change on this file since f82752a4 was f82752a4, checked in by Daniel Hellstrom <daniel@…>, on Jun 4, 2014 at 9:23:34 AM

Let CPU/BSP Fatal handler have access to source

Without the source the error code does not say that much.
Let it be up to the CPU/BSP to determine the error code
reported on fatal shutdown.

This patch does not change the current behaviour, just
adds the option to handle the source of the fatal halt.

  • Property mode set to 100644
File size: 40.1 KB
Line 
1/**
2 * @file
3 *
4 * @brief LM32 CPU Department Source
5 *
6 * This include file contains information pertaining to the LM32
7 * processor.
8 */
9
10/*
11 *  COPYRIGHT (c) 1989-2008.
12 *  On-Line Applications Research Corporation (OAR).
13 *
14 *  The license and distribution terms for this file may be
15 *  found in the file LICENSE in this distribution or at
16 *  http://www.rtems.org/license/LICENSE.
17 */
18
19#ifndef _RTEMS_SCORE_CPU_H
20#define _RTEMS_SCORE_CPU_H
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26#include <rtems/score/types.h>
27#include <rtems/score/lm32.h>
28
29/* conditional compilation parameters */
30
31/**
32 * Should the calls to @ref _Thread_Enable_dispatch be inlined?
33 *
34 * If TRUE, then they are inlined.
35 * If FALSE, then a subroutine call is made.
36 *
37 * This conditional is an example of the classic trade-off of size
38 * versus speed.  Inlining the call (TRUE) typically increases the
39 * size of RTEMS while speeding up the enabling of dispatching.
40 *
41 * NOTE: In general, the @ref _Thread_Dispatch_disable_level will
42 * only be 0 or 1 unless you are in an interrupt handler and that
43 * interrupt handler invokes the executive.]  When not inlined
44 * something calls @ref _Thread_Enable_dispatch which in turns calls
45 * @ref _Thread_Dispatch.  If the enable dispatch is inlined, then
46 * one subroutine call is avoided entirely.
47 *
48 * Port Specific Information:
49 *
50 * XXX document implementation including references if appropriate
51 */
52#define CPU_INLINE_ENABLE_DISPATCH       FALSE
53
54/**
55 * Should the body of the search loops in _Thread_queue_Enqueue_priority
56 * be unrolled one time?  In unrolled each iteration of the loop examines
57 * two "nodes" on the chain being searched.  Otherwise, only one node
58 * is examined per iteration.
59 *
60 * If TRUE, then the loops are unrolled.
61 * If FALSE, then the loops are not unrolled.
62 *
63 * The primary factor in making this decision is the cost of disabling
64 * and enabling interrupts (_ISR_Flash) versus the cost of rest of the
65 * body of the loop.  On some CPUs, the flash is more expensive than
66 * one iteration of the loop body.  In this case, it might be desirable
67 * to unroll the loop.  It is important to note that on some CPUs, this
68 * code is the longest interrupt disable period in RTEMS.  So it is
69 * necessary to strike a balance when setting this parameter.
70 *
71 * Port Specific Information:
72 *
73 * XXX document implementation including references if appropriate
74 */
75#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
76
77/**
78 * Does RTEMS manage a dedicated interrupt stack in software?
79 *
80 * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
81 * If FALSE, nothing is done.
82 *
83 * If the CPU supports a dedicated interrupt stack in hardware,
84 * then it is generally the responsibility of the BSP to allocate it
85 * and set it up.
86 *
87 * If the CPU does not support a dedicated interrupt stack, then
88 * the porter has two options: (1) execute interrupts on the
89 * stack of the interrupted task, and (2) have RTEMS manage a dedicated
90 * interrupt stack.
91 *
92 * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
93 *
94 * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
95 * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
96 * possible that both are FALSE for a particular CPU.  Although it
97 * is unclear what that would imply about the interrupt processing
98 * procedure on that CPU.
99 *
100 * Port Specific Information:
101 *
102 * XXX document implementation including references if appropriate
103 */
104#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
105
106/**
107 * Does the CPU follow the simple vectored interrupt model?
108 *
109 * If TRUE, then RTEMS allocates the vector table it internally manages.
110 * If FALSE, then the BSP is assumed to allocate and manage the vector
111 * table
112 *
113 * Port Specific Information:
114 *
115 * XXX document implementation including references if appropriate
116 */
117#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
118
119/**
120 * Does this CPU have hardware support for a dedicated interrupt stack?
121 *
122 * If TRUE, then it must be installed during initialization.
123 * If FALSE, then no installation is performed.
124 *
125 * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
126 *
127 * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
128 * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
129 * possible that both are FALSE for a particular CPU.  Although it
130 * is unclear what that would imply about the interrupt processing
131 * procedure on that CPU.
132 *
133 * Port Specific Information:
134 *
135 * XXX document implementation including references if appropriate
136 */
137#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
138
139/**
140 * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
141 *
142 * If TRUE, then the memory is allocated during initialization.
143 * If FALSE, then the memory is allocated during initialization.
144 *
145 * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
146 *
147 * Port Specific Information:
148 *
149 * XXX document implementation including references if appropriate
150 */
151#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
152
153/**
154 * Does the RTEMS invoke the user's ISR with the vector number and
155 * a pointer to the saved interrupt frame (1) or just the vector
156 * number (0)?
157 *
158 * Port Specific Information:
159 *
160 * XXX document implementation including references if appropriate
161 */
162#define CPU_ISR_PASSES_FRAME_POINTER 1
163
164/**
165 * @def CPU_HARDWARE_FP
166 *
167 * Does the CPU have hardware floating point?
168 *
169 * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
170 * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
171 *
172 * If there is a FP coprocessor such as the i387 or mc68881, then
173 * the answer is TRUE.
174 *
175 * The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
176 * It indicates whether or not this CPU model has FP support.  For
177 * example, it would be possible to have an i386_nofp CPU model
178 * which set this to false to indicate that you have an i386 without
179 * an i387 and wish to leave floating point support out of RTEMS.
180 */
181
182/**
183 * @def CPU_SOFTWARE_FP
184 *
185 * Does the CPU have no hardware floating point and GCC provides a
186 * software floating point implementation which must be context
187 * switched?
188 *
189 * This feature conditional is used to indicate whether or not there
190 * is software implemented floating point that must be context
191 * switched.  The determination of whether or not this applies
192 * is very tool specific and the state saved/restored is also
193 * compiler specific.
194 *
195 * Port Specific Information:
196 *
197 * XXX document implementation including references if appropriate
198 */
199#define CPU_HARDWARE_FP     FALSE
200#define CPU_SOFTWARE_FP     FALSE
201
202/**
203 * Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
204 *
205 * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
206 * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
207 *
208 * So far, the only CPUs in which this option has been used are the
209 * HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
210 * gcc both implicitly used the floating point registers to perform
211 * integer multiplies.  Similarly, the PowerPC port of gcc has been
212 * seen to allocate floating point local variables and touch the FPU
213 * even when the flow through a subroutine (like vfprintf()) might
214 * not use floating point formats.
215 *
216 * If a function which you would not think utilize the FP unit DOES,
217 * then one can not easily predict which tasks will use the FP hardware.
218 * In this case, this option should be TRUE.
219 *
220 * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
221 *
222 * Port Specific Information:
223 *
224 * XXX document implementation including references if appropriate
225 */
226#define CPU_ALL_TASKS_ARE_FP     FALSE
227
228/**
229 * Should the IDLE task have a floating point context?
230 *
231 * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
232 * and it has a floating point context which is switched in and out.
233 * If FALSE, then the IDLE task does not have a floating point context.
234 *
235 * Setting this to TRUE negatively impacts the time required to preempt
236 * the IDLE task from an interrupt because the floating point context
237 * must be saved as part of the preemption.
238 *
239 * Port Specific Information:
240 *
241 * XXX document implementation including references if appropriate
242 */
243#define CPU_IDLE_TASK_IS_FP      FALSE
244
245/**
246 * Should the saving of the floating point registers be deferred
247 * until a context switch is made to another different floating point
248 * task?
249 *
250 * If TRUE, then the floating point context will not be stored until
251 * necessary.  It will remain in the floating point registers and not
252 * disturned until another floating point task is switched to.
253 *
254 * If FALSE, then the floating point context is saved when a floating
255 * point task is switched out and restored when the next floating point
256 * task is restored.  The state of the floating point registers between
257 * those two operations is not specified.
258 *
259 * If the floating point context does NOT have to be saved as part of
260 * interrupt dispatching, then it should be safe to set this to TRUE.
261 *
262 * Setting this flag to TRUE results in using a different algorithm
263 * for deciding when to save and restore the floating point context.
264 * The deferred FP switch algorithm minimizes the number of times
265 * the FP context is saved and restored.  The FP context is not saved
266 * until a context switch is made to another, different FP task.
267 * Thus in a system with only one FP task, the FP context will never
268 * be saved or restored.
269 *
270 * Port Specific Information:
271 *
272 * XXX document implementation including references if appropriate
273 */
274#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
275
276/**
277 * Does this port provide a CPU dependent IDLE task implementation?
278 *
279 * If TRUE, then the routine @ref _CPU_Thread_Idle_body
280 * must be provided and is the default IDLE thread body instead of
281 * @ref _CPU_Thread_Idle_body.
282 *
283 * If FALSE, then use the generic IDLE thread body if the BSP does
284 * not provide one.
285 *
286 * This is intended to allow for supporting processors which have
287 * a low power or idle mode.  When the IDLE thread is executed, then
288 * the CPU can be powered down.
289 *
290 * The order of precedence for selecting the IDLE thread body is:
291 *
292 *   -#  BSP provided
293 *   -#  CPU dependent (if provided)
294 *   -#  generic (if no BSP and no CPU dependent)
295 *
296 * Port Specific Information:
297 *
298 * XXX document implementation including references if appropriate
299 */
300#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
301
302/**
303 * Does the stack grow up (toward higher addresses) or down
304 * (toward lower addresses)?
305 *
306 * If TRUE, then the grows upward.
307 * If FALSE, then the grows toward smaller addresses.
308 *
309 * Port Specific Information:
310 *
311 * XXX document implementation including references if appropriate
312 */
313#define CPU_STACK_GROWS_UP               FALSE
314
315/**
316 * The following is the variable attribute used to force alignment
317 * of critical RTEMS structures.  On some processors it may make
318 * sense to have these aligned on tighter boundaries than
319 * the minimum requirements of the compiler in order to have as
320 * much of the critical data area as possible in a cache line.
321 *
322 * The placement of this macro in the declaration of the variables
323 * is based on the syntactically requirements of the GNU C
324 * "__attribute__" extension.  For example with GNU C, use
325 * the following to force a structures to a 32 byte boundary.
326 *
327 *     __attribute__ ((aligned (32)))
328 *
329 * NOTE: Currently only the Priority Bit Map table uses this feature.
330 *       To benefit from using this, the data must be heavily
331 *       used so it will stay in the cache and used frequently enough
332 *       in the executive to justify turning this on.
333 *
334 * Port Specific Information:
335 *
336 * L2 cache lines are 32 bytes in Milkymist SoC
337 */
338#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32)))
339
340#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
341
342/**
343 * @defgroup CPUEndian Processor Dependent Endianness Support
344 *
345 * This group assists in issues related to processor endianness.
346 *
347 */
348/**@{**/
349
350/**
351 * Define what is required to specify how the network to host conversion
352 * routines are handled.
353 *
354 * NOTE: @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
355 * same values.
356 *
357 * @see CPU_LITTLE_ENDIAN
358 *
359 * Port Specific Information:
360 *
361 * XXX document implementation including references if appropriate
362 */
363#define CPU_BIG_ENDIAN                           TRUE
364
365/**
366 * Define what is required to specify how the network to host conversion
367 * routines are handled.
368 *
369 * NOTE: @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
370 * same values.
371 *
372 * @see CPU_BIG_ENDIAN
373 *
374 * Port Specific Information:
375 *
376 * XXX document implementation including references if appropriate
377 */
378#define CPU_LITTLE_ENDIAN                        FALSE
379
380/** @} */
381
382/**
383 * @ingroup CPUInterrupt
384 * The following defines the number of bits actually used in the
385 * interrupt field of the task mode.  How those bits map to the
386 * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
387 *
388 * Port Specific Information:
389 *
390 * XXX document implementation including references if appropriate
391 */
392#define CPU_MODES_INTERRUPT_MASK   0x00000001
393
394#define CPU_PER_CPU_CONTROL_SIZE 0
395
396/*
397 *  Processor defined structures required for cpukit/score.
398 *
399 *  Port Specific Information:
400 *
401 *  XXX document implementation including references if appropriate
402 */
403
404/* may need to put some structures here.  */
405
406typedef struct {
407  /* There is no CPU specific per-CPU state */
408} CPU_Per_CPU_control;
409
410/**
411 * @defgroup CPUContext Processor Dependent Context Management
412 *
413 * From the highest level viewpoint, there are 2 types of context to save.
414 *
415 *    -# Interrupt registers to save
416 *    -# Task level registers to save
417 *
418 * Since RTEMS handles integer and floating point contexts separately, this
419 * means we have the following 3 context items:
420 *
421 *    -# task level context stuff::  Context_Control
422 *    -# floating point task stuff:: Context_Control_fp
423 *    -# special interrupt level context :: CPU_Interrupt_frame
424 *
425 * On some processors, it is cost-effective to save only the callee
426 * preserved registers during a task context switch.  This means
427 * that the ISR code needs to save those registers which do not
428 * persist across function calls.  It is not mandatory to make this
429 * distinctions between the caller/callee saves registers for the
430 * purpose of minimizing context saved during task switch and on interrupts.
431 * If the cost of saving extra registers is minimal, simplicity is the
432 * choice.  Save the same context on interrupt entry as for tasks in
433 * this case.
434 *
435 * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
436 * care should be used in designing the context area.
437 *
438 * On some CPUs with hardware floating point support, the Context_Control_fp
439 * structure will not be used or it simply consist of an array of a
440 * fixed number of bytes.   This is done when the floating point context
441 * is dumped by a "FP save context" type instruction and the format
442 * is not really defined by the CPU.  In this case, there is no need
443 * to figure out the exact format -- only the size.  Of course, although
444 * this is enough information for RTEMS, it is probably not enough for
445 * a debugger such as gdb.  But that is another problem.
446 *
447 * Port Specific Information:
448 *
449 * XXX document implementation including references if appropriate
450 */
451/**@{**/
452
453/**
454 * This defines the minimal set of integer and processor state registers
455 * that must be saved during a voluntary context switch from one thread
456 * to another.
457 */
458typedef struct {
459  uint32_t r11;
460  uint32_t r12;
461  uint32_t r13;
462  uint32_t r14;
463  uint32_t r15;
464  uint32_t r16;
465  uint32_t r17;
466  uint32_t r18;
467  uint32_t r19;
468  uint32_t r20;
469  uint32_t r21;
470  uint32_t r22;
471  uint32_t r23;
472  uint32_t r24;
473  uint32_t r25;
474  uint32_t gp;
475  uint32_t fp;
476  uint32_t sp;
477  uint32_t ra;
478  uint32_t ie;
479  uint32_t epc;
480} Context_Control;
481
482/**
483 *
484 * This macro returns the stack pointer associated with @a _context.
485 *
486 * @param[in] _context is the thread context area to access
487 *
488 * @return This method returns the stack pointer.
489 */
490#define _CPU_Context_Get_SP( _context ) \
491  (_context)->sp
492
493/**
494 * This defines the complete set of floating point registers that must
495 * be saved during any context switch from one thread to another.
496 */
497typedef struct {
498} Context_Control_fp;
499
500/**
501 * This defines the set of integer and processor state registers that must
502 * be saved during an interrupt.  This set does not include any which are
503 * in @ref Context_Control.
504 */
505typedef struct {
506  uint32_t r1;
507  uint32_t r2;
508  uint32_t r3;
509  uint32_t r4;
510  uint32_t r5;
511  uint32_t r6;
512  uint32_t r7;
513  uint32_t r8;
514  uint32_t r9;
515  uint32_t r10;
516  uint32_t ra;
517  uint32_t ba;
518  uint32_t ea;
519} CPU_Interrupt_frame;
520
521/**
522 * This variable is optional.  It is used on CPUs on which it is difficult
523 * to generate an "uninitialized" FP context.  It is filled in by
524 * @ref _CPU_Initialize and copied into the task's FP context area during
525 * @ref _CPU_Context_Initialize.
526 *
527 * Port Specific Information:
528 *
529 * XXX document implementation including references if appropriate
530 */
531#if 0
532SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
533#endif
534
535/** @} */
536
537/**
538 * @defgroup CPUInterrupt Processor Dependent Interrupt Management
539 *
540 * On some CPUs, RTEMS supports a software managed interrupt stack.
541 * This stack is allocated by the Interrupt Manager and the switch
542 * is performed in @ref _ISR_Handler.  These variables contain pointers
543 * to the lowest and highest addresses in the chunk of memory allocated
544 * for the interrupt stack.  Since it is unknown whether the stack
545 * grows up or down (in general), this give the CPU dependent
546 * code the option of picking the version it wants to use.
547 *
548 * NOTE: These two variables are required if the macro
549 *       @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
550 *
551 * Port Specific Information:
552 *
553 * XXX document implementation including references if appropriate
554 */
555/**@{**/
556
557/*
558 * Nothing prevents the porter from declaring more CPU specific variables.
559 *
560 * Port Specific Information:
561 *
562 * XXX document implementation including references if appropriate
563 */
564
565/* XXX: if needed, put more variables here */
566
567/**
568 * @ingroup CPUContext
569 * The size of the floating point context area.  On some CPUs this
570 * will not be a "sizeof" because the format of the floating point
571 * area is not defined -- only the size is.  This is usually on
572 * CPUs with a "floating point save context" instruction.
573 *
574 * Port Specific Information:
575 *
576 * XXX document implementation including references if appropriate
577 */
578#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
579
580/**
581 * Amount of extra stack (above minimum stack size) required by
582 * MPCI receive server thread.  Remember that in a multiprocessor
583 * system this thread must exist and be able to process all directives.
584 *
585 * Port Specific Information:
586 *
587 * XXX document implementation including references if appropriate
588 */
589#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
590
591/**
592 * This defines the number of entries in the @ref _ISR_Vector_table managed
593 * by RTEMS.
594 *
595 * Port Specific Information:
596 *
597 * XXX document implementation including references if appropriate
598 */
599#define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
600
601/**
602 * This defines the highest interrupt vector number for this port.
603 */
604#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
605
606/**
607 * This is defined if the port has a special way to report the ISR nesting
608 * level.  Most ports maintain the variable @a _ISR_Nest_level.
609 */
610#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
611
612/** @} */
613
614/**
615 * @ingroup CPUContext
616 * Should be large enough to run all RTEMS tests.  This ensures
617 * that a "reasonable" small application should not have any problems.
618 *
619 * Port Specific Information:
620 *
621 * XXX document implementation including references if appropriate
622 */
623#define CPU_STACK_MINIMUM_SIZE          (1024*4)
624
625#define CPU_SIZEOF_POINTER 4
626
627/**
628 * CPU's worst alignment requirement for data types on a byte boundary.  This
629 * alignment does not take into account the requirements for the stack.
630 *
631 * Port Specific Information:
632 * The LM32 architecture manual simply states: "All memory accesses must be
633 * aligned to the size of the access", and there is no hardware support
634 * whatsoever for 64-bit numbers.
635 * (lm32_archman.pdf, July 2009, p. 15)
636 */
637#define CPU_ALIGNMENT              4
638
639/**
640 * This number corresponds to the byte alignment requirement for the
641 * heap handler.  This alignment requirement may be stricter than that
642 * for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
643 * common for the heap to follow the same alignment requirement as
644 * @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
645 * the heap, then this should be set to @ref CPU_ALIGNMENT.
646 *
647 * NOTE:  This does not have to be a power of 2 although it should be
648 *        a multiple of 2 greater than or equal to 2.  The requirement
649 *        to be a multiple of 2 is because the heap uses the least
650 *        significant field of the front and back flags to indicate
651 *        that a block is in use or free.  So you do not want any odd
652 *        length blocks really putting length data in that bit.
653 *
654 *        On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
655 *        have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
656 *        elements allocated from the heap meet all restrictions.
657 *
658 * Port Specific Information:
659 *
660 * XXX document implementation including references if appropriate
661 */
662#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
663
664/**
665 * This number corresponds to the byte alignment requirement for memory
666 * buffers allocated by the partition manager.  This alignment requirement
667 * may be stricter than that for the data types alignment specified by
668 * @ref CPU_ALIGNMENT.  It is common for the partition to follow the same
669 * alignment requirement as @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is
670 * strict enough for the partition, then this should be set to
671 * @ref CPU_ALIGNMENT.
672 *
673 * NOTE:  This does not have to be a power of 2.  It does have to
674 *        be greater or equal to than @ref CPU_ALIGNMENT.
675 *
676 * Port Specific Information:
677 *
678 * XXX document implementation including references if appropriate
679 */
680#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
681
682/**
683 * This number corresponds to the byte alignment requirement for the
684 * stack.  This alignment requirement may be stricter than that for the
685 * data types alignment specified by @ref CPU_ALIGNMENT.
686 *
687 *
688 * Port Specific Information:
689 *
690 * Stack is software-managed
691 */
692#define CPU_STACK_ALIGNMENT        CPU_ALIGNMENT
693
694/*
695 *  ISR handler macros
696 */
697
698/**
699 * @addtogroup CPUInterrupt
700 */
701/**@{**/
702
703/**
704 * Support routine to initialize the RTEMS vector table after it is allocated.
705 *
706 * Port Specific Information:
707 *
708 * XXX document implementation including references if appropriate
709 */
710#define _CPU_Initialize_vectors()
711
712/**
713 * Disable all interrupts for an RTEMS critical section.  The previous
714 * level is returned in @a _isr_cookie.
715 *
716 * @param[out] _isr_cookie will contain the previous level cookie
717 *
718 * Port Specific Information:
719 *
720 * XXX document implementation including references if appropriate
721 */
722#define _CPU_ISR_Disable( _isr_cookie ) \
723  lm32_disable_interrupts( _isr_cookie );
724
725/**
726 * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
727 * This indicates the end of an RTEMS critical section.  The parameter
728 * @a _isr_cookie is not modified.
729 *
730 * @param[in] _isr_cookie contain the previous level cookie
731 *
732 * Port Specific Information:
733 *
734 * XXX document implementation including references if appropriate
735 */
736#define _CPU_ISR_Enable( _isr_cookie ) \
737  lm32_enable_interrupts( _isr_cookie );
738
739/**
740 * This temporarily restores the interrupt to @a _isr_cookie before immediately
741 * disabling them again.  This is used to divide long RTEMS critical
742 * sections into two or more parts.  The parameter @a _isr_cookie is not
743 * modified.
744 *
745 * @param[in] _isr_cookie contain the previous level cookie
746 *
747 * Port Specific Information:
748 *
749 * XXX document implementation including references if appropriate
750 */
751#define _CPU_ISR_Flash( _isr_cookie ) \
752  lm32_flash_interrupts( _isr_cookie );
753
754/**
755 * This routine and @ref _CPU_ISR_Get_level
756 * Map the interrupt level in task mode onto the hardware that the CPU
757 * actually provides.  Currently, interrupt levels which do not
758 * map onto the CPU in a generic fashion are undefined.  Someday,
759 * it would be nice if these were "mapped" by the application
760 * via a callout.  For example, m68k has 8 levels 0 - 7, levels
761 * 8 - 255 would be available for bsp/application specific meaning.
762 * This could be used to manage a programmable interrupt controller
763 * via the rtems_task_mode directive.
764 *
765 * Port Specific Information:
766 *
767 * XXX document implementation including references if appropriate
768 */
769#define _CPU_ISR_Set_level( new_level ) \
770  { \
771    _CPU_ISR_Enable( ( new_level==0 ) ? 1 : 0 ); \
772  }
773
774/**
775 * Return the current interrupt disable level for this task in
776 * the format used by the interrupt level portion of the task mode.
777 *
778 * NOTE: This routine usually must be implemented as a subroutine.
779 *
780 * Port Specific Information:
781 *
782 * XXX document implementation including references if appropriate
783 */
784uint32_t   _CPU_ISR_Get_level( void );
785
786/* end of ISR handler macros */
787
788/** @} */
789
790/* Context handler macros */
791
792/**
793 * @ingroup CPUContext
794 * Initialize the context to a state suitable for starting a
795 * task after a context restore operation.  Generally, this
796 * involves:
797 *
798 *    - setting a starting address
799 *    - preparing the stack
800 *    - preparing the stack and frame pointers
801 *    - setting the proper interrupt level in the context
802 *    - initializing the floating point context
803 *
804 * This routine generally does not set any unnecessary register
805 * in the context.  The state of the "general data" registers is
806 * undefined at task start time.
807 *
808 * @param[in] _the_context is the context structure to be initialized
809 * @param[in] _stack_base is the lowest physical address of this task's stack
810 * @param[in] _size is the size of this task's stack
811 * @param[in] _isr is the interrupt disable level
812 * @param[in] _entry_point is the thread's entry point.  This is
813 *        always @a _Thread_Handler
814 * @param[in] _is_fp is TRUE if the thread is to be a floating
815 *       point thread.  This is typically only used on CPUs where the
816 *       FPU may be easily disabled by software such as on the SPARC
817 *       where the PSR contains an enable FPU bit.
818 *
819 * Port Specific Information:
820 *
821 * XXX document implementation including references if appropriate
822 */
823extern char _gp[];
824
825#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
826                                 _isr, _entry_point, _is_fp, _tls_area ) \
827   do { \
828     uint32_t _stack = (uint32_t)(_stack_base) + (_size) - 4; \
829     (_the_context)->gp = (uint32_t)_gp; \
830     (_the_context)->fp = (uint32_t)_stack; \
831     (_the_context)->sp = (uint32_t)_stack; \
832     (_the_context)->ra = (uint32_t)(_entry_point); \
833   } while ( 0 )
834
835/**
836 * This routine is responsible for somehow restarting the currently
837 * executing task.  If you are lucky, then all that is necessary
838 * is restoring the context.  Otherwise, there will need to be
839 * a special assembly routine which does something special in this
840 * case.  For many ports, simply adding a label to the restore path
841 * of @ref _CPU_Context_switch will work.  On other ports, it may be
842 * possibly to load a few arguments and jump to the restore path. It will
843 * not work if restarting self conflicts with the stack frame
844 * assumptions of restoring a context.
845 *
846 * Port Specific Information:
847 *
848 * XXX document implementation including references if appropriate
849 */
850#define _CPU_Context_Restart_self( _the_context ) \
851   _CPU_Context_restore( (_the_context) );
852
853/**
854 * @ingroup CPUContext
855 * The purpose of this macro is to allow the initial pointer into
856 * a floating point context area (used to save the floating point
857 * context) to be at an arbitrary place in the floating point
858 * context area.
859 *
860 * This is necessary because some FP units are designed to have
861 * their context saved as a stack which grows into lower addresses.
862 * Other FP units can be saved by simply moving registers into offsets
863 * from the base of the context area.  Finally some FP units provide
864 * a "dump context" instruction which could fill in from high to low
865 * or low to high based on the whim of the CPU designers.
866 *
867 * @param[in] _base is the lowest physical address of the floating point
868 *        context area
869 * @param[in] _offset is the offset into the floating point area
870 *
871 * Port Specific Information:
872 *
873 * XXX document implementation including references if appropriate
874 */
875#define _CPU_Context_Fp_start( _base, _offset )
876#if 0
877   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
878#endif
879
880/**
881 * This routine initializes the FP context area passed to it to.
882 * There are a few standard ways in which to initialize the
883 * floating point context.  The code included for this macro assumes
884 * that this is a CPU in which a "initial" FP context was saved into
885 * @a _CPU_Null_fp_context and it simply copies it to the destination
886 * context passed to it.
887 *
888 * Other floating point context save/restore models include:
889 *   -# not doing anything, and
890 *   -# putting a "null FP status word" in the correct place in the FP context.
891 *
892 * @param[in] _destination is the floating point context area
893 *
894 * Port Specific Information:
895 *
896 * XXX document implementation including references if appropriate
897 */
898#define _CPU_Context_Initialize_fp( _destination )
899#if 0
900  { \
901   *(*(_destination)) = _CPU_Null_fp_context; \
902  }
903#endif
904
905/* end of Context handler macros */
906
907/* Fatal Error manager macros */
908
909/**
910 * This routine copies _error into a known place -- typically a stack
911 * location or a register, optionally disables interrupts, and
912 * halts/stops the CPU.
913 *
914 * Port Specific Information:
915 *
916 * XXX document implementation including references if appropriate
917 */
918#define _CPU_Fatal_halt( _source, _error ) \
919  { \
920  }
921
922/* end of Fatal Error manager macros */
923
924/* Bitfield handler macros */
925
926/**
927 * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
928 *
929 * This set of routines are used to implement fast searches for
930 * the most important ready task.
931 */
932/**@{**/
933
934/**
935 * This definition is set to TRUE if the port uses the generic bitfield
936 * manipulation implementation.
937 */
938#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
939
940/**
941 * This definition is set to TRUE if the port uses the data tables provided
942 * by the generic bitfield manipulation implementation.
943 * This can occur when actually using the generic bitfield manipulation
944 * implementation or when implementing the same algorithm in assembly
945 * language for improved performance.  It is unlikely that a port will use
946 * the data if it has a bitfield scan instruction.
947 */
948#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
949
950/**
951 * This routine sets @a _output to the bit number of the first bit
952 * set in @a _value.  @a _value is of CPU dependent type
953 * @a Priority_bit_map_Word.  This type may be either 16 or 32 bits
954 * wide although only the 16 least significant bits will be used.
955 *
956 * There are a number of variables in using a "find first bit" type
957 * instruction.
958 *
959 *   -# What happens when run on a value of zero?
960 *   -# Bits may be numbered from MSB to LSB or vice-versa.
961 *   -# The numbering may be zero or one based.
962 *   -# The "find first bit" instruction may search from MSB or LSB.
963 *
964 * RTEMS guarantees that (1) will never happen so it is not a concern.
965 * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
966 * @ref _CPU_Priority_bits_index.  These three form a set of routines
967 * which must logically operate together.  Bits in the _value are
968 * set and cleared based on masks built by @ref _CPU_Priority_Mask.
969 * The basic major and minor values calculated by @ref _Priority_Major
970 * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
971 * to properly range between the values returned by the "find first bit"
972 * instruction.  This makes it possible for @ref _Priority_Get_highest to
973 * calculate the major and directly index into the minor table.
974 * This mapping is necessary to ensure that 0 (a high priority major/minor)
975 * is the first bit found.
976 *
977 * This entire "find first bit" and mapping process depends heavily
978 * on the manner in which a priority is broken into a major and minor
979 * components with the major being the 4 MSB of a priority and minor
980 * the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
981 * priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
982 * to the lowest priority.
983 *
984 * If your CPU does not have a "find first bit" instruction, then
985 * there are ways to make do without it.  Here are a handful of ways
986 * to implement this in software:
987 *
988@verbatim
989      - a series of 16 bit test instructions
990      - a "binary search using if's"
991      - _number = 0
992        if _value > 0x00ff
993          _value >>=8
994          _number = 8;
995
996        if _value > 0x0000f
997          _value >=8
998          _number += 4
999
1000        _number += bit_set_table[ _value ]
1001@endverbatim
1002
1003 *   where bit_set_table[ 16 ] has values which indicate the first
1004 *     bit set
1005 *
1006 * @param[in] _value is the value to be scanned
1007 * @param[in] _output is the first bit set
1008 *
1009 * Port Specific Information:
1010 *
1011 * XXX document implementation including references if appropriate
1012 */
1013
1014#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1015#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
1016  { \
1017    (_output) = 0;   /* do something to prevent warnings */ \
1018  }
1019#endif
1020
1021/* end of Bitfield handler macros */
1022
1023/** @} */
1024
1025/**
1026 * This routine builds the mask which corresponds to the bit fields
1027 * as searched by @ref _CPU_Bitfield_Find_first_bit.  See the discussion
1028 * for that routine.
1029 *
1030 * Port Specific Information:
1031 *
1032 * XXX document implementation including references if appropriate
1033 */
1034#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1035
1036#define _CPU_Priority_Mask( _bit_number ) \
1037  ( 1 << (_bit_number) )
1038
1039#endif
1040
1041/**
1042 * @ingroup CPUBitfield
1043 * This routine translates the bit numbers returned by
1044 * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
1045 * a major or minor component of a priority.  See the discussion
1046 * for that routine.
1047 *
1048 * @param[in] _priority is the major or minor number to translate
1049 *
1050 * Port Specific Information:
1051 *
1052 * XXX document implementation including references if appropriate
1053 */
1054#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1055
1056#define _CPU_Priority_bits_index( _priority ) \
1057  (_priority)
1058
1059#endif
1060
1061/* end of Priority handler macros */
1062
1063/* functions */
1064
1065/**
1066 * This routine performs CPU dependent initialization.
1067 *
1068 * Port Specific Information:
1069 *
1070 * XXX document implementation including references if appropriate
1071 */
1072void _CPU_Initialize(void);
1073
1074/**
1075 * @addtogroup CPUInterrupt
1076 */
1077/**@{**/
1078
1079/**
1080 * This routine installs a "raw" interrupt handler directly into the
1081 * processor's vector table.
1082 *
1083 * @param[in] vector is the vector number
1084 * @param[in] new_handler is the raw ISR handler to install
1085 * @param[in] old_handler is the previously installed ISR Handler
1086 *
1087 * Port Specific Information:
1088 *
1089 * XXX document implementation including references if appropriate
1090 */
1091void _CPU_ISR_install_raw_handler(
1092  uint32_t    vector,
1093  proc_ptr    new_handler,
1094  proc_ptr   *old_handler
1095);
1096
1097/**
1098 * This routine installs an interrupt vector.
1099 *
1100 * @param[in] vector is the vector number
1101 * @param[in] new_handler is the RTEMS ISR handler to install
1102 * @param[in] old_handler is the previously installed ISR Handler
1103 *
1104 * Port Specific Information:
1105 *
1106 * XXX document implementation including references if appropriate
1107 */
1108void _CPU_ISR_install_vector(
1109  uint32_t    vector,
1110  proc_ptr    new_handler,
1111  proc_ptr   *old_handler
1112);
1113
1114/**
1115 * This routine installs the hardware interrupt stack pointer.
1116 *
1117 * NOTE:  It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
1118 *        is TRUE.
1119 *
1120 * Port Specific Information:
1121 *
1122 * XXX document implementation including references if appropriate
1123 */
1124void _CPU_Install_interrupt_stack( void );
1125
1126/** @} */
1127
1128/**
1129 * This routine is the CPU dependent IDLE thread body.
1130 *
1131 * NOTE:  It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY
1132 *        is TRUE.
1133 *
1134 * Port Specific Information:
1135 *
1136 * XXX document implementation including references if appropriate
1137 */
1138void *_CPU_Thread_Idle_body( uintptr_t ignored );
1139
1140/**
1141 * @ingroup CPUContext
1142 * This routine switches from the run context to the heir context.
1143 *
1144 * @param[in] run points to the context of the currently executing task
1145 * @param[in] heir points to the context of the heir task
1146 *
1147 * Port Specific Information:
1148 *
1149 * XXX document implementation including references if appropriate
1150 */
1151void _CPU_Context_switch(
1152  Context_Control  *run,
1153  Context_Control  *heir
1154);
1155
1156/**
1157 * @addtogroup CPUContext
1158 */
1159/**@{**/
1160
1161/**
1162 * This routine is generally used only to restart self in an
1163 * efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
1164 *
1165 * @param[in] new_context points to the context to be restored.
1166 *
1167 * NOTE: May be unnecessary to reload some registers.
1168 *
1169 * Port Specific Information:
1170 *
1171 * XXX document implementation including references if appropriate
1172 */
1173void _CPU_Context_restore(
1174  Context_Control *new_context
1175) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
1176
1177/**
1178 * This routine saves the floating point context passed to it.
1179 *
1180 * @param[in] fp_context_ptr is a pointer to a pointer to a floating
1181 * point context area
1182 *
1183 * @return on output @a *fp_context_ptr will contain the address that
1184 * should be used with @ref _CPU_Context_restore_fp to restore this context.
1185 *
1186 * Port Specific Information:
1187 *
1188 * XXX document implementation including references if appropriate
1189 */
1190void _CPU_Context_save_fp(
1191  Context_Control_fp **fp_context_ptr
1192);
1193
1194/**
1195 * This routine restores the floating point context passed to it.
1196 *
1197 * @param[in] fp_context_ptr is a pointer to a pointer to a floating
1198 * point context area to restore
1199 *
1200 * @return on output @a *fp_context_ptr will contain the address that
1201 * should be used with @ref _CPU_Context_save_fp to save this context.
1202 *
1203 * Port Specific Information:
1204 *
1205 * XXX document implementation including references if appropriate
1206 */
1207void _CPU_Context_restore_fp(
1208  Context_Control_fp **fp_context_ptr
1209);
1210
1211static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
1212{
1213  /* TODO */
1214}
1215
1216static inline void _CPU_Context_validate( uintptr_t pattern )
1217{
1218  while (1) {
1219    /* TODO */
1220  }
1221}
1222
1223/** @} */
1224
1225/* FIXME */
1226typedef CPU_Interrupt_frame CPU_Exception_frame;
1227
1228void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
1229
1230/**
1231 * @ingroup CPUEndian
1232 * The following routine swaps the endian format of an unsigned int.
1233 * It must be static because it is referenced indirectly.
1234 *
1235 * This version will work on any processor, but if there is a better
1236 * way for your CPU PLEASE use it.  The most common way to do this is to:
1237 *
1238 *    swap least significant two bytes with 16-bit rotate
1239 *    swap upper and lower 16-bits
1240 *    swap most significant two bytes with 16-bit rotate
1241 *
1242 * Some CPUs have special instructions which swap a 32-bit quantity in
1243 * a single instruction (e.g. i486).  It is probably best to avoid
1244 * an "endian swapping control bit" in the CPU.  One good reason is
1245 * that interrupts would probably have to be disabled to ensure that
1246 * an interrupt does not try to access the same "chunk" with the wrong
1247 * endian.  Another good reason is that on some CPUs, the endian bit
1248 * endianness for ALL fetches -- both code and data -- so the code
1249 * will be fetched incorrectly.
1250 *
1251 * @param[in] value is the value to be swapped
1252 * @return the value after being endian swapped
1253 *
1254 * Port Specific Information:
1255 *
1256 * XXX document implementation including references if appropriate
1257 */
1258static inline uint32_t CPU_swap_u32(
1259  uint32_t value
1260)
1261{
1262  uint32_t byte1, byte2, byte3, byte4, swapped;
1263
1264  byte4 = (value >> 24) & 0xff;
1265  byte3 = (value >> 16) & 0xff;
1266  byte2 = (value >> 8)  & 0xff;
1267  byte1 =  value        & 0xff;
1268
1269  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1270  return swapped;
1271}
1272
1273/**
1274 * @ingroup CPUEndian
1275 * This routine swaps a 16 bir quantity.
1276 *
1277 * @param[in] value is the value to be swapped
1278 * @return the value after being endian swapped
1279 */
1280static inline uint16_t CPU_swap_u16(uint16_t v)
1281{
1282    return v << 8 | v >> 8;
1283}
1284
1285typedef uint32_t CPU_Counter_ticks;
1286
1287CPU_Counter_ticks _CPU_Counter_read( void );
1288
1289static inline CPU_Counter_ticks _CPU_Counter_difference(
1290  CPU_Counter_ticks second,
1291  CPU_Counter_ticks first
1292)
1293{
1294  return second - first;
1295}
1296
1297#ifdef __cplusplus
1298}
1299#endif
1300
1301#endif
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