source: rtems/cpukit/score/cpu/lm32/rtems/score/cpu.h @ 4ef13360

4.11
Last change on this file since 4ef13360 was 4ef13360, checked in by Joel Sherrill <joel.sherrill@…>, on Jul 29, 2010 at 5:51:56 PM

2010-07-29 Gedare Bloom <giddyup44@…>

PR 1635/cpukit

  • rtems/score/cpu.h, rtems/score/types.h: Refactoring of priority handling, to isolate the bitmap implementation of priorities in the supercore so that priority management is a little more modular. This change is in anticipation of scheduler implementations that can select how they manage tracking priority levels / finding the highest priority ready task. Note that most of the changes here are simple renaming, to clarify the use of the bitmap-based priority management.
  • Property mode set to 100644
File size: 40.8 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  This include file contains information pertaining to the XXX
7 *  processor.
8 *
9 *  @note This file is part of a porting template that is intended
10 *  to be used as the starting point when porting RTEMS to a new
11 *  CPU family.  The following needs to be done when using this as
12 *  the starting point for a new port:
13 *
14 *  + Anywhere there is an XXX, it should be replaced
15 *    with information about the CPU family being ported to.
16 *
17 *  + At the end of each comment section, there is a heading which
18 *    says "Port Specific Information:".  When porting to RTEMS,
19 *    add CPU family specific information in this section
20 */
21
22/*
23 *  COPYRIGHT (c) 1989-2008.
24 *  On-Line Applications Research Corporation (OAR).
25 *
26 *  The license and distribution terms for this file may be
27 *  found in the file LICENSE in this distribution or at
28 *  http://www.rtems.com/license/LICENSE.
29 *
30 *  $Id$
31 */
32
33#ifndef _RTEMS_SCORE_CPU_H
34#define _RTEMS_SCORE_CPU_H
35
36#ifdef __cplusplus
37extern "C" {
38#endif
39
40#include <rtems/score/types.h>
41#include <rtems/score/lm32.h>
42
43/* conditional compilation parameters */
44
45/**
46 *  Should the calls to @ref _Thread_Enable_dispatch be inlined?
47 *
48 *  If TRUE, then they are inlined.
49 *  If FALSE, then a subroutine call is made.
50 *
51 *  This conditional is an example of the classic trade-off of size
52 *  versus speed.  Inlining the call (TRUE) typically increases the
53 *  size of RTEMS while speeding up the enabling of dispatching.
54 *
55 *  @note In general, the @ref _Thread_Dispatch_disable_level will
56 *  only be 0 or 1 unless you are in an interrupt handler and that
57 *  interrupt handler invokes the executive.]  When not inlined
58 *  something calls @ref _Thread_Enable_dispatch which in turns calls
59 *  @ref _Thread_Dispatch.  If the enable dispatch is inlined, then
60 *  one subroutine call is avoided entirely.
61 *
62 *  Port Specific Information:
63 *
64 *  XXX document implementation including references if appropriate
65 */
66#define CPU_INLINE_ENABLE_DISPATCH       FALSE
67
68/**
69 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
70 *  be unrolled one time?  In unrolled each iteration of the loop examines
71 *  two "nodes" on the chain being searched.  Otherwise, only one node
72 *  is examined per iteration.
73 *
74 *  If TRUE, then the loops are unrolled.
75 *  If FALSE, then the loops are not unrolled.
76 *
77 *  The primary factor in making this decision is the cost of disabling
78 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
79 *  body of the loop.  On some CPUs, the flash is more expensive than
80 *  one iteration of the loop body.  In this case, it might be desirable
81 *  to unroll the loop.  It is important to note that on some CPUs, this
82 *  code is the longest interrupt disable period in RTEMS.  So it is
83 *  necessary to strike a balance when setting this parameter.
84 *
85 *  Port Specific Information:
86 *
87 *  XXX document implementation including references if appropriate
88 */
89#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
90
91/**
92 *  Does RTEMS manage a dedicated interrupt stack in software?
93 *
94 *  If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
95 *  If FALSE, nothing is done.
96 *
97 *  If the CPU supports a dedicated interrupt stack in hardware,
98 *  then it is generally the responsibility of the BSP to allocate it
99 *  and set it up.
100 *
101 *  If the CPU does not support a dedicated interrupt stack, then
102 *  the porter has two options: (1) execute interrupts on the
103 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
104 *  interrupt stack.
105 *
106 *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
107 *
108 *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
109 *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
110 *  possible that both are FALSE for a particular CPU.  Although it
111 *  is unclear what that would imply about the interrupt processing
112 *  procedure on that CPU.
113 *
114 *  Port Specific Information:
115 *
116 *  XXX document implementation including references if appropriate
117 */
118#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
119
120/**
121 *  Does the CPU follow the simple vectored interrupt model?
122 *
123 *  If TRUE, then RTEMS allocates the vector table it internally manages.
124 *  If FALSE, then the BSP is assumed to allocate and manage the vector
125 *  table
126 *
127 *  Port Specific Information:
128 *
129 *  XXX document implementation including references if appropriate
130 */
131#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
132
133/**
134 *  Does this CPU have hardware support for a dedicated interrupt stack?
135 *
136 *  If TRUE, then it must be installed during initialization.
137 *  If FALSE, then no installation is performed.
138 *
139 *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
140 *
141 *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
142 *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
143 *  possible that both are FALSE for a particular CPU.  Although it
144 *  is unclear what that would imply about the interrupt processing
145 *  procedure on that CPU.
146 *
147 *  Port Specific Information:
148 *
149 *  XXX document implementation including references if appropriate
150 */
151#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
152
153/**
154 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
155 *
156 *  If TRUE, then the memory is allocated during initialization.
157 *  If FALSE, then the memory is allocated during initialization.
158 *
159 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
160 *
161 *  Port Specific Information:
162 *
163 *  XXX document implementation including references if appropriate
164 */
165#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
166
167/**
168 *  Does the RTEMS invoke the user's ISR with the vector number and
169 *  a pointer to the saved interrupt frame (1) or just the vector
170 *  number (0)?
171 *
172 *  Port Specific Information:
173 *
174 *  XXX document implementation including references if appropriate
175 */
176#define CPU_ISR_PASSES_FRAME_POINTER 1
177
178/**
179 *  @def CPU_HARDWARE_FP
180 *
181 *  Does the CPU have hardware floating point?
182 *
183 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
184 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
185 *
186 *  If there is a FP coprocessor such as the i387 or mc68881, then
187 *  the answer is TRUE.
188 *
189 *  The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
190 *  It indicates whether or not this CPU model has FP support.  For
191 *  example, it would be possible to have an i386_nofp CPU model
192 *  which set this to false to indicate that you have an i386 without
193 *  an i387 and wish to leave floating point support out of RTEMS.
194 */
195
196/**
197 *  @def CPU_SOFTWARE_FP
198 *
199 *  Does the CPU have no hardware floating point and GCC provides a
200 *  software floating point implementation which must be context
201 *  switched?
202 *
203 *  This feature conditional is used to indicate whether or not there
204 *  is software implemented floating point that must be context
205 *  switched.  The determination of whether or not this applies
206 *  is very tool specific and the state saved/restored is also
207 *  compiler specific.
208 *
209 *  Port Specific Information:
210 *
211 *  XXX document implementation including references if appropriate
212 */
213#define CPU_HARDWARE_FP     FALSE
214#define CPU_SOFTWARE_FP     FALSE
215
216/**
217 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
218 *
219 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
220 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
221 *
222 *  So far, the only CPUs in which this option has been used are the
223 *  HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
224 *  gcc both implicitly used the floating point registers to perform
225 *  integer multiplies.  Similarly, the PowerPC port of gcc has been
226 *  seen to allocate floating point local variables and touch the FPU
227 *  even when the flow through a subroutine (like vfprintf()) might
228 *  not use floating point formats.
229 *
230 *  If a function which you would not think utilize the FP unit DOES,
231 *  then one can not easily predict which tasks will use the FP hardware.
232 *  In this case, this option should be TRUE.
233 *
234 *  If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
235 *
236 *  Port Specific Information:
237 *
238 *  XXX document implementation including references if appropriate
239 */
240#define CPU_ALL_TASKS_ARE_FP     FALSE
241
242/**
243 *  Should the IDLE task have a floating point context?
244 *
245 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
246 *  and it has a floating point context which is switched in and out.
247 *  If FALSE, then the IDLE task does not have a floating point context.
248 *
249 *  Setting this to TRUE negatively impacts the time required to preempt
250 *  the IDLE task from an interrupt because the floating point context
251 *  must be saved as part of the preemption.
252 *
253 *  Port Specific Information:
254 *
255 *  XXX document implementation including references if appropriate
256 */
257#define CPU_IDLE_TASK_IS_FP      FALSE
258
259/**
260 *  Should the saving of the floating point registers be deferred
261 *  until a context switch is made to another different floating point
262 *  task?
263 *
264 *  If TRUE, then the floating point context will not be stored until
265 *  necessary.  It will remain in the floating point registers and not
266 *  disturned until another floating point task is switched to.
267 *
268 *  If FALSE, then the floating point context is saved when a floating
269 *  point task is switched out and restored when the next floating point
270 *  task is restored.  The state of the floating point registers between
271 *  those two operations is not specified.
272 *
273 *  If the floating point context does NOT have to be saved as part of
274 *  interrupt dispatching, then it should be safe to set this to TRUE.
275 *
276 *  Setting this flag to TRUE results in using a different algorithm
277 *  for deciding when to save and restore the floating point context.
278 *  The deferred FP switch algorithm minimizes the number of times
279 *  the FP context is saved and restored.  The FP context is not saved
280 *  until a context switch is made to another, different FP task.
281 *  Thus in a system with only one FP task, the FP context will never
282 *  be saved or restored.
283 *
284 *  Port Specific Information:
285 *
286 *  XXX document implementation including references if appropriate
287 */
288#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
289
290/**
291 *  Does this port provide a CPU dependent IDLE task implementation?
292 *
293 *  If TRUE, then the routine @ref _CPU_Thread_Idle_body
294 *  must be provided and is the default IDLE thread body instead of
295 *  @ref _CPU_Thread_Idle_body.
296 *
297 *  If FALSE, then use the generic IDLE thread body if the BSP does
298 *  not provide one.
299 *
300 *  This is intended to allow for supporting processors which have
301 *  a low power or idle mode.  When the IDLE thread is executed, then
302 *  the CPU can be powered down.
303 *
304 *  The order of precedence for selecting the IDLE thread body is:
305 *
306 *    -#  BSP provided
307 *    -#  CPU dependent (if provided)
308 *    -#  generic (if no BSP and no CPU dependent)
309 *
310 *  Port Specific Information:
311 *
312 *  XXX document implementation including references if appropriate
313 */
314#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
315
316/**
317 *  Does the stack grow up (toward higher addresses) or down
318 *  (toward lower addresses)?
319 *
320 *  If TRUE, then the grows upward.
321 *  If FALSE, then the grows toward smaller addresses.
322 *
323 *  Port Specific Information:
324 *
325 *  XXX document implementation including references if appropriate
326 */
327#define CPU_STACK_GROWS_UP               FALSE
328
329/**
330 *  The following is the variable attribute used to force alignment
331 *  of critical RTEMS structures.  On some processors it may make
332 *  sense to have these aligned on tighter boundaries than
333 *  the minimum requirements of the compiler in order to have as
334 *  much of the critical data area as possible in a cache line.
335 *
336 *  The placement of this macro in the declaration of the variables
337 *  is based on the syntactically requirements of the GNU C
338 *  "__attribute__" extension.  For example with GNU C, use
339 *  the following to force a structures to a 32 byte boundary.
340 *
341 *      __attribute__ ((aligned (32)))
342 *
343 *  @note Currently only the Priority Bit Map table uses this feature.
344 *        To benefit from using this, the data must be heavily
345 *        used so it will stay in the cache and used frequently enough
346 *        in the executive to justify turning this on.
347 *
348 *  Port Specific Information:
349 *
350 *  XXX document implementation including references if appropriate
351 */
352#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (8)))
353
354/**
355 *  @defgroup CPUEndian Processor Dependent Endianness Support
356 *
357 *  This group assists in issues related to processor endianness.
358 */
359
360/**
361 *  @ingroup CPUEndian
362 *  Define what is required to specify how the network to host conversion
363 *  routines are handled.
364 *
365 *  @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
366 *  same values.
367 *
368 *  @see CPU_LITTLE_ENDIAN
369 *
370 *  Port Specific Information:
371 *
372 *  XXX document implementation including references if appropriate
373 */
374#define CPU_BIG_ENDIAN                           TRUE
375
376/**
377 *  @ingroup CPUEndian
378 *  Define what is required to specify how the network to host conversion
379 *  routines are handled.
380 *
381 *  @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
382 *  same values.
383 *
384 *  @see CPU_BIG_ENDIAN
385 *
386 *  Port Specific Information:
387 *
388 *  XXX document implementation including references if appropriate
389 */
390#define CPU_LITTLE_ENDIAN                        FALSE
391
392/**
393 *  @ingroup CPUInterrupt
394 *  The following defines the number of bits actually used in the
395 *  interrupt field of the task mode.  How those bits map to the
396 *  CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
397 *
398 *  Port Specific Information:
399 *
400 *  XXX document implementation including references if appropriate
401 */
402#define CPU_MODES_INTERRUPT_MASK   0x00000001
403
404/*
405 *  Processor defined structures required for cpukit/score.
406 *
407 *  Port Specific Information:
408 *
409 *  XXX document implementation including references if appropriate
410 */
411
412/* may need to put some structures here.  */
413
414/**
415 * @defgroup CPUContext Processor Dependent Context Management
416 *
417 *  From the highest level viewpoint, there are 2 types of context to save.
418 *
419 *     -# Interrupt registers to save
420 *     -# Task level registers to save
421 *
422 *  Since RTEMS handles integer and floating point contexts separately, this
423 *  means we have the following 3 context items:
424 *
425 *     -# task level context stuff::  Context_Control
426 *     -# floating point task stuff:: Context_Control_fp
427 *     -# special interrupt level context :: CPU_Interrupt_frame
428 *
429 *  On some processors, it is cost-effective to save only the callee
430 *  preserved registers during a task context switch.  This means
431 *  that the ISR code needs to save those registers which do not
432 *  persist across function calls.  It is not mandatory to make this
433 *  distinctions between the caller/callee saves registers for the
434 *  purpose of minimizing context saved during task switch and on interrupts.
435 *  If the cost of saving extra registers is minimal, simplicity is the
436 *  choice.  Save the same context on interrupt entry as for tasks in
437 *  this case.
438 *
439 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
440 *  care should be used in designing the context area.
441 *
442 *  On some CPUs with hardware floating point support, the Context_Control_fp
443 *  structure will not be used or it simply consist of an array of a
444 *  fixed number of bytes.   This is done when the floating point context
445 *  is dumped by a "FP save context" type instruction and the format
446 *  is not really defined by the CPU.  In this case, there is no need
447 *  to figure out the exact format -- only the size.  Of course, although
448 *  this is enough information for RTEMS, it is probably not enough for
449 *  a debugger such as gdb.  But that is another problem.
450 *
451 *  Port Specific Information:
452 *
453 *  XXX document implementation including references if appropriate
454 */
455
456/**
457 *  @ingroup CPUContext Management
458 *  This defines the minimal set of integer and processor state registers
459 *  that must be saved during a voluntary context switch from one thread
460 *  to another.
461 */
462typedef struct {
463  uint32_t r11;
464  uint32_t r12;
465  uint32_t r13;
466  uint32_t r14;
467  uint32_t r15;
468  uint32_t r16;
469  uint32_t r17;
470  uint32_t r18;
471  uint32_t r19;
472  uint32_t r20;
473  uint32_t r21;
474  uint32_t r22;
475  uint32_t r23;
476  uint32_t r24;
477  uint32_t r25;
478  uint32_t gp;
479  uint32_t fp;
480  uint32_t sp;
481  uint32_t ra;
482  uint32_t ie;
483  uint32_t epc;
484} Context_Control;
485
486/**
487 *  @ingroup CPUContext Management
488 *
489 *  This macro returns the stack pointer associated with @a _context.
490 *
491 *  @param[in] _context is the thread context area to access
492 *
493 *  @return This method returns the stack pointer.
494 */
495#define _CPU_Context_Get_SP( _context ) \
496  (_context)->sp
497
498/**
499 *  @ingroup CPUContext Management
500 *  This defines the complete set of floating point registers that must
501 *  be saved during any context switch from one thread to another.
502 */
503typedef struct {
504} Context_Control_fp;
505
506/**
507 *  @ingroup CPUContext Management
508 *  This defines the set of integer and processor state registers that must
509 *  be saved during an interrupt.  This set does not include any which are
510 *  in @ref Context_Control.
511 */
512typedef struct {
513  uint32_t r1;
514  uint32_t r2;
515  uint32_t r3;
516  uint32_t r4;
517  uint32_t r5;
518  uint32_t r6;
519  uint32_t r7;
520  uint32_t r8;
521  uint32_t r9;
522  uint32_t r10;
523  uint32_t ra;
524  uint32_t ba;
525  uint32_t ea;
526} CPU_Interrupt_frame;
527
528/**
529 *  This variable is optional.  It is used on CPUs on which it is difficult
530 *  to generate an "uninitialized" FP context.  It is filled in by
531 *  @ref _CPU_Initialize and copied into the task's FP context area during
532 *  @ref _CPU_Context_Initialize.
533 *
534 *  Port Specific Information:
535 *
536 *  XXX document implementation including references if appropriate
537 */
538#if 0
539SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
540#endif
541
542/**
543 *  @defgroup CPUInterrupt Processor Dependent Interrupt Management
544 *
545 *  On some CPUs, RTEMS supports a software managed interrupt stack.
546 *  This stack is allocated by the Interrupt Manager and the switch
547 *  is performed in @ref _ISR_Handler.  These variables contain pointers
548 *  to the lowest and highest addresses in the chunk of memory allocated
549 *  for the interrupt stack.  Since it is unknown whether the stack
550 *  grows up or down (in general), this give the CPU dependent
551 *  code the option of picking the version it wants to use.
552 *
553 *  @note These two variables are required if the macro
554 *        @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
555 *
556 *  Port Specific Information:
557 *
558 *  XXX document implementation including references if appropriate
559 */
560
561/*
562 *  Nothing prevents the porter from declaring more CPU specific variables.
563 *
564 *  Port Specific Information:
565 *
566 *  XXX document implementation including references if appropriate
567 */
568
569/* XXX: if needed, put more variables here */
570
571/**
572 *  @ingroup CPUContext
573 *  The size of the floating point context area.  On some CPUs this
574 *  will not be a "sizeof" because the format of the floating point
575 *  area is not defined -- only the size is.  This is usually on
576 *  CPUs with a "floating point save context" instruction.
577 *
578 *  Port Specific Information:
579 *
580 *  XXX document implementation including references if appropriate
581 */
582#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
583
584/**
585 *  Amount of extra stack (above minimum stack size) required by
586 *  MPCI receive server thread.  Remember that in a multiprocessor
587 *  system this thread must exist and be able to process all directives.
588 *
589 *  Port Specific Information:
590 *
591 *  XXX document implementation including references if appropriate
592 */
593#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
594
595/**
596 *  @ingroup CPUInterrupt
597 *  This defines the number of entries in the @ref _ISR_Vector_table managed
598 *  by RTEMS.
599 *
600 *  Port Specific Information:
601 *
602 *  XXX document implementation including references if appropriate
603 */
604#define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
605
606/**
607 *  @ingroup CPUInterrupt
608 *  This defines the highest interrupt vector number for this port.
609 */
610#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
611
612/**
613 *  @ingroup CPUInterrupt
614 *  This is defined if the port has a special way to report the ISR nesting
615 *  level.  Most ports maintain the variable @a _ISR_Nest_level.
616 */
617#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
618
619/**
620 *  @ingroup CPUContext
621 *  Should be large enough to run all RTEMS tests.  This ensures
622 *  that a "reasonable" small application should not have any problems.
623 *
624 *  Port Specific Information:
625 *
626 *  XXX document implementation including references if appropriate
627 */
628#define CPU_STACK_MINIMUM_SIZE          (1024*4)
629
630/**
631 *  CPU's worst alignment requirement for data types on a byte boundary.  This
632 *  alignment does not take into account the requirements for the stack.
633 *
634 *  Port Specific Information:
635 *
636 *  XXX document implementation including references if appropriate
637 */
638#define CPU_ALIGNMENT              8
639
640/**
641 *  This number corresponds to the byte alignment requirement for the
642 *  heap handler.  This alignment requirement may be stricter than that
643 *  for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
644 *  common for the heap to follow the same alignment requirement as
645 *  @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
646 *  the heap, then this should be set to @ref CPU_ALIGNMENT.
647 *
648 *  @note  This does not have to be a power of 2 although it should be
649 *         a multiple of 2 greater than or equal to 2.  The requirement
650 *         to be a multiple of 2 is because the heap uses the least
651 *         significant field of the front and back flags to indicate
652 *         that a block is in use or free.  So you do not want any odd
653 *         length blocks really putting length data in that bit.
654 *
655 *         On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
656 *         have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
657 *         elements allocated from the heap meet all restrictions.
658 *
659 *  Port Specific Information:
660 *
661 *  XXX document implementation including references if appropriate
662 */
663#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
664
665/**
666 *  This number corresponds to the byte alignment requirement for memory
667 *  buffers allocated by the partition manager.  This alignment requirement
668 *  may be stricter than that for the data types alignment specified by
669 *  @ref CPU_ALIGNMENT.  It is common for the partition to follow the same
670 *  alignment requirement as @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is
671 *  strict enough for the partition, then this should be set to
672 *  @ref CPU_ALIGNMENT.
673 *
674 *  @note  This does not have to be a power of 2.  It does have to
675 *         be greater or equal to than @ref CPU_ALIGNMENT.
676 *
677 *  Port Specific Information:
678 *
679 *  XXX document implementation including references if appropriate
680 */
681#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
682
683/**
684 *  This number corresponds to the byte alignment requirement for the
685 *  stack.  This alignment requirement may be stricter than that for the
686 *  data types alignment specified by @ref CPU_ALIGNMENT.  If the
687 *  @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
688 *  set to 0.
689 *
690 *  @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
691 *
692 *  Port Specific Information:
693 *
694 *  XXX document implementation including references if appropriate
695 */
696#define CPU_STACK_ALIGNMENT        0
697
698/*
699 *  ISR handler macros
700 */
701
702/**
703 *  @ingroup CPUInterrupt
704 *  Support routine to initialize the RTEMS vector table after it is allocated.
705 *
706 *  Port Specific Information:
707 *
708 *  XXX document implementation including references if appropriate
709 */
710#define _CPU_Initialize_vectors()
711
712/**
713 *  @ingroup CPUInterrupt
714 *  Disable all interrupts for an RTEMS critical section.  The previous
715 *  level is returned in @a _isr_cookie.
716 *
717 *  @param[out] _isr_cookie will contain the previous level cookie
718 *
719 *  Port Specific Information:
720 *
721 *  XXX document implementation including references if appropriate
722 */
723#define _CPU_ISR_Disable( _isr_cookie ) \
724  lm32_disable_interrupts( _isr_cookie );
725
726/**
727 *  @ingroup CPUInterrupt
728 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
729 *  This indicates the end of an RTEMS critical section.  The parameter
730 *  @a _isr_cookie is not modified.
731 *
732 *  @param[in] _isr_cookie contain the previous level cookie
733 *
734 *  Port Specific Information:
735 *
736 *  XXX document implementation including references if appropriate
737 */
738#define _CPU_ISR_Enable( _isr_cookie ) \
739  lm32_enable_interrupts( _isr_cookie );
740
741/**
742 *  @ingroup CPUInterrupt
743 *  This temporarily restores the interrupt to @a _isr_cookie before immediately
744 *  disabling them again.  This is used to divide long RTEMS critical
745 *  sections into two or more parts.  The parameter @a _isr_cookie is not
746 *  modified.
747 *
748 *  @param[in] _isr_cookie contain the previous level cookie
749 *
750 *  Port Specific Information:
751 *
752 *  XXX document implementation including references if appropriate
753 */
754#define _CPU_ISR_Flash( _isr_cookie ) \
755  lm32_flash_interrupts( _isr_cookie );
756
757/**
758 *  @ingroup CPUInterrupt
759 *
760 *  This routine and @ref _CPU_ISR_Get_level
761 *  Map the interrupt level in task mode onto the hardware that the CPU
762 *  actually provides.  Currently, interrupt levels which do not
763 *  map onto the CPU in a generic fashion are undefined.  Someday,
764 *  it would be nice if these were "mapped" by the application
765 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
766 *  8 - 255 would be available for bsp/application specific meaning.
767 *  This could be used to manage a programmable interrupt controller
768 *  via the rtems_task_mode directive.
769 *
770 *  Port Specific Information:
771 *
772 *  XXX document implementation including references if appropriate
773 */
774#define _CPU_ISR_Set_level( new_level ) \
775  { \
776    _CPU_ISR_Enable( ( new_level==0 ) ? 1 : 0 ); \
777  }
778
779/**
780 *  @ingroup CPUInterrupt
781 *  Return the current interrupt disable level for this task in
782 *  the format used by the interrupt level portion of the task mode.
783 *
784 *  @note This routine usually must be implemented as a subroutine.
785 *
786 *  Port Specific Information:
787 *
788 *  XXX document implementation including references if appropriate
789 */
790uint32_t   _CPU_ISR_Get_level( void );
791
792/* end of ISR handler macros */
793
794/* Context handler macros */
795
796/**
797 *  @ingroup CPUContext
798 *  Initialize the context to a state suitable for starting a
799 *  task after a context restore operation.  Generally, this
800 *  involves:
801 *
802 *     - setting a starting address
803 *     - preparing the stack
804 *     - preparing the stack and frame pointers
805 *     - setting the proper interrupt level in the context
806 *     - initializing the floating point context
807 *
808 *  This routine generally does not set any unnecessary register
809 *  in the context.  The state of the "general data" registers is
810 *  undefined at task start time.
811 *
812 *  @param[in] _the_context is the context structure to be initialized
813 *  @param[in] _stack_base is the lowest physical address of this task's stack
814 *  @param[in] _size is the size of this task's stack
815 *  @param[in] _isr is the interrupt disable level
816 *  @param[in] _entry_point is the thread's entry point.  This is
817 *         always @a _Thread_Handler
818 *  @param[in] _is_fp is TRUE if the thread is to be a floating
819 *        point thread.  This is typically only used on CPUs where the
820 *        FPU may be easily disabled by software such as on the SPARC
821 *        where the PSR contains an enable FPU bit.
822 *
823 *  Port Specific Information:
824 *
825 *  XXX document implementation including references if appropriate
826 */
827extern char _gp[];
828
829#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
830                                 _isr, _entry_point, _is_fp ) \
831   do { \
832     uint32_t _stack = (uint32_t)(_stack_base) + (_size) - 4; \
833     (_the_context)->gp = (uint32_t)_gp; \
834     (_the_context)->fp = (uint32_t)_stack; \
835     (_the_context)->sp = (uint32_t)_stack; \
836     (_the_context)->ra = (uint32_t)(_entry_point); \
837   } while ( 0 )
838
839/**
840 *  This routine is responsible for somehow restarting the currently
841 *  executing task.  If you are lucky, then all that is necessary
842 *  is restoring the context.  Otherwise, there will need to be
843 *  a special assembly routine which does something special in this
844 *  case.  For many ports, simply adding a label to the restore path
845 *  of @ref _CPU_Context_switch will work.  On other ports, it may be
846 *  possibly to load a few arguments and jump to the restore path. It will
847 *  not work if restarting self conflicts with the stack frame
848 *  assumptions of restoring a context.
849 *
850 *  Port Specific Information:
851 *
852 *  XXX document implementation including references if appropriate
853 */
854#define _CPU_Context_Restart_self( _the_context ) \
855   _CPU_Context_restore( (_the_context) );
856
857/**
858 *  @ingroup CPUContext
859 *  The purpose of this macro is to allow the initial pointer into
860 *  a floating point context area (used to save the floating point
861 *  context) to be at an arbitrary place in the floating point
862 *  context area.
863 *
864 *  This is necessary because some FP units are designed to have
865 *  their context saved as a stack which grows into lower addresses.
866 *  Other FP units can be saved by simply moving registers into offsets
867 *  from the base of the context area.  Finally some FP units provide
868 *  a "dump context" instruction which could fill in from high to low
869 *  or low to high based on the whim of the CPU designers.
870 *
871 *  @param[in] _base is the lowest physical address of the floating point
872 *         context area
873 *  @param[in] _offset is the offset into the floating point area
874 *
875 *  Port Specific Information:
876 *
877 *  XXX document implementation including references if appropriate
878 */
879#define _CPU_Context_Fp_start( _base, _offset )
880#if 0
881   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
882#endif
883
884/**
885 *  This routine initializes the FP context area passed to it to.
886 *  There are a few standard ways in which to initialize the
887 *  floating point context.  The code included for this macro assumes
888 *  that this is a CPU in which a "initial" FP context was saved into
889 *  @a _CPU_Null_fp_context and it simply copies it to the destination
890 *  context passed to it.
891 *
892 *  Other floating point context save/restore models include:
893 *    -# not doing anything, and
894 *    -# putting a "null FP status word" in the correct place in the FP context.
895 *
896 *  @param[in] _destination is the floating point context area
897 *
898 *  Port Specific Information:
899 *
900 *  XXX document implementation including references if appropriate
901 */
902#define _CPU_Context_Initialize_fp( _destination )
903#if 0
904  { \
905   *(*(_destination)) = _CPU_Null_fp_context; \
906  }
907#endif
908
909/* end of Context handler macros */
910
911/* Fatal Error manager macros */
912
913/**
914 *  This routine copies _error into a known place -- typically a stack
915 *  location or a register, optionally disables interrupts, and
916 *  halts/stops the CPU.
917 *
918 *  Port Specific Information:
919 *
920 *  XXX document implementation including references if appropriate
921 */
922#define _CPU_Fatal_halt( _error ) \
923  { \
924  }
925
926/* end of Fatal Error manager macros */
927
928/* Bitfield handler macros */
929
930/**
931 *  @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
932 *
933 *  This set of routines are used to implement fast searches for
934 *  the most important ready task.
935 */
936
937/**
938 *  @ingroup CPUBitfield
939 *  This definition is set to TRUE if the port uses the generic bitfield
940 *  manipulation implementation.
941 */
942#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
943
944/**
945 *  @ingroup CPUBitfield
946 *  This definition is set to TRUE if the port uses the data tables provided
947 *  by the generic bitfield manipulation implementation.
948 *  This can occur when actually using the generic bitfield manipulation
949 *  implementation or when implementing the same algorithm in assembly
950 *  language for improved performance.  It is unlikely that a port will use
951 *  the data if it has a bitfield scan instruction.
952 */
953#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
954
955/**
956 *  @ingroup CPUBitfield
957 *  This routine sets @a _output to the bit number of the first bit
958 *  set in @a _value.  @a _value is of CPU dependent type
959 *  @a Priority_bit_map_Control.  This type may be either 16 or 32 bits
960 *  wide although only the 16 least significant bits will be used.
961 *
962 *  There are a number of variables in using a "find first bit" type
963 *  instruction.
964 *
965 *    -# What happens when run on a value of zero?
966 *    -# Bits may be numbered from MSB to LSB or vice-versa.
967 *    -# The numbering may be zero or one based.
968 *    -# The "find first bit" instruction may search from MSB or LSB.
969 *
970 *  RTEMS guarantees that (1) will never happen so it is not a concern.
971 *  (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
972 *  @ref _CPU_Priority_bits_index.  These three form a set of routines
973 *  which must logically operate together.  Bits in the _value are
974 *  set and cleared based on masks built by @ref _CPU_Priority_Mask.
975 *  The basic major and minor values calculated by @ref _Priority_Major
976 *  and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
977 *  to properly range between the values returned by the "find first bit"
978 *  instruction.  This makes it possible for @ref _Priority_Get_highest to
979 *  calculate the major and directly index into the minor table.
980 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
981 *  is the first bit found.
982 *
983 *  This entire "find first bit" and mapping process depends heavily
984 *  on the manner in which a priority is broken into a major and minor
985 *  components with the major being the 4 MSB of a priority and minor
986 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
987 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
988 *  to the lowest priority.
989 *
990 *  If your CPU does not have a "find first bit" instruction, then
991 *  there are ways to make do without it.  Here are a handful of ways
992 *  to implement this in software:
993 *
994@verbatim
995      - a series of 16 bit test instructions
996      - a "binary search using if's"
997      - _number = 0
998        if _value > 0x00ff
999          _value >>=8
1000          _number = 8;
1001
1002        if _value > 0x0000f
1003          _value >=8
1004          _number += 4
1005
1006        _number += bit_set_table[ _value ]
1007@endverbatim
1008
1009 *    where bit_set_table[ 16 ] has values which indicate the first
1010 *      bit set
1011 *
1012 *  @param[in] _value is the value to be scanned
1013 *  @param[in] _output is the first bit set
1014 *
1015 *  Port Specific Information:
1016 *
1017 *  XXX document implementation including references if appropriate
1018 */
1019
1020#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1021#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
1022  { \
1023    (_output) = 0;   /* do something to prevent warnings */ \
1024  }
1025#endif
1026
1027/* end of Bitfield handler macros */
1028
1029/**
1030 *  This routine builds the mask which corresponds to the bit fields
1031 *  as searched by @ref _CPU_Bitfield_Find_first_bit.  See the discussion
1032 *  for that routine.
1033 *
1034 *  Port Specific Information:
1035 *
1036 *  XXX document implementation including references if appropriate
1037 */
1038#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1039
1040#define _CPU_Priority_Mask( _bit_number ) \
1041  ( 1 << (_bit_number) )
1042
1043#endif
1044
1045/**
1046 *  @ingroup CPUBitfield
1047 *  This routine translates the bit numbers returned by
1048 *  @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
1049 *  a major or minor component of a priority.  See the discussion
1050 *  for that routine.
1051 *
1052 *  @param[in] _priority is the major or minor number to translate
1053 *
1054 *  Port Specific Information:
1055 *
1056 *  XXX document implementation including references if appropriate
1057 */
1058#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1059
1060#define _CPU_Priority_bits_index( _priority ) \
1061  (_priority)
1062
1063#endif
1064
1065/* end of Priority handler macros */
1066
1067/* functions */
1068
1069/**
1070 *  This routine performs CPU dependent initialization.
1071 *
1072 *  Port Specific Information:
1073 *
1074 *  XXX document implementation including references if appropriate
1075 */
1076void _CPU_Initialize(void);
1077
1078/**
1079 *  @ingroup CPUInterrupt
1080 *  This routine installs a "raw" interrupt handler directly into the
1081 *  processor's vector table.
1082 *
1083 *  @param[in] vector is the vector number
1084 *  @param[in] new_handler is the raw ISR handler to install
1085 *  @param[in] old_handler is the previously installed ISR Handler
1086 *
1087 *  Port Specific Information:
1088 *
1089 *  XXX document implementation including references if appropriate
1090 */
1091void _CPU_ISR_install_raw_handler(
1092  uint32_t    vector,
1093  proc_ptr    new_handler,
1094  proc_ptr   *old_handler
1095);
1096
1097/**
1098 *  @ingroup CPUInterrupt
1099 *  This routine installs an interrupt vector.
1100 *
1101 *  @param[in] vector is the vector number
1102 *  @param[in] new_handler is the RTEMS ISR handler to install
1103 *  @param[in] old_handler is the previously installed ISR Handler
1104 *
1105 *  Port Specific Information:
1106 *
1107 *  XXX document implementation including references if appropriate
1108 */
1109void _CPU_ISR_install_vector(
1110  uint32_t    vector,
1111  proc_ptr    new_handler,
1112  proc_ptr   *old_handler
1113);
1114
1115/**
1116 *  @ingroup CPUInterrupt
1117 *  This routine installs the hardware interrupt stack pointer.
1118 *
1119 *  @note  It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
1120 *         is TRUE.
1121 *
1122 *  Port Specific Information:
1123 *
1124 *  XXX document implementation including references if appropriate
1125 */
1126void _CPU_Install_interrupt_stack( void );
1127
1128/**
1129 *  This routine is the CPU dependent IDLE thread body.
1130 *
1131 *  @note  It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY
1132 *         is TRUE.
1133 *
1134 *  Port Specific Information:
1135 *
1136 *  XXX document implementation including references if appropriate
1137 */
1138void *_CPU_Thread_Idle_body( uintptr_t ignored );
1139
1140/**
1141 *  @ingroup CPUContext
1142 *  This routine switches from the run context to the heir context.
1143 *
1144 *  @param[in] run points to the context of the currently executing task
1145 *  @param[in] heir points to the context of the heir task
1146 *
1147 *  Port Specific Information:
1148 *
1149 *  XXX document implementation including references if appropriate
1150 */
1151void _CPU_Context_switch(
1152  Context_Control  *run,
1153  Context_Control  *heir
1154);
1155
1156/**
1157 *  @ingroup CPUContext
1158 *  This routine is generally used only to restart self in an
1159 *  efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
1160 *
1161 *  @param[in] new_context points to the context to be restored.
1162 *
1163 *  @note May be unnecessary to reload some registers.
1164 *
1165 *  Port Specific Information:
1166 *
1167 *  XXX document implementation including references if appropriate
1168 */
1169void _CPU_Context_restore(
1170  Context_Control *new_context
1171);
1172
1173/**
1174 *  @ingroup CPUContext
1175 *  This routine saves the floating point context passed to it.
1176 *
1177 *  @param[in] fp_context_ptr is a pointer to a pointer to a floating
1178 *  point context area
1179 *
1180 *  @return on output @a *fp_context_ptr will contain the address that
1181 *  should be used with @ref _CPU_Context_restore_fp to restore this context.
1182 *
1183 *  Port Specific Information:
1184 *
1185 *  XXX document implementation including references if appropriate
1186 */
1187void _CPU_Context_save_fp(
1188  Context_Control_fp **fp_context_ptr
1189);
1190
1191/**
1192 *  @ingroup CPUContext
1193 *  This routine restores the floating point context passed to it.
1194 *
1195 *  @param[in] fp_context_ptr is a pointer to a pointer to a floating
1196 *  point context area to restore
1197 *
1198 *  @return on output @a *fp_context_ptr will contain the address that
1199 *  should be used with @ref _CPU_Context_save_fp to save this context.
1200 *
1201 *  Port Specific Information:
1202 *
1203 *  XXX document implementation including references if appropriate
1204 */
1205void _CPU_Context_restore_fp(
1206  Context_Control_fp **fp_context_ptr
1207);
1208
1209/**
1210 *  @ingroup CPUEndian
1211 *  The following routine swaps the endian format of an unsigned int.
1212 *  It must be static because it is referenced indirectly.
1213 *
1214 *  This version will work on any processor, but if there is a better
1215 *  way for your CPU PLEASE use it.  The most common way to do this is to:
1216 *
1217 *     swap least significant two bytes with 16-bit rotate
1218 *     swap upper and lower 16-bits
1219 *     swap most significant two bytes with 16-bit rotate
1220 *
1221 *  Some CPUs have special instructions which swap a 32-bit quantity in
1222 *  a single instruction (e.g. i486).  It is probably best to avoid
1223 *  an "endian swapping control bit" in the CPU.  One good reason is
1224 *  that interrupts would probably have to be disabled to ensure that
1225 *  an interrupt does not try to access the same "chunk" with the wrong
1226 *  endian.  Another good reason is that on some CPUs, the endian bit
1227 *  endianness for ALL fetches -- both code and data -- so the code
1228 *  will be fetched incorrectly.
1229 *
1230 *  @param[in] value is the value to be swapped
1231 *  @return the value after being endian swapped
1232 *
1233 *  Port Specific Information:
1234 *
1235 *  XXX document implementation including references if appropriate
1236 */
1237static inline uint32_t CPU_swap_u32(
1238  uint32_t value
1239)
1240{
1241  uint32_t byte1, byte2, byte3, byte4, swapped;
1242
1243  byte4 = (value >> 24) & 0xff;
1244  byte3 = (value >> 16) & 0xff;
1245  byte2 = (value >> 8)  & 0xff;
1246  byte1 =  value        & 0xff;
1247
1248  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1249  return swapped;
1250}
1251
1252/**
1253 *  @ingroup CPUEndian
1254 *  This routine swaps a 16 bir quantity.
1255 *
1256 *  @param[in] value is the value to be swapped
1257 *  @return the value after being endian swapped
1258 */
1259#define CPU_swap_u16( value ) \
1260  (((value&0xff) << 8) | ((value >> 8)&0xff))
1261
1262#ifdef __cplusplus
1263}
1264#endif
1265
1266#endif
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