source: rtems/cpukit/score/cpu/lm32/rtems/score/cpu.h @ 42e243e

4.104.11
Last change on this file since 42e243e was 42e243e, checked in by Ralf Corsepius <ralf.corsepius@…>, on Dec 4, 2009 at 4:27:21 AM

Whitespace removal.

  • Property mode set to 100644
File size: 41.2 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  This include file contains information pertaining to the XXX
7 *  processor.
8 *
9 *  @note This file is part of a porting template that is intended
10 *  to be used as the starting point when porting RTEMS to a new
11 *  CPU family.  The following needs to be done when using this as
12 *  the starting point for a new port:
13 *
14 *  + Anywhere there is an XXX, it should be replaced
15 *    with information about the CPU family being ported to.
16 *
17 *  + At the end of each comment section, there is a heading which
18 *    says "Port Specific Information:".  When porting to RTEMS,
19 *    add CPU family specific information in this section
20 */
21
22/*
23 *  COPYRIGHT (c) 1989-2008.
24 *  On-Line Applications Research Corporation (OAR).
25 *
26 *  The license and distribution terms for this file may be
27 *  found in the file LICENSE in this distribution or at
28 *  http://www.rtems.com/license/LICENSE.
29 *
30 *  $Id$
31 */
32
33#ifndef _RTEMS_SCORE_CPU_H
34#define _RTEMS_SCORE_CPU_H
35
36#ifdef __cplusplus
37extern "C" {
38#endif
39
40#include <rtems/score/lm32.h>            /* pick up machine definitions */
41#ifndef ASM
42#include <rtems/score/types.h>
43#endif
44
45/* conditional compilation parameters */
46
47/**
48 *  Should the calls to @ref _Thread_Enable_dispatch be inlined?
49 *
50 *  If TRUE, then they are inlined.
51 *  If FALSE, then a subroutine call is made.
52 *
53 *  This conditional is an example of the classic trade-off of size
54 *  versus speed.  Inlining the call (TRUE) typically increases the
55 *  size of RTEMS while speeding up the enabling of dispatching.
56 *
57 *  @note In general, the @ref _Thread_Dispatch_disable_level will
58 *  only be 0 or 1 unless you are in an interrupt handler and that
59 *  interrupt handler invokes the executive.]  When not inlined
60 *  something calls @ref _Thread_Enable_dispatch which in turns calls
61 *  @ref _Thread_Dispatch.  If the enable dispatch is inlined, then
62 *  one subroutine call is avoided entirely.
63 *
64 *  Port Specific Information:
65 *
66 *  XXX document implementation including references if appropriate
67 */
68#define CPU_INLINE_ENABLE_DISPATCH       FALSE
69
70/**
71 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
72 *  be unrolled one time?  In unrolled each iteration of the loop examines
73 *  two "nodes" on the chain being searched.  Otherwise, only one node
74 *  is examined per iteration.
75 *
76 *  If TRUE, then the loops are unrolled.
77 *  If FALSE, then the loops are not unrolled.
78 *
79 *  The primary factor in making this decision is the cost of disabling
80 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
81 *  body of the loop.  On some CPUs, the flash is more expensive than
82 *  one iteration of the loop body.  In this case, it might be desirable
83 *  to unroll the loop.  It is important to note that on some CPUs, this
84 *  code is the longest interrupt disable period in RTEMS.  So it is
85 *  necessary to strike a balance when setting this parameter.
86 *
87 *  Port Specific Information:
88 *
89 *  XXX document implementation including references if appropriate
90 */
91#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
92
93/**
94 *  Does RTEMS manage a dedicated interrupt stack in software?
95 *
96 *  If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
97 *  If FALSE, nothing is done.
98 *
99 *  If the CPU supports a dedicated interrupt stack in hardware,
100 *  then it is generally the responsibility of the BSP to allocate it
101 *  and set it up.
102 *
103 *  If the CPU does not support a dedicated interrupt stack, then
104 *  the porter has two options: (1) execute interrupts on the
105 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
106 *  interrupt stack.
107 *
108 *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
109 *
110 *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
111 *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
112 *  possible that both are FALSE for a particular CPU.  Although it
113 *  is unclear what that would imply about the interrupt processing
114 *  procedure on that CPU.
115 *
116 *  Port Specific Information:
117 *
118 *  XXX document implementation including references if appropriate
119 */
120#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
121
122/**
123 *  Does the CPU follow the simple vectored interrupt model?
124 *
125 *  If TRUE, then RTEMS allocates the vector table it internally manages.
126 *  If FALSE, then the BSP is assumed to allocate and manage the vector
127 *  table
128 *
129 *  Port Specific Information:
130 *
131 *  XXX document implementation including references if appropriate
132 */
133#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
134
135/**
136 *  Does this CPU have hardware support for a dedicated interrupt stack?
137 *
138 *  If TRUE, then it must be installed during initialization.
139 *  If FALSE, then no installation is performed.
140 *
141 *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
142 *
143 *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
144 *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
145 *  possible that both are FALSE for a particular CPU.  Although it
146 *  is unclear what that would imply about the interrupt processing
147 *  procedure on that CPU.
148 *
149 *  Port Specific Information:
150 *
151 *  XXX document implementation including references if appropriate
152 */
153#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
154
155/**
156 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
157 *
158 *  If TRUE, then the memory is allocated during initialization.
159 *  If FALSE, then the memory is allocated during initialization.
160 *
161 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
162 *
163 *  Port Specific Information:
164 *
165 *  XXX document implementation including references if appropriate
166 */
167#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
168
169/**
170 *  Does the RTEMS invoke the user's ISR with the vector number and
171 *  a pointer to the saved interrupt frame (1) or just the vector
172 *  number (0)?
173 *
174 *  Port Specific Information:
175 *
176 *  XXX document implementation including references if appropriate
177 */
178#define CPU_ISR_PASSES_FRAME_POINTER 1
179
180/**
181 *  @def CPU_HARDWARE_FP
182 *
183 *  Does the CPU have hardware floating point?
184 *
185 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
186 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
187 *
188 *  If there is a FP coprocessor such as the i387 or mc68881, then
189 *  the answer is TRUE.
190 *
191 *  The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
192 *  It indicates whether or not this CPU model has FP support.  For
193 *  example, it would be possible to have an i386_nofp CPU model
194 *  which set this to false to indicate that you have an i386 without
195 *  an i387 and wish to leave floating point support out of RTEMS.
196 */
197
198/**
199 *  @def CPU_SOFTWARE_FP
200 *
201 *  Does the CPU have no hardware floating point and GCC provides a
202 *  software floating point implementation which must be context
203 *  switched?
204 *
205 *  This feature conditional is used to indicate whether or not there
206 *  is software implemented floating point that must be context
207 *  switched.  The determination of whether or not this applies
208 *  is very tool specific and the state saved/restored is also
209 *  compiler specific.
210 *
211 *  Port Specific Information:
212 *
213 *  XXX document implementation including references if appropriate
214 */
215#define CPU_HARDWARE_FP     FALSE
216#define CPU_SOFTWARE_FP     FALSE
217
218/**
219 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
220 *
221 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
222 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
223 *
224 *  So far, the only CPUs in which this option has been used are the
225 *  HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
226 *  gcc both implicitly used the floating point registers to perform
227 *  integer multiplies.  Similarly, the PowerPC port of gcc has been
228 *  seen to allocate floating point local variables and touch the FPU
229 *  even when the flow through a subroutine (like vfprintf()) might
230 *  not use floating point formats.
231 *
232 *  If a function which you would not think utilize the FP unit DOES,
233 *  then one can not easily predict which tasks will use the FP hardware.
234 *  In this case, this option should be TRUE.
235 *
236 *  If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
237 *
238 *  Port Specific Information:
239 *
240 *  XXX document implementation including references if appropriate
241 */
242#define CPU_ALL_TASKS_ARE_FP     FALSE
243
244/**
245 *  Should the IDLE task have a floating point context?
246 *
247 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
248 *  and it has a floating point context which is switched in and out.
249 *  If FALSE, then the IDLE task does not have a floating point context.
250 *
251 *  Setting this to TRUE negatively impacts the time required to preempt
252 *  the IDLE task from an interrupt because the floating point context
253 *  must be saved as part of the preemption.
254 *
255 *  Port Specific Information:
256 *
257 *  XXX document implementation including references if appropriate
258 */
259#define CPU_IDLE_TASK_IS_FP      FALSE
260
261/**
262 *  Should the saving of the floating point registers be deferred
263 *  until a context switch is made to another different floating point
264 *  task?
265 *
266 *  If TRUE, then the floating point context will not be stored until
267 *  necessary.  It will remain in the floating point registers and not
268 *  disturned until another floating point task is switched to.
269 *
270 *  If FALSE, then the floating point context is saved when a floating
271 *  point task is switched out and restored when the next floating point
272 *  task is restored.  The state of the floating point registers between
273 *  those two operations is not specified.
274 *
275 *  If the floating point context does NOT have to be saved as part of
276 *  interrupt dispatching, then it should be safe to set this to TRUE.
277 *
278 *  Setting this flag to TRUE results in using a different algorithm
279 *  for deciding when to save and restore the floating point context.
280 *  The deferred FP switch algorithm minimizes the number of times
281 *  the FP context is saved and restored.  The FP context is not saved
282 *  until a context switch is made to another, different FP task.
283 *  Thus in a system with only one FP task, the FP context will never
284 *  be saved or restored.
285 *
286 *  Port Specific Information:
287 *
288 *  XXX document implementation including references if appropriate
289 */
290#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
291
292/**
293 *  Does this port provide a CPU dependent IDLE task implementation?
294 *
295 *  If TRUE, then the routine @ref _CPU_Thread_Idle_body
296 *  must be provided and is the default IDLE thread body instead of
297 *  @ref _CPU_Thread_Idle_body.
298 *
299 *  If FALSE, then use the generic IDLE thread body if the BSP does
300 *  not provide one.
301 *
302 *  This is intended to allow for supporting processors which have
303 *  a low power or idle mode.  When the IDLE thread is executed, then
304 *  the CPU can be powered down.
305 *
306 *  The order of precedence for selecting the IDLE thread body is:
307 *
308 *    -#  BSP provided
309 *    -#  CPU dependent (if provided)
310 *    -#  generic (if no BSP and no CPU dependent)
311 *
312 *  Port Specific Information:
313 *
314 *  XXX document implementation including references if appropriate
315 */
316#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
317
318/**
319 *  Does the stack grow up (toward higher addresses) or down
320 *  (toward lower addresses)?
321 *
322 *  If TRUE, then the grows upward.
323 *  If FALSE, then the grows toward smaller addresses.
324 *
325 *  Port Specific Information:
326 *
327 *  XXX document implementation including references if appropriate
328 */
329#define CPU_STACK_GROWS_UP               FALSE
330
331/**
332 *  The following is the variable attribute used to force alignment
333 *  of critical RTEMS structures.  On some processors it may make
334 *  sense to have these aligned on tighter boundaries than
335 *  the minimum requirements of the compiler in order to have as
336 *  much of the critical data area as possible in a cache line.
337 *
338 *  The placement of this macro in the declaration of the variables
339 *  is based on the syntactically requirements of the GNU C
340 *  "__attribute__" extension.  For example with GNU C, use
341 *  the following to force a structures to a 32 byte boundary.
342 *
343 *      __attribute__ ((aligned (32)))
344 *
345 *  @note Currently only the Priority Bit Map table uses this feature.
346 *        To benefit from using this, the data must be heavily
347 *        used so it will stay in the cache and used frequently enough
348 *        in the executive to justify turning this on.
349 *
350 *  Port Specific Information:
351 *
352 *  XXX document implementation including references if appropriate
353 */
354#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (8)))
355
356/**
357 *  @defgroup CPUEndian Processor Dependent Endianness Support
358 *
359 *  This group assists in issues related to processor endianness.
360 */
361
362/**
363 *  @ingroup CPUEndian
364 *  Define what is required to specify how the network to host conversion
365 *  routines are handled.
366 *
367 *  @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
368 *  same values.
369 *
370 *  @see CPU_LITTLE_ENDIAN
371 *
372 *  Port Specific Information:
373 *
374 *  XXX document implementation including references if appropriate
375 */
376#define CPU_BIG_ENDIAN                           TRUE
377
378/**
379 *  @ingroup CPUEndian
380 *  Define what is required to specify how the network to host conversion
381 *  routines are handled.
382 *
383 *  @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
384 *  same values.
385 *
386 *  @see CPU_BIG_ENDIAN
387 *
388 *  Port Specific Information:
389 *
390 *  XXX document implementation including references if appropriate
391 */
392#define CPU_LITTLE_ENDIAN                        FALSE
393
394/**
395 *  @ingroup CPUInterrupt
396 *  The following defines the number of bits actually used in the
397 *  interrupt field of the task mode.  How those bits map to the
398 *  CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
399 *
400 *  Port Specific Information:
401 *
402 *  XXX document implementation including references if appropriate
403 */
404#define CPU_MODES_INTERRUPT_MASK   0x00000001
405
406/*
407 *  Processor defined structures required for cpukit/score.
408 *
409 *  Port Specific Information:
410 *
411 *  XXX document implementation including references if appropriate
412 */
413
414/* may need to put some structures here.  */
415
416/**
417 * @defgroup CPUContext Processor Dependent Context Management
418 *
419 *  From the highest level viewpoint, there are 2 types of context to save.
420 *
421 *     -# Interrupt registers to save
422 *     -# Task level registers to save
423 *
424 *  Since RTEMS handles integer and floating point contexts separately, this
425 *  means we have the following 3 context items:
426 *
427 *     -# task level context stuff::  Context_Control
428 *     -# floating point task stuff:: Context_Control_fp
429 *     -# special interrupt level context :: CPU_Interrupt_frame
430 *
431 *  On some processors, it is cost-effective to save only the callee
432 *  preserved registers during a task context switch.  This means
433 *  that the ISR code needs to save those registers which do not
434 *  persist across function calls.  It is not mandatory to make this
435 *  distinctions between the caller/callee saves registers for the
436 *  purpose of minimizing context saved during task switch and on interrupts.
437 *  If the cost of saving extra registers is minimal, simplicity is the
438 *  choice.  Save the same context on interrupt entry as for tasks in
439 *  this case.
440 *
441 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
442 *  care should be used in designing the context area.
443 *
444 *  On some CPUs with hardware floating point support, the Context_Control_fp
445 *  structure will not be used or it simply consist of an array of a
446 *  fixed number of bytes.   This is done when the floating point context
447 *  is dumped by a "FP save context" type instruction and the format
448 *  is not really defined by the CPU.  In this case, there is no need
449 *  to figure out the exact format -- only the size.  Of course, although
450 *  this is enough information for RTEMS, it is probably not enough for
451 *  a debugger such as gdb.  But that is another problem.
452 *
453 *  Port Specific Information:
454 *
455 *  XXX document implementation including references if appropriate
456 */
457
458/**
459 *  @ingroup CPUContext Management
460 *  This defines the minimal set of integer and processor state registers
461 *  that must be saved during a voluntary context switch from one thread
462 *  to another.
463 */
464typedef struct {
465  uint32_t r11;
466  uint32_t r12;
467  uint32_t r13;
468  uint32_t r14;
469  uint32_t r15;
470  uint32_t r16;
471  uint32_t r17;
472  uint32_t r18;
473  uint32_t r19;
474  uint32_t r20;
475  uint32_t r21;
476  uint32_t r22;
477  uint32_t r23;
478  uint32_t r24;
479  uint32_t r25;
480  uint32_t gp;
481  uint32_t fp;
482  uint32_t sp;
483  uint32_t ra;
484  uint32_t ie;
485  uint32_t epc;
486} Context_Control;
487
488/**
489 *  @ingroup CPUContext Management
490 *
491 *  This macro returns the stack pointer associated with @a _context.
492 *
493 *  @param[in] _context is the thread context area to access
494 *
495 *  @return This method returns the stack pointer.
496 */
497#define _CPU_Context_Get_SP( _context ) \
498  (_context)->sp
499
500/**
501 *  @ingroup CPUContext Management
502 *  This defines the complete set of floating point registers that must
503 *  be saved during any context switch from one thread to another.
504 */
505typedef struct {
506} Context_Control_fp;
507
508/**
509 *  @ingroup CPUContext Management
510 *  This defines the set of integer and processor state registers that must
511 *  be saved during an interrupt.  This set does not include any which are
512 *  in @ref Context_Control.
513 */
514typedef struct {
515  uint32_t r1;
516  uint32_t r2;
517  uint32_t r3;
518  uint32_t r4;
519  uint32_t r5;
520  uint32_t r6;
521  uint32_t r7;
522  uint32_t r8;
523  uint32_t r9;
524  uint32_t r10;
525  uint32_t ra;
526  uint32_t ba;
527  uint32_t ea;
528} CPU_Interrupt_frame;
529
530/**
531 *  This variable is optional.  It is used on CPUs on which it is difficult
532 *  to generate an "uninitialized" FP context.  It is filled in by
533 *  @ref _CPU_Initialize and copied into the task's FP context area during
534 *  @ref _CPU_Context_Initialize.
535 *
536 *  Port Specific Information:
537 *
538 *  XXX document implementation including references if appropriate
539 */
540#if 0
541SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
542#endif
543
544/**
545 *  @defgroup CPUInterrupt Processor Dependent Interrupt Management
546 *
547 *  On some CPUs, RTEMS supports a software managed interrupt stack.
548 *  This stack is allocated by the Interrupt Manager and the switch
549 *  is performed in @ref _ISR_Handler.  These variables contain pointers
550 *  to the lowest and highest addresses in the chunk of memory allocated
551 *  for the interrupt stack.  Since it is unknown whether the stack
552 *  grows up or down (in general), this give the CPU dependent
553 *  code the option of picking the version it wants to use.
554 *
555 *  @note These two variables are required if the macro
556 *        @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
557 *
558 *  Port Specific Information:
559 *
560 *  XXX document implementation including references if appropriate
561 */
562
563/**
564 *  @ingroup CPUInterrupt
565 *  This variable points to the lowest physical address of the interrupt
566 *  stack.
567 */
568SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
569
570/**
571 *  @ingroup CPUInterrupt
572 *  This variable points to the lowest physical address of the interrupt
573 *  stack.
574 */
575SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
576
577/*
578 *  Nothing prevents the porter from declaring more CPU specific variables.
579 *
580 *  Port Specific Information:
581 *
582 *  XXX document implementation including references if appropriate
583 */
584
585/* XXX: if needed, put more variables here */
586
587/**
588 *  @ingroup CPUContext
589 *  The size of the floating point context area.  On some CPUs this
590 *  will not be a "sizeof" because the format of the floating point
591 *  area is not defined -- only the size is.  This is usually on
592 *  CPUs with a "floating point save context" instruction.
593 *
594 *  Port Specific Information:
595 *
596 *  XXX document implementation including references if appropriate
597 */
598#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
599
600/**
601 *  Amount of extra stack (above minimum stack size) required by
602 *  MPCI receive server thread.  Remember that in a multiprocessor
603 *  system this thread must exist and be able to process all directives.
604 *
605 *  Port Specific Information:
606 *
607 *  XXX document implementation including references if appropriate
608 */
609#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
610
611/**
612 *  @ingroup CPUInterrupt
613 *  This defines the number of entries in the @ref _ISR_Vector_table managed
614 *  by RTEMS.
615 *
616 *  Port Specific Information:
617 *
618 *  XXX document implementation including references if appropriate
619 */
620#define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
621
622/**
623 *  @ingroup CPUInterrupt
624 *  This defines the highest interrupt vector number for this port.
625 */
626#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
627
628/**
629 *  @ingroup CPUInterrupt
630 *  This is defined if the port has a special way to report the ISR nesting
631 *  level.  Most ports maintain the variable @a _ISR_Nest_level.
632 */
633#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
634
635/**
636 *  @ingroup CPUContext
637 *  Should be large enough to run all RTEMS tests.  This ensures
638 *  that a "reasonable" small application should not have any problems.
639 *
640 *  Port Specific Information:
641 *
642 *  XXX document implementation including references if appropriate
643 */
644#define CPU_STACK_MINIMUM_SIZE          (1024*4)
645
646/**
647 *  CPU's worst alignment requirement for data types on a byte boundary.  This
648 *  alignment does not take into account the requirements for the stack.
649 *
650 *  Port Specific Information:
651 *
652 *  XXX document implementation including references if appropriate
653 */
654#define CPU_ALIGNMENT              8
655
656/**
657 *  This number corresponds to the byte alignment requirement for the
658 *  heap handler.  This alignment requirement may be stricter than that
659 *  for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
660 *  common for the heap to follow the same alignment requirement as
661 *  @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
662 *  the heap, then this should be set to @ref CPU_ALIGNMENT.
663 *
664 *  @note  This does not have to be a power of 2 although it should be
665 *         a multiple of 2 greater than or equal to 2.  The requirement
666 *         to be a multiple of 2 is because the heap uses the least
667 *         significant field of the front and back flags to indicate
668 *         that a block is in use or free.  So you do not want any odd
669 *         length blocks really putting length data in that bit.
670 *
671 *         On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
672 *         have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
673 *         elements allocated from the heap meet all restrictions.
674 *
675 *  Port Specific Information:
676 *
677 *  XXX document implementation including references if appropriate
678 */
679#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
680
681/**
682 *  This number corresponds to the byte alignment requirement for memory
683 *  buffers allocated by the partition manager.  This alignment requirement
684 *  may be stricter than that for the data types alignment specified by
685 *  @ref CPU_ALIGNMENT.  It is common for the partition to follow the same
686 *  alignment requirement as @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is
687 *  strict enough for the partition, then this should be set to
688 *  @ref CPU_ALIGNMENT.
689 *
690 *  @note  This does not have to be a power of 2.  It does have to
691 *         be greater or equal to than @ref CPU_ALIGNMENT.
692 *
693 *  Port Specific Information:
694 *
695 *  XXX document implementation including references if appropriate
696 */
697#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
698
699/**
700 *  This number corresponds to the byte alignment requirement for the
701 *  stack.  This alignment requirement may be stricter than that for the
702 *  data types alignment specified by @ref CPU_ALIGNMENT.  If the
703 *  @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
704 *  set to 0.
705 *
706 *  @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
707 *
708 *  Port Specific Information:
709 *
710 *  XXX document implementation including references if appropriate
711 */
712#define CPU_STACK_ALIGNMENT        0
713
714/*
715 *  ISR handler macros
716 */
717
718/**
719 *  @ingroup CPUInterrupt
720 *  Support routine to initialize the RTEMS vector table after it is allocated.
721 *
722 *  Port Specific Information:
723 *
724 *  XXX document implementation including references if appropriate
725 */
726#define _CPU_Initialize_vectors()
727
728/**
729 *  @ingroup CPUInterrupt
730 *  Disable all interrupts for an RTEMS critical section.  The previous
731 *  level is returned in @a _isr_cookie.
732 *
733 *  @param[out] _isr_cookie will contain the previous level cookie
734 *
735 *  Port Specific Information:
736 *
737 *  XXX document implementation including references if appropriate
738 */
739#define _CPU_ISR_Disable( _isr_cookie ) \
740  lm32_disable_interrupts( _isr_cookie );
741
742/**
743 *  @ingroup CPUInterrupt
744 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
745 *  This indicates the end of an RTEMS critical section.  The parameter
746 *  @a _isr_cookie is not modified.
747 *
748 *  @param[in] _isr_cookie contain the previous level cookie
749 *
750 *  Port Specific Information:
751 *
752 *  XXX document implementation including references if appropriate
753 */
754#define _CPU_ISR_Enable( _isr_cookie ) \
755  lm32_enable_interrupts( _isr_cookie );
756
757/**
758 *  @ingroup CPUInterrupt
759 *  This temporarily restores the interrupt to @a _isr_cookie before immediately
760 *  disabling them again.  This is used to divide long RTEMS critical
761 *  sections into two or more parts.  The parameter @a _isr_cookie is not
762 *  modified.
763 *
764 *  @param[in] _isr_cookie contain the previous level cookie
765 *
766 *  Port Specific Information:
767 *
768 *  XXX document implementation including references if appropriate
769 */
770#define _CPU_ISR_Flash( _isr_cookie ) \
771  lm32_flash_interrupts( _isr_cookie );
772
773/**
774 *  @ingroup CPUInterrupt
775 *
776 *  This routine and @ref _CPU_ISR_Get_level
777 *  Map the interrupt level in task mode onto the hardware that the CPU
778 *  actually provides.  Currently, interrupt levels which do not
779 *  map onto the CPU in a generic fashion are undefined.  Someday,
780 *  it would be nice if these were "mapped" by the application
781 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
782 *  8 - 255 would be available for bsp/application specific meaning.
783 *  This could be used to manage a programmable interrupt controller
784 *  via the rtems_task_mode directive.
785 *
786 *  Port Specific Information:
787 *
788 *  XXX document implementation including references if appropriate
789 */
790#define _CPU_ISR_Set_level( new_level ) \
791  { \
792    _CPU_ISR_Enable( ( new_level==0 ) ? 1 : 0 ); \
793  }
794
795/**
796 *  @ingroup CPUInterrupt
797 *  Return the current interrupt disable level for this task in
798 *  the format used by the interrupt level portion of the task mode.
799 *
800 *  @note This routine usually must be implemented as a subroutine.
801 *
802 *  Port Specific Information:
803 *
804 *  XXX document implementation including references if appropriate
805 */
806uint32_t   _CPU_ISR_Get_level( void );
807
808/* end of ISR handler macros */
809
810/* Context handler macros */
811
812/**
813 *  @ingroup CPUContext
814 *  Initialize the context to a state suitable for starting a
815 *  task after a context restore operation.  Generally, this
816 *  involves:
817 *
818 *     - setting a starting address
819 *     - preparing the stack
820 *     - preparing the stack and frame pointers
821 *     - setting the proper interrupt level in the context
822 *     - initializing the floating point context
823 *
824 *  This routine generally does not set any unnecessary register
825 *  in the context.  The state of the "general data" registers is
826 *  undefined at task start time.
827 *
828 *  @param[in] _the_context is the context structure to be initialized
829 *  @param[in] _stack_base is the lowest physical address of this task's stack
830 *  @param[in] _size is the size of this task's stack
831 *  @param[in] _isr is the interrupt disable level
832 *  @param[in] _entry_point is the thread's entry point.  This is
833 *         always @a _Thread_Handler
834 *  @param[in] _is_fp is TRUE if the thread is to be a floating
835 *        point thread.  This is typically only used on CPUs where the
836 *        FPU may be easily disabled by software such as on the SPARC
837 *        where the PSR contains an enable FPU bit.
838 *
839 *  Port Specific Information:
840 *
841 *  XXX document implementation including references if appropriate
842 */
843#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
844                                 _isr, _entry_point, _is_fp ) \
845   do { \
846     extern char _gp[]; \
847     uint32_t _stack = (uint32_t)(_stack_base) + (_size) - 4; \
848     (_the_context)->gp = (void *)_gp; \
849     (_the_context)->fp = (void *)_stack; \
850     (_the_context)->sp = (void *)_stack; \
851     (_the_context)->ra = (void *)(_entry_point); \
852   } while ( 0 )
853
854/**
855 *  This routine is responsible for somehow restarting the currently
856 *  executing task.  If you are lucky, then all that is necessary
857 *  is restoring the context.  Otherwise, there will need to be
858 *  a special assembly routine which does something special in this
859 *  case.  For many ports, simply adding a label to the restore path
860 *  of @ref _CPU_Context_switch will work.  On other ports, it may be
861 *  possibly to load a few arguments and jump to the restore path. It will
862 *  not work if restarting self conflicts with the stack frame
863 *  assumptions of restoring a context.
864 *
865 *  Port Specific Information:
866 *
867 *  XXX document implementation including references if appropriate
868 */
869#define _CPU_Context_Restart_self( _the_context ) \
870   _CPU_Context_restore( (_the_context) );
871
872/**
873 *  @ingroup CPUContext
874 *  The purpose of this macro is to allow the initial pointer into
875 *  a floating point context area (used to save the floating point
876 *  context) to be at an arbitrary place in the floating point
877 *  context area.
878 *
879 *  This is necessary because some FP units are designed to have
880 *  their context saved as a stack which grows into lower addresses.
881 *  Other FP units can be saved by simply moving registers into offsets
882 *  from the base of the context area.  Finally some FP units provide
883 *  a "dump context" instruction which could fill in from high to low
884 *  or low to high based on the whim of the CPU designers.
885 *
886 *  @param[in] _base is the lowest physical address of the floating point
887 *         context area
888 *  @param[in] _offset is the offset into the floating point area
889 *
890 *  Port Specific Information:
891 *
892 *  XXX document implementation including references if appropriate
893 */
894#define _CPU_Context_Fp_start( _base, _offset )
895#if 0
896   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
897#endif
898
899/**
900 *  This routine initializes the FP context area passed to it to.
901 *  There are a few standard ways in which to initialize the
902 *  floating point context.  The code included for this macro assumes
903 *  that this is a CPU in which a "initial" FP context was saved into
904 *  @a _CPU_Null_fp_context and it simply copies it to the destination
905 *  context passed to it.
906 *
907 *  Other floating point context save/restore models include:
908 *    -# not doing anything, and
909 *    -# putting a "null FP status word" in the correct place in the FP context.
910 *
911 *  @param[in] _destination is the floating point context area
912 *
913 *  Port Specific Information:
914 *
915 *  XXX document implementation including references if appropriate
916 */
917#define _CPU_Context_Initialize_fp( _destination )
918#if 0
919  { \
920   *(*(_destination)) = _CPU_Null_fp_context; \
921  }
922#endif
923
924/* end of Context handler macros */
925
926/* Fatal Error manager macros */
927
928/**
929 *  This routine copies _error into a known place -- typically a stack
930 *  location or a register, optionally disables interrupts, and
931 *  halts/stops the CPU.
932 *
933 *  Port Specific Information:
934 *
935 *  XXX document implementation including references if appropriate
936 */
937#define _CPU_Fatal_halt( _error ) \
938  { \
939  }
940
941/* end of Fatal Error manager macros */
942
943/* Bitfield handler macros */
944
945/**
946 *  @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
947 *
948 *  This set of routines are used to implement fast searches for
949 *  the most important ready task.
950 */
951
952/**
953 *  @ingroup CPUBitfield
954 *  This definition is set to TRUE if the port uses the generic bitfield
955 *  manipulation implementation.
956 */
957#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
958
959/**
960 *  @ingroup CPUBitfield
961 *  This definition is set to TRUE if the port uses the data tables provided
962 *  by the generic bitfield manipulation implementation.
963 *  This can occur when actually using the generic bitfield manipulation
964 *  implementation or when implementing the same algorithm in assembly
965 *  language for improved performance.  It is unlikely that a port will use
966 *  the data if it has a bitfield scan instruction.
967 */
968#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
969
970/**
971 *  @ingroup CPUBitfield
972 *  This routine sets @a _output to the bit number of the first bit
973 *  set in @a _value.  @a _value is of CPU dependent type
974 *  @a Priority_Bit_map_control.  This type may be either 16 or 32 bits
975 *  wide although only the 16 least significant bits will be used.
976 *
977 *  There are a number of variables in using a "find first bit" type
978 *  instruction.
979 *
980 *    -# What happens when run on a value of zero?
981 *    -# Bits may be numbered from MSB to LSB or vice-versa.
982 *    -# The numbering may be zero or one based.
983 *    -# The "find first bit" instruction may search from MSB or LSB.
984 *
985 *  RTEMS guarantees that (1) will never happen so it is not a concern.
986 *  (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
987 *  @ref _CPU_Priority_bits_index.  These three form a set of routines
988 *  which must logically operate together.  Bits in the _value are
989 *  set and cleared based on masks built by @ref _CPU_Priority_Mask.
990 *  The basic major and minor values calculated by @ref _Priority_Major
991 *  and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
992 *  to properly range between the values returned by the "find first bit"
993 *  instruction.  This makes it possible for @ref _Priority_Get_highest to
994 *  calculate the major and directly index into the minor table.
995 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
996 *  is the first bit found.
997 *
998 *  This entire "find first bit" and mapping process depends heavily
999 *  on the manner in which a priority is broken into a major and minor
1000 *  components with the major being the 4 MSB of a priority and minor
1001 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
1002 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
1003 *  to the lowest priority.
1004 *
1005 *  If your CPU does not have a "find first bit" instruction, then
1006 *  there are ways to make do without it.  Here are a handful of ways
1007 *  to implement this in software:
1008 *
1009@verbatim
1010      - a series of 16 bit test instructions
1011      - a "binary search using if's"
1012      - _number = 0
1013        if _value > 0x00ff
1014          _value >>=8
1015          _number = 8;
1016
1017        if _value > 0x0000f
1018          _value >=8
1019          _number += 4
1020
1021        _number += bit_set_table[ _value ]
1022@endverbatim
1023
1024 *    where bit_set_table[ 16 ] has values which indicate the first
1025 *      bit set
1026 *
1027 *  @param[in] _value is the value to be scanned
1028 *  @param[in] _output is the first bit set
1029 *
1030 *  Port Specific Information:
1031 *
1032 *  XXX document implementation including references if appropriate
1033 */
1034
1035#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1036#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
1037  { \
1038    (_output) = 0;   /* do something to prevent warnings */ \
1039  }
1040#endif
1041
1042/* end of Bitfield handler macros */
1043
1044/**
1045 *  This routine builds the mask which corresponds to the bit fields
1046 *  as searched by @ref _CPU_Bitfield_Find_first_bit.  See the discussion
1047 *  for that routine.
1048 *
1049 *  Port Specific Information:
1050 *
1051 *  XXX document implementation including references if appropriate
1052 */
1053#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1054
1055#define _CPU_Priority_Mask( _bit_number ) \
1056  ( 1 << (_bit_number) )
1057
1058#endif
1059
1060/**
1061 *  @ingroup CPUBitfield
1062 *  This routine translates the bit numbers returned by
1063 *  @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
1064 *  a major or minor component of a priority.  See the discussion
1065 *  for that routine.
1066 *
1067 *  @param[in] _priority is the major or minor number to translate
1068 *
1069 *  Port Specific Information:
1070 *
1071 *  XXX document implementation including references if appropriate
1072 */
1073#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1074
1075#define _CPU_Priority_bits_index( _priority ) \
1076  (_priority)
1077
1078#endif
1079
1080/* end of Priority handler macros */
1081
1082/* functions */
1083
1084/**
1085 *  This routine performs CPU dependent initialization.
1086 *
1087 *  Port Specific Information:
1088 *
1089 *  XXX document implementation including references if appropriate
1090 */
1091void _CPU_Initialize(void);
1092
1093/**
1094 *  @ingroup CPUInterrupt
1095 *  This routine installs a "raw" interrupt handler directly into the
1096 *  processor's vector table.
1097 *
1098 *  @param[in] vector is the vector number
1099 *  @param[in] new_handler is the raw ISR handler to install
1100 *  @param[in] old_handler is the previously installed ISR Handler
1101 *
1102 *  Port Specific Information:
1103 *
1104 *  XXX document implementation including references if appropriate
1105 */
1106void _CPU_ISR_install_raw_handler(
1107  uint32_t    vector,
1108  proc_ptr    new_handler,
1109  proc_ptr   *old_handler
1110);
1111
1112/**
1113 *  @ingroup CPUInterrupt
1114 *  This routine installs an interrupt vector.
1115 *
1116 *  @param[in] vector is the vector number
1117 *  @param[in] new_handler is the RTEMS ISR handler to install
1118 *  @param[in] old_handler is the previously installed ISR Handler
1119 *
1120 *  Port Specific Information:
1121 *
1122 *  XXX document implementation including references if appropriate
1123 */
1124void _CPU_ISR_install_vector(
1125  uint32_t    vector,
1126  proc_ptr    new_handler,
1127  proc_ptr   *old_handler
1128);
1129
1130/**
1131 *  @ingroup CPUInterrupt
1132 *  This routine installs the hardware interrupt stack pointer.
1133 *
1134 *  @note  It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
1135 *         is TRUE.
1136 *
1137 *  Port Specific Information:
1138 *
1139 *  XXX document implementation including references if appropriate
1140 */
1141void _CPU_Install_interrupt_stack( void );
1142
1143/**
1144 *  This routine is the CPU dependent IDLE thread body.
1145 *
1146 *  @note  It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY
1147 *         is TRUE.
1148 *
1149 *  Port Specific Information:
1150 *
1151 *  XXX document implementation including references if appropriate
1152 */
1153void *_CPU_Thread_Idle_body( uintptr_t ignored );
1154
1155/**
1156 *  @ingroup CPUContext
1157 *  This routine switches from the run context to the heir context.
1158 *
1159 *  @param[in] run points to the context of the currently executing task
1160 *  @param[in] heir points to the context of the heir task
1161 *
1162 *  Port Specific Information:
1163 *
1164 *  XXX document implementation including references if appropriate
1165 */
1166void _CPU_Context_switch(
1167  Context_Control  *run,
1168  Context_Control  *heir
1169);
1170
1171/**
1172 *  @ingroup CPUContext
1173 *  This routine is generally used only to restart self in an
1174 *  efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
1175 *
1176 *  @param[in] new_context points to the context to be restored.
1177 *
1178 *  @note May be unnecessary to reload some registers.
1179 *
1180 *  Port Specific Information:
1181 *
1182 *  XXX document implementation including references if appropriate
1183 */
1184void _CPU_Context_restore(
1185  Context_Control *new_context
1186);
1187
1188/**
1189 *  @ingroup CPUContext
1190 *  This routine saves the floating point context passed to it.
1191 *
1192 *  @param[in] fp_context_ptr is a pointer to a pointer to a floating
1193 *  point context area
1194 *
1195 *  @return on output @a *fp_context_ptr will contain the address that
1196 *  should be used with @ref _CPU_Context_restore_fp to restore this context.
1197 *
1198 *  Port Specific Information:
1199 *
1200 *  XXX document implementation including references if appropriate
1201 */
1202void _CPU_Context_save_fp(
1203  Context_Control_fp **fp_context_ptr
1204);
1205
1206/**
1207 *  @ingroup CPUContext
1208 *  This routine restores the floating point context passed to it.
1209 *
1210 *  @param[in] fp_context_ptr is a pointer to a pointer to a floating
1211 *  point context area to restore
1212 *
1213 *  @return on output @a *fp_context_ptr will contain the address that
1214 *  should be used with @ref _CPU_Context_save_fp to save this context.
1215 *
1216 *  Port Specific Information:
1217 *
1218 *  XXX document implementation including references if appropriate
1219 */
1220void _CPU_Context_restore_fp(
1221  Context_Control_fp **fp_context_ptr
1222);
1223
1224/**
1225 *  @ingroup CPUEndian
1226 *  The following routine swaps the endian format of an unsigned int.
1227 *  It must be static because it is referenced indirectly.
1228 *
1229 *  This version will work on any processor, but if there is a better
1230 *  way for your CPU PLEASE use it.  The most common way to do this is to:
1231 *
1232 *     swap least significant two bytes with 16-bit rotate
1233 *     swap upper and lower 16-bits
1234 *     swap most significant two bytes with 16-bit rotate
1235 *
1236 *  Some CPUs have special instructions which swap a 32-bit quantity in
1237 *  a single instruction (e.g. i486).  It is probably best to avoid
1238 *  an "endian swapping control bit" in the CPU.  One good reason is
1239 *  that interrupts would probably have to be disabled to ensure that
1240 *  an interrupt does not try to access the same "chunk" with the wrong
1241 *  endian.  Another good reason is that on some CPUs, the endian bit
1242 *  endianness for ALL fetches -- both code and data -- so the code
1243 *  will be fetched incorrectly.
1244 *
1245 *  @param[in] value is the value to be swapped
1246 *  @return the value after being endian swapped
1247 *
1248 *  Port Specific Information:
1249 *
1250 *  XXX document implementation including references if appropriate
1251 */
1252static inline uint32_t CPU_swap_u32(
1253  uint32_t value
1254)
1255{
1256  uint32_t byte1, byte2, byte3, byte4, swapped;
1257
1258  byte4 = (value >> 24) & 0xff;
1259  byte3 = (value >> 16) & 0xff;
1260  byte2 = (value >> 8)  & 0xff;
1261  byte1 =  value        & 0xff;
1262
1263  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1264  return swapped;
1265}
1266
1267/**
1268 *  @ingroup CPUEndian
1269 *  This routine swaps a 16 bir quantity.
1270 *
1271 *  @param[in] value is the value to be swapped
1272 *  @return the value after being endian swapped
1273 */
1274#define CPU_swap_u16( value ) \
1275  (((value&0xff) << 8) | ((value >> 8)&0xff))
1276
1277#ifdef __cplusplus
1278}
1279#endif
1280
1281#endif
Note: See TracBrowser for help on using the repository browser.